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Commit 31a49c4bf8f964b7a9897baa889916d71b51d9c1

Authored by Yoshihiro Shimoda
Committed by Paul Mundt
1 parent 52e8b118ec
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

sh: Add support for SH7721 CPU subtype. 

Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>

Showing 19 changed files with 68 additions and 29 deletions Side-by-side Diff

... ... @@ -214,6 +214,13 @@
214 214 help
215 215 Select SH7720 if you have a SH3-DSP SH7720 CPU.
216 216  
  217 +config CPU_SUBTYPE_SH7721
  218 + bool "Support SH7721 processor"
  219 + select CPU_SH3
  220 + select CPU_HAS_DSP
  221 + help
  222 + Select SH7721 if you have a SH3-DSP SH7721 CPU.
  223 +
217 224 # SH-4 Processor Support
218 225  
219 226 config CPU_SUBTYPE_SH7750
arch/sh/Kconfig.debug
Diff comments   View file @ 31a49c4
... ... @@ -35,7 +35,7 @@
35 35 default "0xfffe9800" if CPU_SUBTYPE_SH7206 || CPU_SUBTYPE_SH7263
36 36 default "0xf8420000" if CPU_SUBTYPE_SH7619
37 37 default "0xa4400000" if CPU_SUBTYPE_SH7712 || CPU_SUBTYPE_SH7705
38   - default "0xa4430000" if CPU_SUBTYPE_SH7720
  38 + default "0xa4430000" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
39 39 default "0xffc30000" if CPU_SUBTYPE_SHX3
40 40 default "0xffe80000" if CPU_SH4
41 41 default "0x00000000"
arch/sh/drivers/dma/Kconfig
Diff comments   View file @ 31a49c4
... ... @@ -12,7 +12,7 @@
12 12 config NR_ONCHIP_DMA_CHANNELS
13 13 int
14 14 depends on SH_DMA
15   - default "6" if CPU_SUBTYPE_SH7720
  15 + default "6" if CPU_SUBTYPE_SH7720 || CPU_SUBTYPE_SH7721
16 16 default "8" if CPU_SUBTYPE_SH7750R || CPU_SUBTYPE_SH7751R
17 17 default "12" if CPU_SUBTYPE_SH7780
18 18 default "4"
arch/sh/drivers/dma/dma-sh.c
Diff comments   View file @ 31a49c4
... ... @@ -25,6 +25,7 @@
25 25 DMTE2_IRQ,
26 26 DMTE3_IRQ,
27 27 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  28 + defined(CONFIG_CPU_SUBTYPE_SH7721) || \
28 29 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
29 30 defined(CONFIG_CPU_SUBTYPE_SH7760) || \
30 31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
... ... @@ -203,6 +204,7 @@
203 204 }
204 205  
205 206 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  207 + defined(CONFIG_CPU_SUBTYPE_SH7721) || \
206 208 defined(CONFIG_CPU_SUBTYPE_SH7780)
207 209 #define dmaor_read_reg() ctrl_inw(DMAOR)
208 210 #define dmaor_write_reg(data) ctrl_outw(data, DMAOR)
arch/sh/kernel/cpu/sh3/Makefile
Diff comments   View file @ 31a49c4
... ... @@ -13,6 +13,7 @@
13 13 obj-$(CONFIG_CPU_SUBTYPE_SH7710) += setup-sh7710.o
14 14 obj-$(CONFIG_CPU_SUBTYPE_SH7712) += setup-sh7710.o
15 15 obj-$(CONFIG_CPU_SUBTYPE_SH7720) += setup-sh7720.o
  16 +obj-$(CONFIG_CPU_SUBTYPE_SH7721) += setup-sh7720.o
16 17  
17 18 # Primary on-chip clocks (common)
18 19 clock-$(CONFIG_CPU_SH3) := clock-sh3.o
arch/sh/kernel/cpu/sh3/probe.c
Diff comments   View file @ 31a49c4
... ... @@ -84,6 +84,9 @@
84 84 #if defined(CONFIG_CPU_SUBTYPE_SH7720)
85 85 boot_cpu_data.type = CPU_SH7720;
86 86 #endif
  87 +#if defined(CONFIG_CPU_SUBTYPE_SH7721)
  88 + boot_cpu_data.type = CPU_SH7721;
  89 +#endif
87 90 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
88 91 boot_cpu_data.type = CPU_SH7705;
89 92  
arch/sh/kernel/cpu/sh3/setup-sh7720.c
Diff comments   View file @ 31a49c4
... ... @@ -127,8 +127,11 @@
127 127 INTC_VECT(USBF_SPD, 0x6e0), INTC_VECT(DMAC1_DEI0, 0x800),
128 128 INTC_VECT(DMAC1_DEI1, 0x820), INTC_VECT(DMAC1_DEI2, 0x840),
129 129 INTC_VECT(DMAC1_DEI3, 0x860), INTC_VECT(LCDC, 0x900),
130   - INTC_VECT(SSL, 0x980), INTC_VECT(USBFI0, 0xa20),
131   - INTC_VECT(USBFI1, 0xa40), INTC_VECT(USBHI, 0xa60),
  130 +#if defined(CONFIG_CPU_SUBTYPE_SH7720)
  131 + INTC_VECT(SSL, 0x980),
  132 +#endif
  133 + INTC_VECT(USBFI0, 0xa20), INTC_VECT(USBFI1, 0xa40),
  134 + INTC_VECT(USBHI, 0xa60),
132 135 INTC_VECT(DMAC2_DEI4, 0xb80), INTC_VECT(DMAC2_DEI5, 0xba0),
133 136 INTC_VECT(ADC, 0xbe0), INTC_VECT(SCIF0, 0xc00),
134 137 INTC_VECT(SCIF1, 0xc20), INTC_VECT(PINT07, 0xc80),
135 138  
... ... @@ -168,7 +171,11 @@
168 171 { 0xA414FEE4UL, 0, 16, 4, /* IPRB */ { WDT, REF_RCMI, SIM, 0 } },
169 172 { 0xA4140016UL, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
170 173 { 0xA4140018UL, 0, 16, 4, /* IPRD */ { USBF_SPD, TMU_SUNI, IRQ5, IRQ4 } },
  174 +#if defined(CONFIG_CPU_SUBTYPE_SH7720)
171 175 { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, SSL } },
  176 +#else
  177 + { 0xA414001AUL, 0, 16, 4, /* IPRE */ { DMAC1, 0, LCDC, 0 } },
  178 +#endif
172 179 { 0xA4080000UL, 0, 16, 4, /* IPRF */ { ADC, DMAC2, USBFI, CMT } },
173 180 { 0xA4080002UL, 0, 16, 4, /* IPRG */ { SCIF0, SCIF1, 0, 0 } },
174 181 { 0xA4080004UL, 0, 16, 4, /* IPRH */ { PINT07, PINT815, TPU, IIC } },
arch/sh/kernel/early_printk.c
Diff comments   View file @ 31a49c4
... ... @@ -63,7 +63,8 @@
63 63 #include <linux/serial_core.h>
64 64 #include "../../../drivers/serial/sh-sci.h"
65 65  
66   -#if defined(CONFIG_CPU_SUBTYPE_SH7720)
  66 +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  67 + defined(CONFIG_CPU_SUBTYPE_SH7721)
67 68 #define EPK_SCSMR_VALUE 0x000
68 69 #define EPK_SCBRR_VALUE 0x00C
69 70 #define EPK_FIFO_SIZE 64
... ... @@ -117,7 +118,8 @@
117 118 };
118 119  
119 120 #if !defined(CONFIG_SH_STANDARD_BIOS)
120   -#if defined(CONFIG_CPU_SUBTYPE_SH7720)
  121 +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  122 + defined(CONFIG_CPU_SUBTYPE_SH7721)
121 123 static void scif_sercon_init(char *s)
122 124 {
123 125 sci_out(&scif_port, SCSCR, 0x0000); /* clear TE and RE */
124 126  
... ... @@ -208,9 +210,11 @@
208 210 if (!strncmp(buf, "serial", 6)) {
209 211 early_console = &scif_console;
210 212  
211   -#if (defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720)) && \
212   - !defined(CONFIG_SH_STANDARD_BIOS)
  213 +#if !defined(CONFIG_SH_STANDARD_BIOS)
  214 +#if defined(CONFIG_CPU_SH4) || defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  215 + defined(CONFIG_CPU_SUBTYPE_SH7721)
213 216 scif_sercon_init(buf + 6);
  217 +#endif
214 218 #endif
215 219 }
216 220 #endif
arch/sh/kernel/setup.c
Diff comments   View file @ 31a49c4
... ... @@ -314,10 +314,10 @@
314 314 [CPU_SH7707] = "SH7707", [CPU_SH7708] = "SH7708",
315 315 [CPU_SH7709] = "SH7709", [CPU_SH7710] = "SH7710",
316 316 [CPU_SH7712] = "SH7712", [CPU_SH7720] = "SH7720",
317   - [CPU_SH7729] = "SH7729", [CPU_SH7750] = "SH7750",
318   - [CPU_SH7750S] = "SH7750S", [CPU_SH7750R] = "SH7750R",
319   - [CPU_SH7751] = "SH7751", [CPU_SH7751R] = "SH7751R",
320   - [CPU_SH7760] = "SH7760",
  317 + [CPU_SH7721] = "SH7721", [CPU_SH7729] = "SH7729",
  318 + [CPU_SH7750] = "SH7750", [CPU_SH7750S] = "SH7750S",
  319 + [CPU_SH7750R] = "SH7750R", [CPU_SH7751] = "SH7751",
  320 + [CPU_SH7751R] = "SH7751R", [CPU_SH7760] = "SH7760",
321 321 [CPU_SH4_202] = "SH4-202", [CPU_SH4_501] = "SH4-501",
322 322 [CPU_SH7770] = "SH7770", [CPU_SH7780] = "SH7780",
323 323 [CPU_SH7781] = "SH7781", [CPU_SH7343] = "SH7343",
arch/sh/kernel/timers/timer-tmu.c
Diff comments   View file @ 31a49c4
... ... @@ -174,6 +174,7 @@
174 174 tmu_timer_stop();
175 175  
176 176 #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
  177 + !defined(CONFIG_CPU_SUBTYPE_SH7721) && \
177 178 !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
178 179 !defined(CONFIG_CPU_SUBTYPE_SH7785) && \
179 180 !defined(CONFIG_CPU_SUBTYPE_SHX3)
drivers/serial/sh-sci.c
Diff comments   View file @ 31a49c4
... ... @@ -302,7 +302,7 @@
302 302 }
303 303 sci_out(port, SCFCR, fcr_val);
304 304 }
305   -#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
  305 +#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7721)
306 306 static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
307 307 {
308 308 unsigned int fcr_val = 0;
drivers/serial/sh-sci.h
Diff comments   View file @ 31a49c4
... ... @@ -46,7 +46,8 @@
46 46 */
47 47 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
48 48 # define SCIF_ONLY
49   -#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
  49 +#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  50 + defined(CONFIG_CPU_SUBTYPE_SH7721)
50 51 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
51 52 # define SCIF_ONLY
52 53 #define SCIF_ORER 0x0200 /* overrun error bit */
... ... @@ -216,7 +217,8 @@
216 217 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
217 218  
218 219 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
219   - defined(CONFIG_CPU_SUBTYPE_SH7720)
  220 + defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  221 + defined(CONFIG_CPU_SUBTYPE_SH7721)
220 222 #define SCIF_ORER 0x0200
221 223 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
222 224 #define SCIF_RFDC_MASK 0x007f
... ... @@ -254,7 +256,8 @@
254 256 # define SCxSR_PER(port) SCIF_PER
255 257 # define SCxSR_BRK(port) SCIF_BRK
256 258 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
257   - defined(CONFIG_CPU_SUBTYPE_SH7720)
  259 + defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  260 + defined(CONFIG_CPU_SUBTYPE_SH7721)
258 261 # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
259 262 # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
260 263 # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
... ... @@ -363,7 +366,8 @@
363 366 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
364 367 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
365 368 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
366   - defined(CONFIG_CPU_SUBTYPE_SH7720)
  369 + defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  370 + defined(CONFIG_CPU_SUBTYPE_SH7721)
367 371 #define SCIF_FNS(name, scif_offset, scif_size) \
368 372 CPU_SCIF_FNS(name, scif_offset, scif_size)
369 373 #else
... ... @@ -390,7 +394,8 @@
390 394 #endif
391 395  
392 396 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
393   - defined(CONFIG_CPU_SUBTYPE_SH7720)
  397 + defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  398 + defined(CONFIG_CPU_SUBTYPE_SH7721)
394 399  
395 400 SCIF_FNS(SCSMR, 0x00, 16)
396 401 SCIF_FNS(SCBRR, 0x04, 8)
... ... @@ -512,7 +517,8 @@
512 517 return;
513 518 }
514 519 }
515   -#elif defined(CONFIG_CPU_SUBTYPE_SH7720)
  520 +#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  521 + defined(CONFIG_CPU_SUBTYPE_SH7721)
516 522 static inline int sci_rxd_in(struct uart_port *port)
517 523 {
518 524 if (port->mapbase == 0xa4430000)
... ... @@ -696,7 +702,8 @@
696 702 defined(CONFIG_CPU_SUBTYPE_SH7785)
697 703 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
698 704 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
699   - defined(CONFIG_CPU_SUBTYPE_SH7720)
  705 + defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  706 + defined(CONFIG_CPU_SUBTYPE_SH7721)
700 707 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
701 708 #elif defined(__H8300H__) || defined(__H8300S__)
702 709 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
include/asm-sh/cpu-sh3/cache.h
Diff comments   View file @ 31a49c4
... ... @@ -33,7 +33,8 @@
33 33  
34 34 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
35 35 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
36   - defined(CONFIG_CPU_SUBTYPE_SH7720)
  36 + defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  37 + defined(CONFIG_CPU_SUBTYPE_SH7721)
37 38 #define CCR3 0xa40000b4
38 39 #define CCR_CACHE_16KB 0x00010000
39 40 #define CCR_CACHE_32KB 0x00020000
include/asm-sh/cpu-sh3/dma.h
Diff comments   View file @ 31a49c4
... ... @@ -2,7 +2,9 @@
2 2 #define __ASM_CPU_SH3_DMA_H
3 3  
4 4  
5   -#if defined(CONFIG_CPU_SUBTYPE_SH7720) || defined(CONFIG_CPU_SUBTYPE_SH7709)
  5 +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  6 + defined(CONFIG_CPU_SUBTYPE_SH7721) || \
  7 + defined(CONFIG_CPU_SUBTYPE_SH7709)
6 8 #define SH_DMAC_BASE 0xa4010020
7 9  
8 10 #define DMTE0_IRQ 48
include/asm-sh/cpu-sh3/gpio.h
Diff comments   View file @ 31a49c4
... ... @@ -12,7 +12,8 @@
12 12 #ifndef _CPU_SH3_GPIO_H
13 13 #define _CPU_SH3_GPIO_H
14 14  
15   -#if defined(CONFIG_CPU_SUBTYPE_SH7720)
  15 +#if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  16 + defined(CONFIG_CPU_SUBTYPE_SH7721)
16 17  
17 18 /* Control registers */
18 19 #define PORT_PACR 0xA4050100UL
include/asm-sh/cpu-sh3/mmu_context.h
Diff comments   View file @ 31a49c4
... ... @@ -33,7 +33,8 @@
33 33 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
34 34 defined(CONFIG_CPU_SUBTYPE_SH7710) || \
35 35 defined(CONFIG_CPU_SUBTYPE_SH7712) || \
36   - defined(CONFIG_CPU_SUBTYPE_SH7720)
  36 + defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  37 + defined(CONFIG_CPU_SUBTYPE_SH7721)
37 38 #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */
38 39 #else
39 40 #define INTEVT 0xffffffd8
include/asm-sh/cpu-sh3/timer.h
Diff comments   View file @ 31a49c4
... ... @@ -23,12 +23,13 @@
23 23 * ---------------------------------------------------------------------------
24 24 */
25 25  
26   -#if !defined(CONFIG_CPU_SUBTYPE_SH7720)
  26 +#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
27 27 #define TMU_TOCR 0xfffffe90 /* Byte access */
28 28 #endif
29 29  
30 30 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
31   - defined(CONFIG_CPU_SUBTYPE_SH7720)
  31 + defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  32 + defined(CONFIG_CPU_SUBTYPE_SH7721)
32 33 #define TMU_012_TSTR 0xa412fe92 /* Byte access */
33 34  
34 35 #define TMU0_TCOR 0xa412fe94 /* Long access */
... ... @@ -57,7 +58,7 @@
57 58 #define TMU2_TCOR 0xfffffeac /* Long access */
58 59 #define TMU2_TCNT 0xfffffeb0 /* Long access */
59 60 #define TMU2_TCR 0xfffffeb4 /* Word access */
60   -#if !defined(CONFIG_CPU_SUBTYPE_SH7720)
  61 +#if !defined(CONFIG_CPU_SUBTYPE_SH7720) && !defined(CONFIG_CPU_SUBTYPE_SH7721)
61 62 #define TMU2_TCPR2 0xfffffeb8 /* Long access */
62 63 #endif
63 64 #endif
include/asm-sh/cpu-sh3/ubc.h
Diff comments   View file @ 31a49c4
... ... @@ -12,7 +12,8 @@
12 12 #define __ASM_CPU_SH3_UBC_H
13 13  
14 14 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || \
15   - defined(CONFIG_CPU_SUBTYPE_SH7720)
  15 + defined(CONFIG_CPU_SUBTYPE_SH7720) || \
  16 + defined(CONFIG_CPU_SUBTYPE_SH7721)
16 17 #define UBC_BARA 0xa4ffffb0
17 18 #define UBC_BAMRA 0xa4ffffb4
18 19 #define UBC_BBRA 0xa4ffffb8
include/asm-sh/processor.h
Diff comments   View file @ 31a49c4
... ... @@ -23,7 +23,7 @@
23 23 CPU_SH7705, CPU_SH7706, CPU_SH7707,
24 24 CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
25 25 CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
26   - CPU_SH7720, CPU_SH7729,
  26 + CPU_SH7720, CPU_SH7721, CPU_SH7729,
27 27  
28 28 /* SH-4 types */
29 29 CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,