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Commit 328329a7bda52a8ed413cd485211463581f7abab

Authored by Anton Vorontsov
Committed by Linus Torvalds
1 parent d1e44d9ce8
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

spi_mpc83xx handles other processors with QUICC engine 

Currently, all QE SPI controllers are almost the same comparing to
MPC83xx's, thus let's use that driver for them.

Tested to work on MPC85xx in loopback mode.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

Showing 1 changed file with 7 additions and 6 deletions Side-by-side Diff

... ... @@ -124,16 +124,17 @@
124 124 Controller in master SPI mode.
125 125  
126 126 config SPI_MPC83xx
127   - tristate "Freescale MPC83xx SPI controller"
128   - depends on SPI_MASTER && PPC_83xx && EXPERIMENTAL
  127 + tristate "Freescale MPC83xx/QUICC Engine SPI controller"
  128 + depends on SPI_MASTER && (PPC_83xx || QUICC_ENGINE) && EXPERIMENTAL
129 129 select SPI_BITBANG
130 130 help
131   - This enables using the Freescale MPC83xx SPI controller in master
132   - mode.
  131 + This enables using the Freescale MPC83xx and QUICC Engine SPI
  132 + controllers in master mode.
133 133  
134 134 Note, this driver uniquely supports the SPI controller on the MPC83xx
135   - family of PowerPC processors. The MPC83xx uses a simple set of shift
136   - registers for data (opposed to the CPM based descriptor model).
  135 + family of PowerPC processors, plus processors with QUICC Engine
  136 + technology. This driver uses a simple set of shift registers for data
  137 + (opposed to the CPM based descriptor model).
137 138  
138 139 config SPI_OMAP_UWIRE
139 140 tristate "OMAP1 MicroWire"