MIPS: dsp: Add assembler support for DSP ASEs.

Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4752/ Signed-off-by: John Crispin <blogic@openwrt.org>

MIPS: dsp: Add assembler support for DSP ASEs.
Newer toolchains support the DSP and DSP Rev2 instructions. This patch performs a check for that support and adds compiler and assembler flags for only the files that need use those instructions. Signed-off-by: Steven J. Hill <sjhill@mips.com> Acked-by: Florian Fainelli <florian@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4752/ Signed-off-by: John Crispin <blogic@openwrt.org>
Steven J. Hill · John Crispin
1 parent f8fa4811db
Showing 2 changed files with 67 additions and 17 deletions Side-by-side Diff
arch/mips/include/asm/mipsregs.h
arch/mips/kernel/Makefile
@@ -1155,36 +1155,26 @@
         : "=r" (__res));                                        \
         __res;})
  
+#ifdef HAVE_AS_DSP
 #define rddsp(mask)							\
 ({									\
-	unsigned int __res;						\
+	unsigned int __dspctl;						\
 									\
 	__asm__ __volatile__(						\
-	"	.set	push				\n"		\
-	"	.set	noat				\n"		\
-	"	# rddsp $1, %x1				\n"		\
-	"	.word	0x7c000cb8 | (%x1 << 16)	\n"		\
-	"	move	%0, $1				\n"		\
-	"	.set	pop				\n"		\
-	: "=r" (__res)							\
+	"	rddsp	%0, %x1					\n"	\
+	: "=r" (__dspctl)						\
 	: "i" (mask));							\
-	__res;								\
+	__dspctl;							\
 })
  
 #define wrdsp(val, mask)						\
 do {									\
 	__asm__ __volatile__(						\
-	"	.set	push					\n"	\
-	"	.set	noat					\n"	\
-	"	move	$1, %0					\n"	\
-	"	# wrdsp $1, %x1					\n"	\
-	"	.word	0x7c2004f8 | (%x1 << 11)		\n"	\
-	"	.set	pop					\n"	\
-        :								\
+	"	wrdsp	%0, %x1					\n"	\
+	:								\
 	: "r" (val), "i" (mask));					\
 } while (0)
  
-#if 0	/* Need DSP ASE capable assembler ... */
 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
@@ -1206,6 +1196,35 @@
 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
  
 #else
+
+#define rddsp(mask)							\
+({									\
+	unsigned int __res;						\
+									\
+	__asm__ __volatile__(						\
+	"	.set	push				\n"		\
+	"	.set	noat				\n"		\
+	"	# rddsp $1, %x1				\n"		\
+	"	.word	0x7c000cb8 | (%x1 << 16)	\n"		\
+	"	move	%0, $1				\n"		\
+	"	.set	pop				\n"		\
+	: "=r" (__res)							\
+	: "i" (mask));							\
+	__res;								\
+})
+
+#define wrdsp(val, mask)						\
+do {									\
+	__asm__ __volatile__(						\
+	"	.set	push					\n"	\
+	"	.set	noat					\n"	\
+	"	move	$1, %0					\n"	\
+	"	# wrdsp $1, %x1					\n"	\
+	"	.word	0x7c2004f8 | (%x1 << 11)		\n"	\
+	"	.set	pop					\n"	\
+        :								\
+	: "r" (val), "i" (mask));					\
+} while (0)
  
 #define mfhi0()								\
 ({									\
@@ -98,5 +98,36 @@
  
 obj-$(CONFIG_JUMP_LABEL)	+= jump_label.o
  
+#
+# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe
+# to enable DSP assembler support here even if the MIPS Release 2 CPU we
+# are targetting does not support DSP because all code-paths making use of
+# it properly check that the running CPU *actually does* support these
+# instructions.
+#
+ifeq ($(CONFIG_CPU_MIPSR2), y)
+CFLAGS_DSP 			= -DHAVE_AS_DSP
+
+#
+# Check if assembler supports DSP ASE
+#
+ifeq ($(call cc-option-yn,-mdsp), y)
+CFLAGS_DSP			+= -mdsp
+endif
+
+#
+# Check if assembler supports DSP ASE Rev2
+#
+ifeq ($(call cc-option-yn,-mdspr2), y)
+CFLAGS_DSP			+= -mdspr2
+endif
+
+CFLAGS_signal.o			= $(CFLAGS_DSP)
+CFLAGS_signal32.o		= $(CFLAGS_DSP)
+CFLAGS_process.o		= $(CFLAGS_DSP)
+CFLAGS_branch.o			= $(CFLAGS_DSP)
+CFLAGS_ptrace.o			= $(CFLAGS_DSP)
+endif
+
 CPPFLAGS_vmlinux.lds		:= $(KBUILD_CFLAGS)
...	...	@@ -1155,36 +1155,26 @@
1155	1155	: "=r" (__res)); \
1156	1156	__res;})
1157	1157
	1158	+#ifdef HAVE_AS_DSP
1158	1159	#define rddsp(mask) \
1159	1160	({ \
1160		- unsigned int __res; \
	1161	+ unsigned int __dspctl; \
1161	1162	\
1162	1163	__asm__ __volatile__( \
1163		- " .set push \n" \
1164		- " .set noat \n" \
1165		- " # rddsp $1, %x1 \n" \
1166		- " .word 0x7c000cb8 \| (%x1 << 16) \n" \
1167		- " move %0, $1 \n" \
1168		- " .set pop \n" \
1169		- : "=r" (__res) \
	1164	+ " rddsp %0, %x1 \n" \
	1165	+ : "=r" (__dspctl) \
1170	1166	: "i" (mask)); \
1171		- __res; \
	1167	+ __dspctl; \
1172	1168	})
1173	1169
1174	1170	#define wrdsp(val, mask) \
1175	1171	do { \
1176	1172	__asm__ __volatile__( \
1177		- " .set push \n" \
1178		- " .set noat \n" \
1179		- " move $1, %0 \n" \
1180		- " # wrdsp $1, %x1 \n" \
1181		- " .word 0x7c2004f8 \| (%x1 << 11) \n" \
1182		- " .set pop \n" \
1183		- : \
	1173	+ " wrdsp %0, %x1 \n" \
	1174	+ : \
1184	1175	: "r" (val), "i" (mask)); \
1185	1176	} while (0)
1186	1177
1187		-#if 0 /* Need DSP ASE capable assembler ... */
1188	1178	#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
1189	1179	#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
1190	1180	#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
...	...	@@ -1206,6 +1196,35 @@
1206	1196	#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
1207	1197
1208	1198	#else
	1199	+
	1200	+#define rddsp(mask) \
	1201	+({ \
	1202	+ unsigned int __res; \
	1203	+ \
	1204	+ __asm__ __volatile__( \
	1205	+ " .set push \n" \
	1206	+ " .set noat \n" \
	1207	+ " # rddsp $1, %x1 \n" \
	1208	+ " .word 0x7c000cb8 \| (%x1 << 16) \n" \
	1209	+ " move %0, $1 \n" \
	1210	+ " .set pop \n" \
	1211	+ : "=r" (__res) \
	1212	+ : "i" (mask)); \
	1213	+ __res; \
	1214	+})
	1215	+
	1216	+#define wrdsp(val, mask) \
	1217	+do { \
	1218	+ __asm__ __volatile__( \
	1219	+ " .set push \n" \
	1220	+ " .set noat \n" \
	1221	+ " move $1, %0 \n" \
	1222	+ " # wrdsp $1, %x1 \n" \
	1223	+ " .word 0x7c2004f8 \| (%x1 << 11) \n" \
	1224	+ " .set pop \n" \
	1225	+ : \
	1226	+ : "r" (val), "i" (mask)); \
	1227	+} while (0)
1209	1228
1210	1229	#define mfhi0() \
1211	1230	({ \
...	...	@@ -98,5 +98,36 @@
98	98
99	99	obj-$(CONFIG_JUMP_LABEL) += jump_label.o
100	100
	101	+#
	102	+# DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe
	103	+# to enable DSP assembler support here even if the MIPS Release 2 CPU we
	104	+# are targetting does not support DSP because all code-paths making use of
	105	+# it properly check that the running CPU actually does support these
	106	+# instructions.
	107	+#
	108	+ifeq ($(CONFIG_CPU_MIPSR2), y)
	109	+CFLAGS_DSP = -DHAVE_AS_DSP
	110	+
	111	+#
	112	+# Check if assembler supports DSP ASE
	113	+#
	114	+ifeq ($(call cc-option-yn,-mdsp), y)
	115	+CFLAGS_DSP += -mdsp
	116	+endif
	117	+
	118	+#
	119	+# Check if assembler supports DSP ASE Rev2
	120	+#
	121	+ifeq ($(call cc-option-yn,-mdspr2), y)
	122	+CFLAGS_DSP += -mdspr2
	123	+endif
	124	+
	125	+CFLAGS_signal.o = $(CFLAGS_DSP)
	126	+CFLAGS_signal32.o = $(CFLAGS_DSP)
	127	+CFLAGS_process.o = $(CFLAGS_DSP)
	128	+CFLAGS_branch.o = $(CFLAGS_DSP)
	129	+CFLAGS_ptrace.o = $(CFLAGS_DSP)
	130	+endif
	131	+
101	132	CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)