Commit 32b53076c31ce9159740b744d5eb5d9505312add
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serial: sh-sci: Convert tremaining ctrl_xxx I/O routines to __raw_xxx.
ctrl_xxx() is an antiquated SH interface, while __raw_xxx is the standard API that accomplishes the same thing. As such, this converts the remaining sh-sci straggles over, which enables the driver to be wired up for ARM SH-Mobile CPUs as well. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Showing 2 changed files with 61 additions and 61 deletions Side-by-side Diff
drivers/serial/sh-sci.c
... | ... | @@ -222,9 +222,9 @@ |
222 | 222 | Set SCP6MD1,0 = {01} (output) */ |
223 | 223 | __raw_writew((data & 0x0fcf) | 0x1000, SCPCR); |
224 | 224 | |
225 | - data = ctrl_inb(SCPDR); | |
225 | + data = __raw_readb(SCPDR); | |
226 | 226 | /* Set /RTS2 (bit6) = 0 */ |
227 | - ctrl_outb(data & 0xbf, SCPDR); | |
227 | + __raw_writeb(data & 0xbf, SCPDR); | |
228 | 228 | } |
229 | 229 | } |
230 | 230 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
drivers/serial/sh-sci.h
... | ... | @@ -517,20 +517,20 @@ |
517 | 517 | static inline int sci_rxd_in(struct uart_port *port) |
518 | 518 | { |
519 | 519 | if (port->mapbase == 0xfffffe80) |
520 | - return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | |
520 | + return __raw_readb(SCPDR)&0x01 ? 1 : 0; /* SCI */ | |
521 | 521 | if (port->mapbase == 0xa4000150) |
522 | - return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
522 | + return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
523 | 523 | if (port->mapbase == 0xa4000140) |
524 | - return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
524 | + return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
525 | 525 | return 1; |
526 | 526 | } |
527 | 527 | #elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
528 | 528 | static inline int sci_rxd_in(struct uart_port *port) |
529 | 529 | { |
530 | 530 | if (port->mapbase == SCIF0) |
531 | - return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
531 | + return __raw_readb(SCPDR)&0x04 ? 1 : 0; /* IRDA */ | |
532 | 532 | if (port->mapbase == SCIF2) |
533 | - return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
533 | + return __raw_readb(SCPDR)&0x10 ? 1 : 0; /* SCIF */ | |
534 | 534 | return 1; |
535 | 535 | } |
536 | 536 | #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
537 | 537 | |
538 | 538 | |
539 | 539 | |
540 | 540 | |
541 | 541 | |
542 | 542 | |
543 | 543 | |
544 | 544 | |
545 | 545 | |
546 | 546 | |
547 | 547 | |
548 | 548 | |
549 | 549 | |
550 | 550 | |
551 | 551 | |
552 | 552 | |
... | ... | @@ -557,68 +557,68 @@ |
557 | 557 | static inline int sci_rxd_in(struct uart_port *port) |
558 | 558 | { |
559 | 559 | if (port->mapbase == 0xffe00000) |
560 | - return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | |
560 | + return __raw_readb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */ | |
561 | 561 | if (port->mapbase == 0xffe80000) |
562 | - return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
562 | + return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
563 | 563 | return 1; |
564 | 564 | } |
565 | 565 | #elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
566 | 566 | static inline int sci_rxd_in(struct uart_port *port) |
567 | 567 | { |
568 | 568 | if (port->mapbase == 0xffe80000) |
569 | - return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
569 | + return __raw_readw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ | |
570 | 570 | return 1; |
571 | 571 | } |
572 | 572 | #elif defined(CONFIG_CPU_SUBTYPE_SH7757) |
573 | 573 | static inline int sci_rxd_in(struct uart_port *port) |
574 | 574 | { |
575 | 575 | if (port->mapbase == 0xfe4b0000) |
576 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; | |
576 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; | |
577 | 577 | if (port->mapbase == 0xfe4c0000) |
578 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; | |
578 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; | |
579 | 579 | if (port->mapbase == 0xfe4d0000) |
580 | - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; | |
580 | + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; | |
581 | 581 | } |
582 | 582 | #elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
583 | 583 | static inline int sci_rxd_in(struct uart_port *port) |
584 | 584 | { |
585 | 585 | if (port->mapbase == 0xfe600000) |
586 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
586 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
587 | 587 | if (port->mapbase == 0xfe610000) |
588 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
588 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
589 | 589 | if (port->mapbase == 0xfe620000) |
590 | - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
590 | + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
591 | 591 | return 1; |
592 | 592 | } |
593 | 593 | #elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
594 | 594 | static inline int sci_rxd_in(struct uart_port *port) |
595 | 595 | { |
596 | 596 | if (port->mapbase == 0xffe00000) |
597 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
597 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
598 | 598 | if (port->mapbase == 0xffe10000) |
599 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
599 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
600 | 600 | if (port->mapbase == 0xffe20000) |
601 | - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
601 | + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
602 | 602 | if (port->mapbase == 0xffe30000) |
603 | - return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
603 | + return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
604 | 604 | return 1; |
605 | 605 | } |
606 | 606 | #elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
607 | 607 | static inline int sci_rxd_in(struct uart_port *port) |
608 | 608 | { |
609 | 609 | if (port->mapbase == 0xffe00000) |
610 | - return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | |
610 | + return __raw_readb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ | |
611 | 611 | return 1; |
612 | 612 | } |
613 | 613 | #elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
614 | 614 | static inline int sci_rxd_in(struct uart_port *port) |
615 | 615 | { |
616 | 616 | if (port->mapbase == 0xffe00000) |
617 | - return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ | |
617 | + return __raw_readb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */ | |
618 | 618 | if (port->mapbase == 0xffe10000) |
619 | - return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ | |
619 | + return __raw_readb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */ | |
620 | 620 | if (port->mapbase == 0xffe20000) |
621 | - return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ | |
621 | + return __raw_readb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */ | |
622 | 622 | |
623 | 623 | return 1; |
624 | 624 | } |
625 | 625 | |
626 | 626 | |
627 | 627 | |
628 | 628 | |
629 | 629 | |
... | ... | @@ -626,17 +626,17 @@ |
626 | 626 | static inline int sci_rxd_in(struct uart_port *port) |
627 | 627 | { |
628 | 628 | if (port->mapbase == 0xffe00000) |
629 | - return ctrl_inb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ | |
629 | + return __raw_readb(SCSPTR0) & 0x0008 ? 1 : 0; /* SCIF0 */ | |
630 | 630 | if (port->mapbase == 0xffe10000) |
631 | - return ctrl_inb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ | |
631 | + return __raw_readb(SCSPTR1) & 0x0020 ? 1 : 0; /* SCIF1 */ | |
632 | 632 | if (port->mapbase == 0xffe20000) |
633 | - return ctrl_inb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ | |
633 | + return __raw_readb(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF2 */ | |
634 | 634 | if (port->mapbase == 0xa4e30000) |
635 | - return ctrl_inb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ | |
635 | + return __raw_readb(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF3 */ | |
636 | 636 | if (port->mapbase == 0xa4e40000) |
637 | - return ctrl_inb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ | |
637 | + return __raw_readb(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF4 */ | |
638 | 638 | if (port->mapbase == 0xa4e50000) |
639 | - return ctrl_inb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ | |
639 | + return __raw_readb(SCSPTR5) & 0x0008 ? 1 : 0; /* SCIF5 */ | |
640 | 640 | return 1; |
641 | 641 | } |
642 | 642 | #elif defined(CONFIG_CPU_SUBTYPE_SH7724) |
643 | 643 | |
... | ... | @@ -645,9 +645,9 @@ |
645 | 645 | static inline int sci_rxd_in(struct uart_port *port) |
646 | 646 | { |
647 | 647 | if (port->type == PORT_SCIF) |
648 | - return ctrl_inw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0; | |
648 | + return __raw_readw((port->mapbase + SCFSR)) & SCIF_BRK ? 1 : 0; | |
649 | 649 | if (port->type == PORT_SCIFA) |
650 | - return ctrl_inw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0; | |
650 | + return __raw_readw((port->mapbase + SCASSR)) & SCIF_BRK ? 1 : 0; | |
651 | 651 | return 1; |
652 | 652 | } |
653 | 653 | #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
654 | 654 | |
655 | 655 | |
... | ... | @@ -665,11 +665,11 @@ |
665 | 665 | static inline int sci_rxd_in(struct uart_port *port) |
666 | 666 | { |
667 | 667 | if (port->mapbase == 0xffe00000) |
668 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
668 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
669 | 669 | if (port->mapbase == 0xffe08000) |
670 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
670 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
671 | 671 | if (port->mapbase == 0xffe10000) |
672 | - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ | |
672 | + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF/IRDA */ | |
673 | 673 | |
674 | 674 | return 1; |
675 | 675 | } |
676 | 676 | |
677 | 677 | |
678 | 678 | |
679 | 679 | |
... | ... | @@ -677,20 +677,20 @@ |
677 | 677 | static inline int sci_rxd_in(struct uart_port *port) |
678 | 678 | { |
679 | 679 | if (port->mapbase == 0xff923000) |
680 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
680 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
681 | 681 | if (port->mapbase == 0xff924000) |
682 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
682 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
683 | 683 | if (port->mapbase == 0xff925000) |
684 | - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
684 | + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
685 | 685 | return 1; |
686 | 686 | } |
687 | 687 | #elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
688 | 688 | static inline int sci_rxd_in(struct uart_port *port) |
689 | 689 | { |
690 | 690 | if (port->mapbase == 0xffe00000) |
691 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
691 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
692 | 692 | if (port->mapbase == 0xffe10000) |
693 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
693 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
694 | 694 | return 1; |
695 | 695 | } |
696 | 696 | #elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
697 | 697 | |
698 | 698 | |
699 | 699 | |
700 | 700 | |
701 | 701 | |
... | ... | @@ -698,17 +698,17 @@ |
698 | 698 | static inline int sci_rxd_in(struct uart_port *port) |
699 | 699 | { |
700 | 700 | if (port->mapbase == 0xffea0000) |
701 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
701 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
702 | 702 | if (port->mapbase == 0xffeb0000) |
703 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
703 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
704 | 704 | if (port->mapbase == 0xffec0000) |
705 | - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
705 | + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
706 | 706 | if (port->mapbase == 0xffed0000) |
707 | - return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
707 | + return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
708 | 708 | if (port->mapbase == 0xffee0000) |
709 | - return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ | |
709 | + return __raw_readw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */ | |
710 | 710 | if (port->mapbase == 0xffef0000) |
711 | - return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ | |
711 | + return __raw_readw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */ | |
712 | 712 | return 1; |
713 | 713 | } |
714 | 714 | #elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ |
715 | 715 | |
716 | 716 | |
717 | 717 | |
718 | 718 | |
719 | 719 | |
720 | 720 | |
721 | 721 | |
... | ... | @@ -718,22 +718,22 @@ |
718 | 718 | static inline int sci_rxd_in(struct uart_port *port) |
719 | 719 | { |
720 | 720 | if (port->mapbase == 0xfffe8000) |
721 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
721 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
722 | 722 | if (port->mapbase == 0xfffe8800) |
723 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
723 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
724 | 724 | if (port->mapbase == 0xfffe9000) |
725 | - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
725 | + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
726 | 726 | if (port->mapbase == 0xfffe9800) |
727 | - return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
727 | + return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
728 | 728 | #if defined(CONFIG_CPU_SUBTYPE_SH7201) |
729 | 729 | if (port->mapbase == 0xfffeA000) |
730 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
730 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
731 | 731 | if (port->mapbase == 0xfffeA800) |
732 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
732 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
733 | 733 | if (port->mapbase == 0xfffeB000) |
734 | - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
734 | + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
735 | 735 | if (port->mapbase == 0xfffeB800) |
736 | - return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
736 | + return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
737 | 737 | #endif |
738 | 738 | return 1; |
739 | 739 | } |
740 | 740 | |
741 | 741 | |
742 | 742 | |
743 | 743 | |
744 | 744 | |
745 | 745 | |
... | ... | @@ -741,24 +741,24 @@ |
741 | 741 | static inline int sci_rxd_in(struct uart_port *port) |
742 | 742 | { |
743 | 743 | if (port->mapbase == 0xf8400000) |
744 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
744 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
745 | 745 | if (port->mapbase == 0xf8410000) |
746 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
746 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
747 | 747 | if (port->mapbase == 0xf8420000) |
748 | - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
748 | + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
749 | 749 | return 1; |
750 | 750 | } |
751 | 751 | #elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
752 | 752 | static inline int sci_rxd_in(struct uart_port *port) |
753 | 753 | { |
754 | 754 | if (port->mapbase == 0xffc30000) |
755 | - return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
755 | + return __raw_readw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */ | |
756 | 756 | if (port->mapbase == 0xffc40000) |
757 | - return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
757 | + return __raw_readw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */ | |
758 | 758 | if (port->mapbase == 0xffc50000) |
759 | - return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
759 | + return __raw_readw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */ | |
760 | 760 | if (port->mapbase == 0xffc60000) |
761 | - return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
761 | + return __raw_readw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ | |
762 | 762 | return 1; |
763 | 763 | } |
764 | 764 | #endif |