Commit 33959f88fce9b8d3346d8000b3425814cbc6d6c0

Authored by Michael Neuling
Committed by Benjamin Herrenschmidt
1 parent 3b2f64d00c

powerpc: Add second POWER8 PVR entry

POWER8 comes with two different PVRs.  This patch enables the additional
PVR in the cputable.

The existing entry (PVR=0x4b) is renamed to POWER8E and the new entry
(PVR=0x4d) is given POWER8.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Showing 3 changed files with 24 additions and 4 deletions Side-by-side Diff

arch/powerpc/include/asm/reg.h
... ... @@ -1088,7 +1088,8 @@
1088 1088 #define PVR_970MP 0x0044
1089 1089 #define PVR_970GX 0x0045
1090 1090 #define PVR_POWER7p 0x004A
1091   -#define PVR_POWER8 0x004B
  1091 +#define PVR_POWER8E 0x004B
  1092 +#define PVR_POWER8 0x004D
1092 1093 #define PVR_BE 0x0070
1093 1094 #define PVR_PA6T 0x0090
1094 1095  
arch/powerpc/kernel/cputable.c
... ... @@ -494,9 +494,27 @@
494 494 .cpu_restore = __restore_cpu_power7,
495 495 .platform = "power7+",
496 496 },
497   - { /* Power8 */
  497 + { /* Power8E */
498 498 .pvr_mask = 0xffff0000,
499 499 .pvr_value = 0x004b0000,
  500 + .cpu_name = "POWER8E (raw)",
  501 + .cpu_features = CPU_FTRS_POWER8,
  502 + .cpu_user_features = COMMON_USER_POWER8,
  503 + .cpu_user_features2 = COMMON_USER2_POWER8,
  504 + .mmu_features = MMU_FTRS_POWER8,
  505 + .icache_bsize = 128,
  506 + .dcache_bsize = 128,
  507 + .num_pmcs = 6,
  508 + .pmc_type = PPC_PMC_IBM,
  509 + .oprofile_cpu_type = "ppc64/power8",
  510 + .oprofile_type = PPC_OPROFILE_INVALID,
  511 + .cpu_setup = __setup_cpu_power8,
  512 + .cpu_restore = __restore_cpu_power8,
  513 + .platform = "power8",
  514 + },
  515 + { /* Power8 */
  516 + .pvr_mask = 0xffff0000,
  517 + .pvr_value = 0x004d0000,
500 518 .cpu_name = "POWER8 (raw)",
501 519 .cpu_features = CPU_FTRS_POWER8,
502 520 .cpu_user_features = COMMON_USER_POWER8,
arch/powerpc/kernel/prom_init.c
... ... @@ -644,7 +644,8 @@
644 644 W(0xfffe0000), W(0x003a0000), /* POWER5/POWER5+ */
645 645 W(0xffff0000), W(0x003e0000), /* POWER6 */
646 646 W(0xffff0000), W(0x003f0000), /* POWER7 */
647   - W(0xffff0000), W(0x004b0000), /* POWER8 */
  647 + W(0xffff0000), W(0x004b0000), /* POWER8E */
  648 + W(0xffff0000), W(0x004d0000), /* POWER8 */
648 649 W(0xffffffff), W(0x0f000004), /* all 2.07-compliant */
649 650 W(0xffffffff), W(0x0f000003), /* all 2.06-compliant */
650 651 W(0xffffffff), W(0x0f000002), /* all 2.05-compliant */
... ... @@ -706,7 +707,7 @@
706 707 * must match by the macro below. Update the definition if
707 708 * the structure layout changes.
708 709 */
709   -#define IBM_ARCH_VEC_NRCORES_OFFSET 117
  710 +#define IBM_ARCH_VEC_NRCORES_OFFSET 125
710 711 W(NR_CPUS), /* number of cores supported */
711 712 0,
712 713 0,