Doug / smarc-fsl-linux-kernel

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Commit 356bd765e2242bd351964bc2cca602dcee05c19d

Authored by Bjorn Helgaas
2 parents f36c493491 eb36309a9d
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

Merge branch 'pci/host-exynos' into next 

* pci/host-exynos:
  PCI: exynos: Remove redundant of_match_ptr
  PCI: designware: Add irq_create_mapping()
  PCI: designware: Make dw_pcie_rd_own_conf(), etc., static
  PCI: designware: Add header guards
  PCI: exynos: Add missing clk_disable_unprepare() on error path

Showing 3 changed files Side-by-side Diff

drivers/pci/host/pci-exynos.c
Diff comments   View file @ 356bd76
... ... @@ -599,18 +599,24 @@
599 599  
600 600 elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
601 601 exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base);
602   - if (IS_ERR(exynos_pcie->elbi_base))
603   - return PTR_ERR(exynos_pcie->elbi_base);
  602 + if (IS_ERR(exynos_pcie->elbi_base)) {
  603 + ret = PTR_ERR(exynos_pcie->elbi_base);
  604 + goto fail_bus_clk;
  605 + }
604 606  
605 607 phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1);
606 608 exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base);
607   - if (IS_ERR(exynos_pcie->phy_base))
608   - return PTR_ERR(exynos_pcie->phy_base);
  609 + if (IS_ERR(exynos_pcie->phy_base)) {
  610 + ret = PTR_ERR(exynos_pcie->phy_base);
  611 + goto fail_bus_clk;
  612 + }
609 613  
610 614 block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2);
611 615 exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base);
612   - if (IS_ERR(exynos_pcie->block_base))
613   - return PTR_ERR(exynos_pcie->block_base);
  616 + if (IS_ERR(exynos_pcie->block_base)) {
  617 + ret = PTR_ERR(exynos_pcie->block_base);
  618 + goto fail_bus_clk;
  619 + }
614 620  
615 621 ret = add_pcie_port(pp, pdev);
616 622 if (ret < 0)
... ... @@ -647,7 +653,7 @@
647 653 .driver = {
648 654 .name = "exynos-pcie",
649 655 .owner = THIS_MODULE,
650   - .of_match_table = of_match_ptr(exynos_pcie_of_match),
  656 + .of_match_table = exynos_pcie_of_match,
651 657 },
652 658 };
653 659  
drivers/pci/host/pcie-designware.c
Diff comments   View file @ 356bd76
... ... @@ -67,7 +67,7 @@
67 67  
68 68 static struct hw_pci dw_pci;
69 69  
70   -unsigned long global_io_offset;
  70 +static unsigned long global_io_offset;
71 71  
72 72 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
73 73 {
... ... @@ -118,8 +118,8 @@
118 118 writel(val, pp->dbi_base + reg);
119 119 }
120 120  
121   -int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
122   - u32 *val)
  121 +static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
  122 + u32 *val)
123 123 {
124 124 int ret;
125 125  
... ... @@ -131,8 +131,8 @@
131 131 return ret;
132 132 }
133 133  
134   -int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
135   - u32 val)
  134 +static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
  135 + u32 val)
136 136 {
137 137 int ret;
138 138  
... ... @@ -157,7 +157,7 @@
157 157 void dw_handle_msi_irq(struct pcie_port *pp)
158 158 {
159 159 unsigned long val;
160   - int i, pos;
  160 + int i, pos, irq;
161 161  
162 162 for (i = 0; i < MAX_MSI_CTRLS; i++) {
163 163 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
... ... @@ -165,8 +165,9 @@
165 165 if (val) {
166 166 pos = 0;
167 167 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
168   - generic_handle_irq(pp->msi_irq_start
169   - + (i * 32) + pos);
  168 + irq = irq_find_mapping(pp->irq_domain,
  169 + i * 32 + pos);
  170 + generic_handle_irq(irq);
170 171 pos++;
171 172 }
172 173 }
... ... @@ -237,9 +238,8 @@
237 238 }
238 239 }
239 240  
240   - irq = (pp->msi_irq_start + pos0);
241   -
242   - if ((irq + no_irqs) > (pp->msi_irq_start + MAX_MSI_IRQS-1))
  241 + irq = irq_find_mapping(pp->irq_domain, pos0);
  242 + if (!irq)
243 243 goto no_valid_irq;
244 244  
245 245 i = 0;
... ... @@ -270,6 +270,7 @@
270 270 struct irq_desc *desc;
271 271 struct msi_desc *msi;
272 272 struct pcie_port *pp;
  273 + struct irq_data *data = irq_get_irq_data(irq);
273 274  
274 275 /* get the port structure */
275 276 desc = irq_to_desc(irq);
... ... @@ -280,7 +281,7 @@
280 281 return;
281 282 }
282 283  
283   - pos = irq - pp->msi_irq_start;
  284 + pos = data->hwirq;
284 285  
285 286 irq_free_desc(irq);
286 287  
287 288  
... ... @@ -371,9 +372,8 @@
371 372 struct of_pci_range range;
372 373 struct of_pci_range_parser parser;
373 374 u32 val;
  375 + int i;
374 376  
375   - struct irq_domain *irq_domain;
376   -
377 377 if (of_pci_range_parser_init(&parser, np)) {
378 378 dev_err(pp->dev, "missing ranges property\n");
379 379 return -EINVAL;
380 380  
381 381  
... ... @@ -441,15 +441,16 @@
441 441 }
442 442  
443 443 if (IS_ENABLED(CONFIG_PCI_MSI)) {
444   - irq_domain = irq_domain_add_linear(pp->dev->of_node,
  444 + pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
445 445 MAX_MSI_IRQS, &msi_domain_ops,
446 446 &dw_pcie_msi_chip);
447   - if (!irq_domain) {
  447 + if (!pp->irq_domain) {
448 448 dev_err(pp->dev, "irq domain init failed\n");
449 449 return -ENXIO;
450 450 }
451 451  
452   - pp->msi_irq_start = irq_find_mapping(irq_domain, 0);
  452 + for (i = 0; i < MAX_MSI_IRQS; i++)
  453 + irq_create_mapping(pp->irq_domain, i);
453 454 }
454 455  
455 456 if (pp->ops->host_init)
... ... @@ -667,7 +668,7 @@
667 668 .write = dw_pcie_wr_conf,
668 669 };
669 670  
670   -int dw_pcie_setup(int nr, struct pci_sys_data *sys)
  671 +static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
671 672 {
672 673 struct pcie_port *pp;
673 674  
... ... @@ -690,7 +691,7 @@
690 691 return 1;
691 692 }
692 693  
693   -struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
  694 +static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
694 695 {
695 696 struct pci_bus *bus;
696 697 struct pcie_port *pp = sys_to_pcie(sys);
... ... @@ -707,7 +708,7 @@
707 708 return bus;
708 709 }
709 710  
710   -int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  711 +static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
711 712 {
712 713 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
713 714  
drivers/pci/host/pcie-designware.h
Diff comments   View file @ 356bd76
... ... @@ -11,6 +11,9 @@
11 11 * published by the Free Software Foundation.
12 12 */
13 13  
  14 +#ifndef _PCIE_DESIGNWARE_H
  15 +#define _PCIE_DESIGNWARE_H
  16 +
14 17 struct pcie_port_info {
15 18 u32 cfg0_size;
16 19 u32 cfg1_size;
... ... @@ -47,7 +50,7 @@
47 50 u32 lanes;
48 51 struct pcie_host_ops *ops;
49 52 int msi_irq;
50   - int msi_irq_start;
  53 + struct irq_domain *irq_domain;
51 54 unsigned long msi_data;
52 55 DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
53 56 };
54 57  
55 58  
... ... @@ -63,18 +66,13 @@
63 66 void (*host_init)(struct pcie_port *pp);
64 67 };
65 68  
66   -extern unsigned long global_io_offset;
67   -
68 69 int cfg_read(void __iomem *addr, int where, int size, u32 *val);
69 70 int cfg_write(void __iomem *addr, int where, int size, u32 val);
70   -int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val);
71   -int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val);
72 71 void dw_handle_msi_irq(struct pcie_port *pp);
73 72 void dw_pcie_msi_init(struct pcie_port *pp);
74 73 int dw_pcie_link_up(struct pcie_port *pp);
75 74 void dw_pcie_setup_rc(struct pcie_port *pp);
76 75 int dw_pcie_host_init(struct pcie_port *pp);
77   -int dw_pcie_setup(int nr, struct pci_sys_data *sys);
78   -struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys);
79   -int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
  76 +
  77 +#endif /* _PCIE_DESIGNWARE_H */