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Commit 3a2f9b99058cbe3f1b01297d29dc5b376563f670

Authored by Ganesan Ramalingam
Committed by Ralf Baechle
1 parent f35574a3ab
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

MIPS: Netlogic: Platform NAND/NOR flash support 

Changes to add support for the boot NOR flash on XLR boards and the
boot NAND/NOR flash drivers on the XLS boards.

Signed-off-by: Ganesan Ramalingam <ganesanr@netlogicmicro.com>
Signed-off-by: Jayachandran C <jayachandranc@netlogicmicro.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/3758/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 4 changed files with 380 additions and 1 deletions Side-by-side Diff

arch/mips/include/asm/netlogic/xlr/bridge.h
Diff comments   View file @ 3a2f9b9
  1 +/*
  2 + * Copyright (c) 2003-2012 Broadcom Corporation
  3 + * All Rights Reserved
  4 + *
  5 + * This software is available to you under a choice of one of two
  6 + * licenses. You may choose to be licensed under the terms of the GNU
  7 + * General Public License (GPL) Version 2, available from the file
  8 + * COPYING in the main directory of this source tree, or the Broadcom
  9 + * license below:
  10 + *
  11 + * Redistribution and use in source and binary forms, with or without
  12 + * modification, are permitted provided that the following conditions
  13 + * are met:
  14 + *
  15 + * 1. Redistributions of source code must retain the above copyright
  16 + * notice, this list of conditions and the following disclaimer.
  17 + * 2. Redistributions in binary form must reproduce the above copyright
  18 + * notice, this list of conditions and the following disclaimer in
  19 + * the documentation and/or other materials provided with the
  20 + * distribution.
  21 + *
  22 + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25 + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31 + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32 + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33 + */
  34 +#ifndef _ASM_NLM_BRIDGE_H_
  35 +#define _ASM_NLM_BRIDGE_H_
  36 +
  37 +#define BRIDGE_DRAM_0_BAR 0
  38 +#define BRIDGE_DRAM_1_BAR 1
  39 +#define BRIDGE_DRAM_2_BAR 2
  40 +#define BRIDGE_DRAM_3_BAR 3
  41 +#define BRIDGE_DRAM_4_BAR 4
  42 +#define BRIDGE_DRAM_5_BAR 5
  43 +#define BRIDGE_DRAM_6_BAR 6
  44 +#define BRIDGE_DRAM_7_BAR 7
  45 +#define BRIDGE_DRAM_CHN_0_MTR_0_BAR 8
  46 +#define BRIDGE_DRAM_CHN_0_MTR_1_BAR 9
  47 +#define BRIDGE_DRAM_CHN_0_MTR_2_BAR 10
  48 +#define BRIDGE_DRAM_CHN_0_MTR_3_BAR 11
  49 +#define BRIDGE_DRAM_CHN_0_MTR_4_BAR 12
  50 +#define BRIDGE_DRAM_CHN_0_MTR_5_BAR 13
  51 +#define BRIDGE_DRAM_CHN_0_MTR_6_BAR 14
  52 +#define BRIDGE_DRAM_CHN_0_MTR_7_BAR 15
  53 +#define BRIDGE_DRAM_CHN_1_MTR_0_BAR 16
  54 +#define BRIDGE_DRAM_CHN_1_MTR_1_BAR 17
  55 +#define BRIDGE_DRAM_CHN_1_MTR_2_BAR 18
  56 +#define BRIDGE_DRAM_CHN_1_MTR_3_BAR 19
  57 +#define BRIDGE_DRAM_CHN_1_MTR_4_BAR 20
  58 +#define BRIDGE_DRAM_CHN_1_MTR_5_BAR 21
  59 +#define BRIDGE_DRAM_CHN_1_MTR_6_BAR 22
  60 +#define BRIDGE_DRAM_CHN_1_MTR_7_BAR 23
  61 +#define BRIDGE_CFG_BAR 24
  62 +#define BRIDGE_PHNX_IO_BAR 25
  63 +#define BRIDGE_FLASH_BAR 26
  64 +#define BRIDGE_SRAM_BAR 27
  65 +#define BRIDGE_HTMEM_BAR 28
  66 +#define BRIDGE_HTINT_BAR 29
  67 +#define BRIDGE_HTPIC_BAR 30
  68 +#define BRIDGE_HTSM_BAR 31
  69 +#define BRIDGE_HTIO_BAR 32
  70 +#define BRIDGE_HTCFG_BAR 33
  71 +#define BRIDGE_PCIXCFG_BAR 34
  72 +#define BRIDGE_PCIXMEM_BAR 35
  73 +#define BRIDGE_PCIXIO_BAR 36
  74 +#define BRIDGE_DEVICE_MASK 37
  75 +#define BRIDGE_AERR_INTR_LOG1 38
  76 +#define BRIDGE_AERR_INTR_LOG2 39
  77 +#define BRIDGE_AERR_INTR_LOG3 40
  78 +#define BRIDGE_AERR_DEV_STAT 41
  79 +#define BRIDGE_AERR1_LOG1 42
  80 +#define BRIDGE_AERR1_LOG2 43
  81 +#define BRIDGE_AERR1_LOG3 44
  82 +#define BRIDGE_AERR1_DEV_STAT 45
  83 +#define BRIDGE_AERR_INTR_EN 46
  84 +#define BRIDGE_AERR_UPG 47
  85 +#define BRIDGE_AERR_CLEAR 48
  86 +#define BRIDGE_AERR1_CLEAR 49
  87 +#define BRIDGE_SBE_COUNTS 50
  88 +#define BRIDGE_DBE_COUNTS 51
  89 +#define BRIDGE_BITERR_INT_EN 52
  90 +
  91 +#define BRIDGE_SYS2IO_CREDITS 53
  92 +#define BRIDGE_EVNT_CNT_CTRL1 54
  93 +#define BRIDGE_EVNT_COUNTER1 55
  94 +#define BRIDGE_EVNT_CNT_CTRL2 56
  95 +#define BRIDGE_EVNT_COUNTER2 57
  96 +#define BRIDGE_RESERVED1 58
  97 +
  98 +#define BRIDGE_DEFEATURE 59
  99 +#define BRIDGE_SCRATCH0 60
  100 +#define BRIDGE_SCRATCH1 61
  101 +#define BRIDGE_SCRATCH2 62
  102 +#define BRIDGE_SCRATCH3 63
  103 +
  104 +#endif
arch/mips/include/asm/netlogic/xlr/flash.h
Diff comments   View file @ 3a2f9b9
  1 +/*
  2 + * Copyright (c) 2003-2012 Broadcom Corporation
  3 + * All Rights Reserved
  4 + *
  5 + * This software is available to you under a choice of one of two
  6 + * licenses. You may choose to be licensed under the terms of the GNU
  7 + * General Public License (GPL) Version 2, available from the file
  8 + * COPYING in the main directory of this source tree, or the Broadcom
  9 + * license below:
  10 + *
  11 + * Redistribution and use in source and binary forms, with or without
  12 + * modification, are permitted provided that the following conditions
  13 + * are met:
  14 + *
  15 + * 1. Redistributions of source code must retain the above copyright
  16 + * notice, this list of conditions and the following disclaimer.
  17 + * 2. Redistributions in binary form must reproduce the above copyright
  18 + * notice, this list of conditions and the following disclaimer in
  19 + * the documentation and/or other materials provided with the
  20 + * distribution.
  21 + *
  22 + * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
  23 + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24 + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  25 + * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
  26 + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  27 + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  28 + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  29 + * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  30 + * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
  31 + * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
  32 + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33 + */
  34 +#ifndef _ASM_NLM_FLASH_H_
  35 +#define _ASM_NLM_FLASH_H_
  36 +
  37 +#define FLASH_CSBASE_ADDR(cs) (cs)
  38 +#define FLASH_CSADDR_MASK(cs) (0x10 + (cs))
  39 +#define FLASH_CSDEV_PARM(cs) (0x20 + (cs))
  40 +#define FLASH_CSTIME_PARMA(cs) (0x30 + (cs))
  41 +#define FLASH_CSTIME_PARMB(cs) (0x40 + (cs))
  42 +
  43 +#define FLASH_INT_MASK 0x50
  44 +#define FLASH_INT_STATUS 0x60
  45 +#define FLASH_ERROR_STATUS 0x70
  46 +#define FLASH_ERROR_ADDR 0x80
  47 +
  48 +#define FLASH_NAND_CLE(cs) (0x90 + (cs))
  49 +#define FLASH_NAND_ALE(cs) (0xa0 + (cs))
  50 +
  51 +#define FLASH_NAND_CSDEV_PARAM 0x000041e6
  52 +#define FLASH_NAND_CSTIME_PARAMA 0x4f400e22
  53 +#define FLASH_NAND_CSTIME_PARAMB 0x000083cf
  54 +
  55 +#endif
arch/mips/netlogic/xlr/Makefile
Diff comments   View file @ 3a2f9b9
1   -obj-y += setup.o platform.o
  1 +obj-y += setup.o platform.o platform-flash.o
2 2 obj-$(CONFIG_SMP) += wakeup.o
arch/mips/netlogic/xlr/platform-flash.c
Diff comments   View file @ 3a2f9b9
  1 +/*
  2 + * Copyright 2011, Netlogic Microsystems.
  3 + * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
  4 + *
  5 + * This file is licensed under the terms of the GNU General Public
  6 + * License version 2. This program is licensed "as is" without any
  7 + * warranty of any kind, whether express or implied.
  8 + */
  9 +
  10 +#include <linux/device.h>
  11 +#include <linux/platform_device.h>
  12 +#include <linux/kernel.h>
  13 +#include <linux/init.h>
  14 +#include <linux/io.h>
  15 +#include <linux/delay.h>
  16 +#include <linux/ioport.h>
  17 +#include <linux/resource.h>
  18 +#include <linux/spi/flash.h>
  19 +
  20 +#include <linux/mtd/mtd.h>
  21 +#include <linux/mtd/physmap.h>
  22 +#include <linux/mtd/nand.h>
  23 +#include <linux/mtd/partitions.h>
  24 +
  25 +#include <asm/netlogic/haldefs.h>
  26 +#include <asm/netlogic/xlr/iomap.h>
  27 +#include <asm/netlogic/xlr/flash.h>
  28 +#include <asm/netlogic/xlr/bridge.h>
  29 +#include <asm/netlogic/xlr/gpio.h>
  30 +#include <asm/netlogic/xlr/xlr.h>
  31 +
  32 +/*
  33 + * Default NOR partition layout
  34 + */
  35 +static struct mtd_partition xlr_nor_parts[] = {
  36 + {
  37 + .name = "User FS",
  38 + .offset = 0x800000,
  39 + .size = MTDPART_SIZ_FULL,
  40 + }
  41 +};
  42 +
  43 +/*
  44 + * Default NAND partition layout
  45 + */
  46 +static struct mtd_partition xlr_nand_parts[] = {
  47 + {
  48 + .name = "Root Filesystem",
  49 + .offset = 64 * 64 * 2048,
  50 + .size = 432 * 64 * 2048,
  51 + },
  52 + {
  53 + .name = "Home Filesystem",
  54 + .offset = MTDPART_OFS_APPEND,
  55 + .size = MTDPART_SIZ_FULL,
  56 + },
  57 +};
  58 +
  59 +/* Use PHYSMAP flash for NOR */
  60 +struct physmap_flash_data xlr_nor_data = {
  61 + .width = 2,
  62 + .parts = xlr_nor_parts,
  63 + .nr_parts = ARRAY_SIZE(xlr_nor_parts),
  64 +};
  65 +
  66 +static struct resource xlr_nor_res[] = {
  67 + {
  68 + .flags = IORESOURCE_MEM,
  69 + },
  70 +};
  71 +
  72 +static struct platform_device xlr_nor_dev = {
  73 + .name = "physmap-flash",
  74 + .dev = {
  75 + .platform_data = &xlr_nor_data,
  76 + },
  77 + .num_resources = ARRAY_SIZE(xlr_nor_res),
  78 + .resource = xlr_nor_res,
  79 +};
  80 +
  81 +const char *xlr_part_probes[] = { "cmdlinepart", NULL };
  82 +
  83 +/*
  84 + * Use "gen_nand" driver for NAND flash
  85 + *
  86 + * There seems to be no way to store a private pointer containing
  87 + * platform specific info in gen_nand drivier. We will use a global
  88 + * struct for now, since we currently have only one NAND chip per board.
  89 + */
  90 +struct xlr_nand_flash_priv {
  91 + int cs;
  92 + uint64_t flash_mmio;
  93 +};
  94 +
  95 +static struct xlr_nand_flash_priv nand_priv;
  96 +
  97 +static void xlr_nand_ctrl(struct mtd_info *mtd, int cmd,
  98 + unsigned int ctrl)
  99 +{
  100 + if (ctrl & NAND_CLE)
  101 + nlm_write_reg(nand_priv.flash_mmio,
  102 + FLASH_NAND_CLE(nand_priv.cs), cmd);
  103 + else if (ctrl & NAND_ALE)
  104 + nlm_write_reg(nand_priv.flash_mmio,
  105 + FLASH_NAND_ALE(nand_priv.cs), cmd);
  106 +}
  107 +
  108 +struct platform_nand_data xlr_nand_data = {
  109 + .chip = {
  110 + .nr_chips = 1,
  111 + .nr_partitions = ARRAY_SIZE(xlr_nand_parts),
  112 + .chip_delay = 50,
  113 + .partitions = xlr_nand_parts,
  114 + .part_probe_types = xlr_part_probes,
  115 + },
  116 + .ctrl = {
  117 + .cmd_ctrl = xlr_nand_ctrl,
  118 + },
  119 +};
  120 +
  121 +static struct resource xlr_nand_res[] = {
  122 + {
  123 + .flags = IORESOURCE_MEM,
  124 + },
  125 +};
  126 +
  127 +static struct platform_device xlr_nand_dev = {
  128 + .name = "gen_nand",
  129 + .id = -1,
  130 + .num_resources = ARRAY_SIZE(xlr_nand_res),
  131 + .resource = xlr_nand_res,
  132 + .dev = {
  133 + .platform_data = &xlr_nand_data,
  134 + }
  135 +};
  136 +
  137 +/*
  138 + * XLR/XLS supports upto 8 devices on its FLASH interface. The value in
  139 + * FLASH_BAR (on the MEM/IO bridge) gives the base for mapping all the
  140 + * flash devices.
  141 + * Under this, each flash device has an offset and size given by the
  142 + * CSBASE_ADDR and CSBASE_MASK registers for the device.
  143 + *
  144 + * The CSBASE_ registers are expected to be setup by the bootloader.
  145 + */
  146 +static void setup_flash_resource(uint64_t flash_mmio,
  147 + uint64_t flash_map_base, int cs, struct resource *res)
  148 +{
  149 + u32 base, mask;
  150 +
  151 + base = nlm_read_reg(flash_mmio, FLASH_CSBASE_ADDR(cs));
  152 + mask = nlm_read_reg(flash_mmio, FLASH_CSADDR_MASK(cs));
  153 +
  154 + res->start = flash_map_base + ((unsigned long)base << 16);
  155 + res->end = res->start + (mask + 1) * 64 * 1024;
  156 +}
  157 +
  158 +static int __init xlr_flash_init(void)
  159 +{
  160 + uint64_t gpio_mmio, flash_mmio, flash_map_base;
  161 + u32 gpio_resetcfg, flash_bar;
  162 + int cs, boot_nand, boot_nor;
  163 +
  164 + /* Flash address bits 39:24 is in bridge flash BAR */
  165 + flash_bar = nlm_read_reg(nlm_io_base, BRIDGE_FLASH_BAR);
  166 + flash_map_base = (flash_bar & 0xffff0000) << 8;
  167 +
  168 + gpio_mmio = nlm_mmio_base(NETLOGIC_IO_GPIO_OFFSET);
  169 + flash_mmio = nlm_mmio_base(NETLOGIC_IO_FLASH_OFFSET);
  170 +
  171 + /* Get the chip reset config */
  172 + gpio_resetcfg = nlm_read_reg(gpio_mmio, GPIO_PWRON_RESET_CFG_REG);
  173 +
  174 + /* Check for boot flash type */
  175 + boot_nor = boot_nand = 0;
  176 + if (nlm_chip_is_xls()) {
  177 + /* On XLS, check boot from NAND bit (GPIO reset reg bit 16) */
  178 + if (gpio_resetcfg & (1 << 16))
  179 + boot_nand = 1;
  180 +
  181 + /* check boot from PCMCIA, (GPIO reset reg bit 15 */
  182 + if ((gpio_resetcfg & (1 << 15)) == 0)
  183 + boot_nor = 1; /* not set, booted from NOR */
  184 + } else { /* XLR */
  185 + /* check boot from PCMCIA (bit 16 in GPIO reset on XLR) */
  186 + if ((gpio_resetcfg & (1 << 16)) == 0)
  187 + boot_nor = 1; /* not set, booted from NOR */
  188 + }
  189 +
  190 + /* boot flash at chip select 0 */
  191 + cs = 0;
  192 +
  193 + if (boot_nand) {
  194 + nand_priv.cs = cs;
  195 + nand_priv.flash_mmio = flash_mmio;
  196 + setup_flash_resource(flash_mmio, flash_map_base, cs,
  197 + xlr_nand_res);
  198 +
  199 + /* Initialize NAND flash at CS 0 */
  200 + nlm_write_reg(flash_mmio, FLASH_CSDEV_PARM(cs),
  201 + FLASH_NAND_CSDEV_PARAM);
  202 + nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMA(cs),
  203 + FLASH_NAND_CSTIME_PARAMA);
  204 + nlm_write_reg(flash_mmio, FLASH_CSTIME_PARMB(cs),
  205 + FLASH_NAND_CSTIME_PARAMB);
  206 +
  207 + pr_info("ChipSelect %d: NAND Flash %pR\n", cs, xlr_nand_res);
  208 + return platform_device_register(&xlr_nand_dev);
  209 + }
  210 +
  211 + if (boot_nor) {
  212 + setup_flash_resource(flash_mmio, flash_map_base, cs,
  213 + xlr_nor_res);
  214 + pr_info("ChipSelect %d: NOR Flash %pR\n", cs, xlr_nor_res);
  215 + return platform_device_register(&xlr_nor_dev);
  216 + }
  217 + return 0;
  218 +}
  219 +
  220 +arch_initcall(xlr_flash_init);