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Commit 3a95b9fbba893ebfa9b83de105707539e0228e0c

Authored by Alessandro Rubini
Committed by Vinod Koul
1 parent a5dbff111c
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

pl080.h: moved from arm/include/asm/hardware to include/linux/amba/ 

The header is used by drivers/dma/amba-pl08x.c, which can be compiled
under x86, where PL080 exists under a PCI-to-AMBA bridge. This patche
moves it where it can be accessed by other architectures, and fixes
all users.

Signed-off-by: Alessandro Rubini <rubini@gnudd.com>
Acked-by: Giancarlo Asnaghi <giancarlo.asnaghi@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>

Showing 6 changed files with 149 additions and 150 deletions Side-by-side Diff

arch/arm/include/asm/hardware/pl080.h
View file @ 3a95b9f
1   -/* arch/arm/include/asm/hardware/pl080.h
2   - *
3   - * Copyright 2008 Openmoko, Inc.
4   - * Copyright 2008 Simtec Electronics
5   - * http://armlinux.simtec.co.uk/
6   - * Ben Dooks <ben@simtec.co.uk>
7   - *
8   - * ARM PrimeCell PL080 DMA controller
9   - *
10   - * This program is free software; you can redistribute it and/or modify
11   - * it under the terms of the GNU General Public License version 2 as
12   - * published by the Free Software Foundation.
13   -*/
14   -
15   -/* Note, there are some Samsung updates to this controller block which
16   - * make it not entierly compatible with the PL080 specification from
17   - * ARM. When in doubt, check the Samsung documentation first.
18   - *
19   - * The Samsung defines are PL080S, and add an extra control register,
20   - * the ability to move more than 2^11 counts of data and some extra
21   - * OneNAND features.
22   -*/
23   -
24   -#ifndef ASM_PL080_H
25   -#define ASM_PL080_H
26   -
27   -#define PL080_INT_STATUS (0x00)
28   -#define PL080_TC_STATUS (0x04)
29   -#define PL080_TC_CLEAR (0x08)
30   -#define PL080_ERR_STATUS (0x0C)
31   -#define PL080_ERR_CLEAR (0x10)
32   -#define PL080_RAW_TC_STATUS (0x14)
33   -#define PL080_RAW_ERR_STATUS (0x18)
34   -#define PL080_EN_CHAN (0x1c)
35   -#define PL080_SOFT_BREQ (0x20)
36   -#define PL080_SOFT_SREQ (0x24)
37   -#define PL080_SOFT_LBREQ (0x28)
38   -#define PL080_SOFT_LSREQ (0x2C)
39   -
40   -#define PL080_CONFIG (0x30)
41   -#define PL080_CONFIG_M2_BE (1 << 2)
42   -#define PL080_CONFIG_M1_BE (1 << 1)
43   -#define PL080_CONFIG_ENABLE (1 << 0)
44   -
45   -#define PL080_SYNC (0x34)
46   -
47   -/* Per channel configuration registers */
48   -
49   -#define PL080_Cx_STRIDE (0x20)
50   -#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
51   -#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
52   -#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
53   -#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
54   -#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
55   -#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
56   -#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
57   -#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
58   -
59   -#define PL080_CH_SRC_ADDR (0x00)
60   -#define PL080_CH_DST_ADDR (0x04)
61   -#define PL080_CH_LLI (0x08)
62   -#define PL080_CH_CONTROL (0x0C)
63   -#define PL080_CH_CONFIG (0x10)
64   -#define PL080S_CH_CONTROL2 (0x10)
65   -#define PL080S_CH_CONFIG (0x14)
66   -
67   -#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
68   -#define PL080_LLI_ADDR_SHIFT (2)
69   -#define PL080_LLI_LM_AHB2 (1 << 0)
70   -
71   -#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
72   -#define PL080_CONTROL_PROT_MASK (0x7 << 28)
73   -#define PL080_CONTROL_PROT_SHIFT (28)
74   -#define PL080_CONTROL_PROT_CACHE (1 << 30)
75   -#define PL080_CONTROL_PROT_BUFF (1 << 29)
76   -#define PL080_CONTROL_PROT_SYS (1 << 28)
77   -#define PL080_CONTROL_DST_INCR (1 << 27)
78   -#define PL080_CONTROL_SRC_INCR (1 << 26)
79   -#define PL080_CONTROL_DST_AHB2 (1 << 25)
80   -#define PL080_CONTROL_SRC_AHB2 (1 << 24)
81   -#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
82   -#define PL080_CONTROL_DWIDTH_SHIFT (21)
83   -#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
84   -#define PL080_CONTROL_SWIDTH_SHIFT (18)
85   -#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
86   -#define PL080_CONTROL_DB_SIZE_SHIFT (15)
87   -#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
88   -#define PL080_CONTROL_SB_SIZE_SHIFT (12)
89   -#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
90   -#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
91   -
92   -#define PL080_BSIZE_1 (0x0)
93   -#define PL080_BSIZE_4 (0x1)
94   -#define PL080_BSIZE_8 (0x2)
95   -#define PL080_BSIZE_16 (0x3)
96   -#define PL080_BSIZE_32 (0x4)
97   -#define PL080_BSIZE_64 (0x5)
98   -#define PL080_BSIZE_128 (0x6)
99   -#define PL080_BSIZE_256 (0x7)
100   -
101   -#define PL080_WIDTH_8BIT (0x0)
102   -#define PL080_WIDTH_16BIT (0x1)
103   -#define PL080_WIDTH_32BIT (0x2)
104   -
105   -#define PL080N_CONFIG_ITPROT (1 << 20)
106   -#define PL080N_CONFIG_SECPROT (1 << 19)
107   -#define PL080_CONFIG_HALT (1 << 18)
108   -#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
109   -#define PL080_CONFIG_LOCK (1 << 16)
110   -#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
111   -#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
112   -#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
113   -#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
114   -#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
115   -#define PL080_CONFIG_DST_SEL_SHIFT (6)
116   -#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
117   -#define PL080_CONFIG_SRC_SEL_SHIFT (1)
118   -#define PL080_CONFIG_ENABLE (1 << 0)
119   -
120   -#define PL080_FLOW_MEM2MEM (0x0)
121   -#define PL080_FLOW_MEM2PER (0x1)
122   -#define PL080_FLOW_PER2MEM (0x2)
123   -#define PL080_FLOW_SRC2DST (0x3)
124   -#define PL080_FLOW_SRC2DST_DST (0x4)
125   -#define PL080_FLOW_MEM2PER_PER (0x5)
126   -#define PL080_FLOW_PER2MEM_PER (0x6)
127   -#define PL080_FLOW_SRC2DST_SRC (0x7)
128   -
129   -/* DMA linked list chain structure */
130   -
131   -struct pl080_lli {
132   - u32 src_addr;
133   - u32 dst_addr;
134   - u32 next_lli;
135   - u32 control0;
136   -};
137   -
138   -struct pl080s_lli {
139   - u32 src_addr;
140   - u32 dst_addr;
141   - u32 next_lli;
142   - u32 control0;
143   - u32 control1;
144   -};
145   -
146   -#endif /* ASM_PL080_H */
arch/arm/mach-s3c64xx/dma.c
Diff comments   View file @ 3a95b9f
... ... @@ -23,6 +23,7 @@
23 23 #include <linux/clk.h>
24 24 #include <linux/err.h>
25 25 #include <linux/io.h>
  26 +#include <linux/amba/pl080.h>
26 27  
27 28 #include <mach/dma.h>
28 29 #include <mach/map.h>
... ... @@ -30,7 +31,6 @@
30 31  
31 32 #include <mach/regs-sys.h>
32 33  
33   -#include <asm/hardware/pl080.h>
34 34  
35 35 /* dma channel state information */
36 36  
arch/arm/mach-spear3xx/spear3xx.c
Diff comments   View file @ 3a95b9f
... ... @@ -18,7 +18,6 @@
18 18 #include <linux/irqchip/spear-shirq.h>
19 19 #include <linux/of_irq.h>
20 20 #include <linux/io.h>
21   -#include <asm/hardware/pl080.h>
22 21 #include <asm/hardware/vic.h>
23 22 #include <plat/pl080.h>
24 23 #include <mach/generic.h>
arch/arm/mach-spear6xx/spear6xx.c
Diff comments   View file @ 3a95b9f
... ... @@ -20,7 +20,7 @@
20 20 #include <linux/of_address.h>
21 21 #include <linux/of_irq.h>
22 22 #include <linux/of_platform.h>
23   -#include <asm/hardware/pl080.h>
  23 +#include <linux/amba/pl080.h>
24 24 #include <asm/hardware/vic.h>
25 25 #include <asm/mach/arch.h>
26 26 #include <asm/mach/time.h>
drivers/dma/amba-pl08x.c
Diff comments   View file @ 3a95b9f
... ... @@ -83,7 +83,7 @@
83 83 #include <linux/pm_runtime.h>
84 84 #include <linux/seq_file.h>
85 85 #include <linux/slab.h>
86   -#include <asm/hardware/pl080.h>
  86 +#include <linux/amba/pl080.h>
87 87  
88 88 #include "dmaengine.h"
89 89 #include "virt-dma.h"
include/linux/amba/pl080.h
Diff comments   View file @ 3a95b9f
  1 +/* include/linux/amba/pl080.h
  2 + *
  3 + * Copyright 2008 Openmoko, Inc.
  4 + * Copyright 2008 Simtec Electronics
  5 + * http://armlinux.simtec.co.uk/
  6 + * Ben Dooks <ben@simtec.co.uk>
  7 + *
  8 + * ARM PrimeCell PL080 DMA controller
  9 + *
  10 + * This program is free software; you can redistribute it and/or modify
  11 + * it under the terms of the GNU General Public License version 2 as
  12 + * published by the Free Software Foundation.
  13 +*/
  14 +
  15 +/* Note, there are some Samsung updates to this controller block which
  16 + * make it not entierly compatible with the PL080 specification from
  17 + * ARM. When in doubt, check the Samsung documentation first.
  18 + *
  19 + * The Samsung defines are PL080S, and add an extra control register,
  20 + * the ability to move more than 2^11 counts of data and some extra
  21 + * OneNAND features.
  22 +*/
  23 +
  24 +#ifndef ASM_PL080_H
  25 +#define ASM_PL080_H
  26 +
  27 +#define PL080_INT_STATUS (0x00)
  28 +#define PL080_TC_STATUS (0x04)
  29 +#define PL080_TC_CLEAR (0x08)
  30 +#define PL080_ERR_STATUS (0x0C)
  31 +#define PL080_ERR_CLEAR (0x10)
  32 +#define PL080_RAW_TC_STATUS (0x14)
  33 +#define PL080_RAW_ERR_STATUS (0x18)
  34 +#define PL080_EN_CHAN (0x1c)
  35 +#define PL080_SOFT_BREQ (0x20)
  36 +#define PL080_SOFT_SREQ (0x24)
  37 +#define PL080_SOFT_LBREQ (0x28)
  38 +#define PL080_SOFT_LSREQ (0x2C)
  39 +
  40 +#define PL080_CONFIG (0x30)
  41 +#define PL080_CONFIG_M2_BE (1 << 2)
  42 +#define PL080_CONFIG_M1_BE (1 << 1)
  43 +#define PL080_CONFIG_ENABLE (1 << 0)
  44 +
  45 +#define PL080_SYNC (0x34)
  46 +
  47 +/* Per channel configuration registers */
  48 +
  49 +#define PL080_Cx_STRIDE (0x20)
  50 +#define PL080_Cx_BASE(x) ((0x100 + (x * 0x20)))
  51 +#define PL080_Cx_SRC_ADDR(x) ((0x100 + (x * 0x20)))
  52 +#define PL080_Cx_DST_ADDR(x) ((0x104 + (x * 0x20)))
  53 +#define PL080_Cx_LLI(x) ((0x108 + (x * 0x20)))
  54 +#define PL080_Cx_CONTROL(x) ((0x10C + (x * 0x20)))
  55 +#define PL080_Cx_CONFIG(x) ((0x110 + (x * 0x20)))
  56 +#define PL080S_Cx_CONTROL2(x) ((0x110 + (x * 0x20)))
  57 +#define PL080S_Cx_CONFIG(x) ((0x114 + (x * 0x20)))
  58 +
  59 +#define PL080_CH_SRC_ADDR (0x00)
  60 +#define PL080_CH_DST_ADDR (0x04)
  61 +#define PL080_CH_LLI (0x08)
  62 +#define PL080_CH_CONTROL (0x0C)
  63 +#define PL080_CH_CONFIG (0x10)
  64 +#define PL080S_CH_CONTROL2 (0x10)
  65 +#define PL080S_CH_CONFIG (0x14)
  66 +
  67 +#define PL080_LLI_ADDR_MASK (0x3fffffff << 2)
  68 +#define PL080_LLI_ADDR_SHIFT (2)
  69 +#define PL080_LLI_LM_AHB2 (1 << 0)
  70 +
  71 +#define PL080_CONTROL_TC_IRQ_EN (1 << 31)
  72 +#define PL080_CONTROL_PROT_MASK (0x7 << 28)
  73 +#define PL080_CONTROL_PROT_SHIFT (28)
  74 +#define PL080_CONTROL_PROT_CACHE (1 << 30)
  75 +#define PL080_CONTROL_PROT_BUFF (1 << 29)
  76 +#define PL080_CONTROL_PROT_SYS (1 << 28)
  77 +#define PL080_CONTROL_DST_INCR (1 << 27)
  78 +#define PL080_CONTROL_SRC_INCR (1 << 26)
  79 +#define PL080_CONTROL_DST_AHB2 (1 << 25)
  80 +#define PL080_CONTROL_SRC_AHB2 (1 << 24)
  81 +#define PL080_CONTROL_DWIDTH_MASK (0x7 << 21)
  82 +#define PL080_CONTROL_DWIDTH_SHIFT (21)
  83 +#define PL080_CONTROL_SWIDTH_MASK (0x7 << 18)
  84 +#define PL080_CONTROL_SWIDTH_SHIFT (18)
  85 +#define PL080_CONTROL_DB_SIZE_MASK (0x7 << 15)
  86 +#define PL080_CONTROL_DB_SIZE_SHIFT (15)
  87 +#define PL080_CONTROL_SB_SIZE_MASK (0x7 << 12)
  88 +#define PL080_CONTROL_SB_SIZE_SHIFT (12)
  89 +#define PL080_CONTROL_TRANSFER_SIZE_MASK (0xfff << 0)
  90 +#define PL080_CONTROL_TRANSFER_SIZE_SHIFT (0)
  91 +
  92 +#define PL080_BSIZE_1 (0x0)
  93 +#define PL080_BSIZE_4 (0x1)
  94 +#define PL080_BSIZE_8 (0x2)
  95 +#define PL080_BSIZE_16 (0x3)
  96 +#define PL080_BSIZE_32 (0x4)
  97 +#define PL080_BSIZE_64 (0x5)
  98 +#define PL080_BSIZE_128 (0x6)
  99 +#define PL080_BSIZE_256 (0x7)
  100 +
  101 +#define PL080_WIDTH_8BIT (0x0)
  102 +#define PL080_WIDTH_16BIT (0x1)
  103 +#define PL080_WIDTH_32BIT (0x2)
  104 +
  105 +#define PL080N_CONFIG_ITPROT (1 << 20)
  106 +#define PL080N_CONFIG_SECPROT (1 << 19)
  107 +#define PL080_CONFIG_HALT (1 << 18)
  108 +#define PL080_CONFIG_ACTIVE (1 << 17) /* RO */
  109 +#define PL080_CONFIG_LOCK (1 << 16)
  110 +#define PL080_CONFIG_TC_IRQ_MASK (1 << 15)
  111 +#define PL080_CONFIG_ERR_IRQ_MASK (1 << 14)
  112 +#define PL080_CONFIG_FLOW_CONTROL_MASK (0x7 << 11)
  113 +#define PL080_CONFIG_FLOW_CONTROL_SHIFT (11)
  114 +#define PL080_CONFIG_DST_SEL_MASK (0xf << 6)
  115 +#define PL080_CONFIG_DST_SEL_SHIFT (6)
  116 +#define PL080_CONFIG_SRC_SEL_MASK (0xf << 1)
  117 +#define PL080_CONFIG_SRC_SEL_SHIFT (1)
  118 +#define PL080_CONFIG_ENABLE (1 << 0)
  119 +
  120 +#define PL080_FLOW_MEM2MEM (0x0)
  121 +#define PL080_FLOW_MEM2PER (0x1)
  122 +#define PL080_FLOW_PER2MEM (0x2)
  123 +#define PL080_FLOW_SRC2DST (0x3)
  124 +#define PL080_FLOW_SRC2DST_DST (0x4)
  125 +#define PL080_FLOW_MEM2PER_PER (0x5)
  126 +#define PL080_FLOW_PER2MEM_PER (0x6)
  127 +#define PL080_FLOW_SRC2DST_SRC (0x7)
  128 +
  129 +/* DMA linked list chain structure */
  130 +
  131 +struct pl080_lli {
  132 + u32 src_addr;
  133 + u32 dst_addr;
  134 + u32 next_lli;
  135 + u32 control0;
  136 +};
  137 +
  138 +struct pl080s_lli {
  139 + u32 src_addr;
  140 + u32 dst_addr;
  141 + u32 next_lli;
  142 + u32 control0;
  143 + u32 control1;
  144 +};
  145 +
  146 +#endif /* ASM_PL080_H */