ASoC: fsi: Add new funtion for SPDIF

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>

ASoC: fsi: Add new funtion for SPDIF
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Liam Girdwood <lrg@slimlogic.co.uk> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Kuninori Morimoto · Mark Brown
1 parent 265c770d03
Showing 2 changed files with 57 additions and 5 deletions Side-by-side Diff
include/sound/sh_fsi.h
sound/soc/sh/fsi.c
@@ -64,6 +64,8 @@
 #define SH_FSI_FMT_I2S		3
 #define SH_FSI_FMT_TDM		4
 #define SH_FSI_FMT_TDM_DELAY	5
+#define SH_FSI_FMT_SPDIF	6
+
  
 #define SH_FSI_IFMT_TDM_CH(x) \
 	(SH_FSI_IFMT(TDM)	| SH_FSI_SET_CH_I(x))
@@ -30,9 +30,11 @@
 #define DIDT		0x0020
 #define DODT		0x0024
 #define MUTE_ST		0x0028
-#define REG_END		MUTE_ST
+#define OUT_SEL		0x0030
+#define REG_END		OUT_SEL
  
-
+#define A_MST_CTLR	0x0180
+#define B_MST_CTLR	0x01A0
 #define CPU_INT_ST	0x01F4
 #define CPU_IEMSK	0x01F8
 #define CPU_IMSK	0x01FC
@@ -43,7 +45,7 @@
 #define CLK_RST		0x0210
 #define SOFT_RST	0x0214
 #define FIFO_SZ		0x0218
-#define MREG_START	CPU_INT_ST
+#define MREG_START	A_MST_CTLR
 #define MREG_END	FIFO_SZ
  
 /* DO_FMT */
@@ -54,6 +56,7 @@
 #define CR_I2S		(0x3 << 4)
 #define CR_TDM		(0x4 << 4)
 #define CR_TDM_D	(0x5 << 4)
+#define CR_SPDIF	0x00100120
  
 /* DOFF_CTL */
 /* DIFF_CTL */
@@ -69,6 +72,10 @@
 #define ACKMD_MASK	0x00007000
 #define BPFMD_MASK	0x00000700
  
+/* A/B MST_CTLR */
+#define BP	(1 << 4)	/* Fix the signal of Biphase output */
+#define SE	(1 << 0)	/* Fix the master clock */
+
 /* CLK_RST */
 #define B_CLK		0x00000010
 #define A_CLK		0x00000001
@@ -113,6 +120,8 @@
 	int period_len;
 	int buffer_len;
 	int periods;
+
+	u32 mst_ctrl;
 };
  
 struct fsi_core {
@@ -395,6 +404,29 @@
 /************************************************************************
  
  
+		SPDIF master clock function
+
+These functions are used later FSI2
+************************************************************************/
+static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
+{
+	struct fsi_master *master = fsi_get_master(fsi);
+	u32 val = BP | SE;
+
+	if (master->core->ver < 2) {
+		pr_err("fsi: register access err (%s)\n", __func__);
+		return;
+	}
+
+	if (enable)
+		fsi_master_mask_set(master, fsi->mst_ctrl, val, val);
+	else
+		fsi_master_mask_set(master, fsi->mst_ctrl, val, 0);
+}
+
+/************************************************************************
+
+
 		ctrl function
  
  
@@ -671,6 +703,7 @@
 {
 	struct fsi_priv *fsi = fsi_get_priv(substream);
 	u32 flags = fsi_get_info_flags(fsi);
+	struct fsi_master *master = fsi_get_master(fsi);
 	u32 fmt;
 	u32 reg;
 	u32 data;
@@ -732,6 +765,16 @@
 			SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
 		data = CR_TDM_D | (fsi->chan - 1);
 		break;
+	case SH_FSI_FMT_SPDIF:
+		if (master->core->ver < 2) {
+			dev_err(dai->dev, "This FSI can not use SPDIF\n");
+			return -EINVAL;
+		}
+		data = CR_SPDIF;
+		fsi->chan = 2;
+		fsi_spdif_clk_ctrl(fsi, 1);
+		fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010);
+		break;
 	default:
 		dev_err(dai->dev, "unknown format.\n");
 		return -EINVAL;
  
  
  
@@ -1071,14 +1114,21 @@
 		goto exit_kfree;
 	}
  
+	/* master setting */
 	master->irq		= irq;
 	master->info		= pdev->dev.platform_data;
+	master->core		= (struct fsi_core *)id_entry->driver_data;
+	spin_lock_init(&master->lock);
+
+	/* FSI A setting */
 	master->fsia.base	= master->base;
 	master->fsia.master	= master;
+	master->fsia.mst_ctrl	= A_MST_CTLR;
+
+	/* FSI B setting */
 	master->fsib.base	= master->base + 0x40;
 	master->fsib.master	= master;
-	master->core		= (struct fsi_core *)id_entry->driver_data;
-	spin_lock_init(&master->lock);
+	master->fsib.mst_ctrl	= B_MST_CTLR;
  
 	pm_runtime_enable(&pdev->dev);
 	pm_runtime_resume(&pdev->dev);
...	...	@@ -64,6 +64,8 @@
64	64	#define SH_FSI_FMT_I2S 3
65	65	#define SH_FSI_FMT_TDM 4
66	66	#define SH_FSI_FMT_TDM_DELAY 5
	67	+#define SH_FSI_FMT_SPDIF 6
	68	+
67	69
68	70	#define SH_FSI_IFMT_TDM_CH(x) \
69	71	(SH_FSI_IFMT(TDM) \| SH_FSI_SET_CH_I(x))
...	...	@@ -30,9 +30,11 @@
30	30	#define DIDT 0x0020
31	31	#define DODT 0x0024
32	32	#define MUTE_ST 0x0028
33		-#define REG_END MUTE_ST
	33	+#define OUT_SEL 0x0030
	34	+#define REG_END OUT_SEL
34	35
35		-
	36	+#define A_MST_CTLR 0x0180
	37	+#define B_MST_CTLR 0x01A0
36	38	#define CPU_INT_ST 0x01F4
37	39	#define CPU_IEMSK 0x01F8
38	40	#define CPU_IMSK 0x01FC
...	...	@@ -43,7 +45,7 @@
43	45	#define CLK_RST 0x0210
44	46	#define SOFT_RST 0x0214
45	47	#define FIFO_SZ 0x0218
46		-#define MREG_START CPU_INT_ST
	48	+#define MREG_START A_MST_CTLR
47	49	#define MREG_END FIFO_SZ
48	50
49	51	/* DO_FMT */
...	...	@@ -54,6 +56,7 @@
54	56	#define CR_I2S (0x3 << 4)
55	57	#define CR_TDM (0x4 << 4)
56	58	#define CR_TDM_D (0x5 << 4)
	59	+#define CR_SPDIF 0x00100120
57	60
58	61	/* DOFF_CTL */
59	62	/* DIFF_CTL */
...	...	@@ -69,6 +72,10 @@
69	72	#define ACKMD_MASK 0x00007000
70	73	#define BPFMD_MASK 0x00000700
71	74
	75	+/* A/B MST_CTLR */
	76	+#define BP (1 << 4) /* Fix the signal of Biphase output */
	77	+#define SE (1 << 0) /* Fix the master clock */
	78	+
72	79	/* CLK_RST */
73	80	#define B_CLK 0x00000010
74	81	#define A_CLK 0x00000001
...	...	@@ -113,6 +120,8 @@
113	120	int period_len;
114	121	int buffer_len;
115	122	int periods;
	123	+
	124	+ u32 mst_ctrl;
116	125	};
117	126
118	127	struct fsi_core {
...	...	@@ -395,6 +404,29 @@
395	404	/************************************************************************
396	405
397	406
	407	+ SPDIF master clock function
	408	+
	409	+These functions are used later FSI2
	410	+************************************************************************/
	411	+static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
	412	+{
	413	+ struct fsi_master *master = fsi_get_master(fsi);
	414	+ u32 val = BP \| SE;
	415	+
	416	+ if (master->core->ver < 2) {
	417	+ pr_err("fsi: register access err (%s)\n", __func__);
	418	+ return;
	419	+ }
	420	+
	421	+ if (enable)
	422	+ fsi_master_mask_set(master, fsi->mst_ctrl, val, val);
	423	+ else
	424	+ fsi_master_mask_set(master, fsi->mst_ctrl, val, 0);
	425	+}
	426	+
	427	+/************************************************************************
	428	+
	429	+
398	430	ctrl function
399	431
400	432
...	...	@@ -671,6 +703,7 @@
671	703	{
672	704	struct fsi_priv *fsi = fsi_get_priv(substream);
673	705	u32 flags = fsi_get_info_flags(fsi);
	706	+ struct fsi_master *master = fsi_get_master(fsi);
674	707	u32 fmt;
675	708	u32 reg;
676	709	u32 data;
...	...	@@ -732,6 +765,16 @@
732	765	SH_FSI_GET_CH_O(flags) : SH_FSI_GET_CH_I(flags);
733	766	data = CR_TDM_D \| (fsi->chan - 1);
734	767	break;
	768	+ case SH_FSI_FMT_SPDIF:
	769	+ if (master->core->ver < 2) {
	770	+ dev_err(dai->dev, "This FSI can not use SPDIF\n");
	771	+ return -EINVAL;
	772	+ }
	773	+ data = CR_SPDIF;
	774	+ fsi->chan = 2;
	775	+ fsi_spdif_clk_ctrl(fsi, 1);
	776	+ fsi_reg_mask_set(fsi, OUT_SEL, 0x0010, 0x0010);
	777	+ break;
735	778	default:
736	779	dev_err(dai->dev, "unknown format.\n");
737	780	return -EINVAL;
738	781
739	782
740	783
...	...	@@ -1071,14 +1114,21 @@
1071	1114	goto exit_kfree;
1072	1115	}
1073	1116
	1117	+ /* master setting */
1074	1118	master->irq = irq;
1075	1119	master->info = pdev->dev.platform_data;
	1120	+ master->core = (struct fsi_core *)id_entry->driver_data;
	1121	+ spin_lock_init(&master->lock);
	1122	+
	1123	+ /* FSI A setting */
1076	1124	master->fsia.base = master->base;
1077	1125	master->fsia.master = master;
	1126	+ master->fsia.mst_ctrl = A_MST_CTLR;
	1127	+
	1128	+ /* FSI B setting */
1078	1129	master->fsib.base = master->base + 0x40;
1079	1130	master->fsib.master = master;
1080		- master->core = (struct fsi_core *)id_entry->driver_data;
1081		- spin_lock_init(&master->lock);
	1131	+ master->fsib.mst_ctrl = B_MST_CTLR;
1082	1132
1083	1133	pm_runtime_enable(&pdev->dev);
1084	1134	pm_runtime_resume(&pdev->dev);