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Commit 3c0553e7347a96519ea232a9235dfb0eb1c6d3ec

Authored by Jayachandran C
Committed by Ralf Baechle
1 parent 62b734d289
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

MIPS: Netlogic: Avoid using fixed PIC IRT index 

The index for a device interrupt in the PIC interrupt routing table
changes for different chips in the XLP family.  Avoid using the fixed
entries and derive the index value from the SoC device header.

Add workarounds for some devices which do not report the IRT index
correctly.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: http://patchwork.linux-mips.org/patch/5025/
Acked-by: John Crispin <blogic@openwrt.org>

Showing 2 changed files with 40 additions and 75 deletions Side-by-side Diff

arch/mips/include/asm/netlogic/xlp-hal/pic.h
Diff comments   View file @ 3c0553e
... ... @@ -191,59 +191,6 @@
191 191 #define PIC_IRT_PCIE_LINK_2_INDEX 80
192 192 #define PIC_IRT_PCIE_LINK_3_INDEX 81
193 193 #define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX)
194   -/* 78 to 81 */
195   -#define PIC_NUM_NA_IRTS 32
196   -/* 82 to 113 */
197   -#define PIC_IRT_NA_0_INDEX 82
198   -#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX)
199   -#define PIC_IRT_POE_INDEX 114
200   -
201   -#define PIC_NUM_USB_IRTS 6
202   -#define PIC_IRT_USB_0_INDEX 115
203   -#define PIC_IRT_EHCI_0_INDEX 115
204   -#define PIC_IRT_OHCI_0_INDEX 116
205   -#define PIC_IRT_OHCI_1_INDEX 117
206   -#define PIC_IRT_EHCI_1_INDEX 118
207   -#define PIC_IRT_OHCI_2_INDEX 119
208   -#define PIC_IRT_OHCI_3_INDEX 120
209   -#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX)
210   -/* 115 to 120 */
211   -#define PIC_IRT_GDX_INDEX 121
212   -#define PIC_IRT_SEC_INDEX 122
213   -#define PIC_IRT_RSA_INDEX 123
214   -
215   -#define PIC_NUM_COMP_IRTS 4
216   -#define PIC_IRT_COMP_0_INDEX 124
217   -#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX)
218   -/* 124 to 127 */
219   -#define PIC_IRT_GBU_INDEX 128
220   -#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */
221   -#define PIC_IRT_ICC_1_INDEX 130
222   -#define PIC_IRT_ICC_2_INDEX 131
223   -#define PIC_IRT_CAM_INDEX 132
224   -#define PIC_IRT_UART_0_INDEX 133
225   -#define PIC_IRT_UART_1_INDEX 134
226   -#define PIC_IRT_I2C_0_INDEX 135
227   -#define PIC_IRT_I2C_1_INDEX 136
228   -#define PIC_IRT_SYS_0_INDEX 137
229   -#define PIC_IRT_SYS_1_INDEX 138
230   -#define PIC_IRT_JTAG_INDEX 139
231   -#define PIC_IRT_PIC_INDEX 140
232   -#define PIC_IRT_NBU_INDEX 141
233   -#define PIC_IRT_TCU_INDEX 142
234   -#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */
235   -#define PIC_IRT_DMC_0_INDEX 144
236   -#define PIC_IRT_DMC_1_INDEX 145
237   -
238   -#define PIC_NUM_GPIO_IRTS 4
239   -#define PIC_IRT_GPIO_0_INDEX 146
240   -#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX)
241   -
242   -/* 146 to 149 */
243   -#define PIC_IRT_NOR_INDEX 150
244   -#define PIC_IRT_NAND_INDEX 151
245   -#define PIC_IRT_SPI_INDEX 152
246   -#define PIC_IRT_MMC_INDEX 153
247 194  
248 195 #define PIC_CLOCK_TIMER 7
249 196 #define PIC_IRQ_BASE 8
arch/mips/netlogic/xlp/nlm_hal.c
Diff comments   View file @ 3c0553e
... ... @@ -61,43 +61,61 @@
61 61  
62 62 int nlm_irq_to_irt(int irq)
63 63 {
64   - if (!PIC_IRQ_IS_IRT(irq))
65   - return -1;
  64 + uint64_t pcibase;
  65 + int devoff, irt;
66 66  
67 67 switch (irq) {
68 68 case PIC_UART_0_IRQ:
69   - return PIC_IRT_UART_0_INDEX;
  69 + devoff = XLP_IO_UART0_OFFSET(0);
  70 + break;
70 71 case PIC_UART_1_IRQ:
71   - return PIC_IRT_UART_1_INDEX;
72   - case PIC_PCIE_LINK_0_IRQ:
73   - return PIC_IRT_PCIE_LINK_0_INDEX;
74   - case PIC_PCIE_LINK_1_IRQ:
75   - return PIC_IRT_PCIE_LINK_1_INDEX;
76   - case PIC_PCIE_LINK_2_IRQ:
77   - return PIC_IRT_PCIE_LINK_2_INDEX;
78   - case PIC_PCIE_LINK_3_IRQ:
79   - return PIC_IRT_PCIE_LINK_3_INDEX;
  72 + devoff = XLP_IO_UART1_OFFSET(0);
  73 + break;
80 74 case PIC_EHCI_0_IRQ:
81   - return PIC_IRT_EHCI_0_INDEX;
  75 + devoff = XLP_IO_USB_EHCI0_OFFSET(0);
  76 + break;
82 77 case PIC_EHCI_1_IRQ:
83   - return PIC_IRT_EHCI_1_INDEX;
  78 + devoff = XLP_IO_USB_EHCI1_OFFSET(0);
  79 + break;
84 80 case PIC_OHCI_0_IRQ:
85   - return PIC_IRT_OHCI_0_INDEX;
  81 + devoff = XLP_IO_USB_OHCI0_OFFSET(0);
  82 + break;
86 83 case PIC_OHCI_1_IRQ:
87   - return PIC_IRT_OHCI_1_INDEX;
  84 + devoff = XLP_IO_USB_OHCI1_OFFSET(0);
  85 + break;
88 86 case PIC_OHCI_2_IRQ:
89   - return PIC_IRT_OHCI_2_INDEX;
  87 + devoff = XLP_IO_USB_OHCI2_OFFSET(0);
  88 + break;
90 89 case PIC_OHCI_3_IRQ:
91   - return PIC_IRT_OHCI_3_INDEX;
  90 + devoff = XLP_IO_USB_OHCI3_OFFSET(0);
  91 + break;
92 92 case PIC_MMC_IRQ:
93   - return PIC_IRT_MMC_INDEX;
  93 + devoff = XLP_IO_SD_OFFSET(0);
  94 + break;
94 95 case PIC_I2C_0_IRQ:
95   - return PIC_IRT_I2C_0_INDEX;
  96 + devoff = XLP_IO_I2C0_OFFSET(0);
  97 + break;
96 98 case PIC_I2C_1_IRQ:
97   - return PIC_IRT_I2C_1_INDEX;
  99 + devoff = XLP_IO_I2C1_OFFSET(0);
  100 + break;
98 101 default:
99   - return -1;
  102 + devoff = 0;
  103 + break;
100 104 }
  105 +
  106 + if (devoff != 0) {
  107 + pcibase = nlm_pcicfg_base(devoff);
  108 + irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
  109 + /* HW bug, I2C 1 irt entry is off by one */
  110 + if (irq == PIC_I2C_1_IRQ)
  111 + irt = irt + 1;
  112 + } else if (irq >= PIC_PCIE_LINK_0_IRQ && irq <= PIC_PCIE_LINK_3_IRQ) {
  113 + /* HW bug, PCI IRT entries are bad on early silicon, fix */
  114 + irt = PIC_IRT_PCIE_LINK_INDEX(irq - PIC_PCIE_LINK_0_IRQ);
  115 + } else {
  116 + irt = -1;
  117 + }
  118 + return irt;
101 119 }
102 120  
103 121 unsigned int nlm_get_core_frequency(int node, int core)