Commit 3cbaa0f7a78d3b970b566629ee298c310780b919
Exists in
master
and in
7 other branches
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: of/phylib: Use device tree properties to initialize Marvell PHYs. phylib: Add support for Marvell 88E1149R devices. phylib: Use common page register definition for Marvell PHYs. qlge: Fix incorrect usage of module parameters and netdev msg level ipv6: fix missing in6_ifa_put in addrconf SuperH IrDA: correct Baud rate error correction atl1c: Fix hardware type check for enabling OTP CLK net: allow GFP_HIGHMEM in __vmalloc() bonding: change list contact to netdev@vger.kernel.org e1000: fix screaming IRQ
Showing 12 changed files Side-by-side Diff
MAINTAINERS
drivers/net/atl1c/atl1c_hw.c
... | ... | @@ -82,7 +82,7 @@ |
82 | 82 | addr[0] = addr[1] = 0; |
83 | 83 | AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data); |
84 | 84 | if (atl1c_check_eeprom_exist(hw)) { |
85 | - if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c_b) { | |
85 | + if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) { | |
86 | 86 | /* Enable OTP CLK */ |
87 | 87 | if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) { |
88 | 88 | otp_ctrl_data |= OTP_CTRL_CLK_EN; |
drivers/net/e1000/e1000_main.c
... | ... | @@ -31,7 +31,7 @@ |
31 | 31 | |
32 | 32 | char e1000_driver_name[] = "e1000"; |
33 | 33 | static char e1000_driver_string[] = "Intel(R) PRO/1000 Network Driver"; |
34 | -#define DRV_VERSION "7.3.21-k6-NAPI" | |
34 | +#define DRV_VERSION "7.3.21-k8-NAPI" | |
35 | 35 | const char e1000_driver_version[] = DRV_VERSION; |
36 | 36 | static const char e1000_copyright[] = "Copyright (c) 1999-2006 Intel Corporation."; |
37 | 37 | |
... | ... | @@ -485,9 +485,6 @@ |
485 | 485 | struct net_device *netdev = adapter->netdev; |
486 | 486 | u32 rctl, tctl; |
487 | 487 | |
488 | - /* signal that we're down so the interrupt handler does not | |
489 | - * reschedule our watchdog timer */ | |
490 | - set_bit(__E1000_DOWN, &adapter->flags); | |
491 | 488 | |
492 | 489 | /* disable receives in the hardware */ |
493 | 490 | rctl = er32(RCTL); |
... | ... | @@ -507,6 +504,13 @@ |
507 | 504 | napi_disable(&adapter->napi); |
508 | 505 | |
509 | 506 | e1000_irq_disable(adapter); |
507 | + | |
508 | + /* | |
509 | + * Setting DOWN must be after irq_disable to prevent | |
510 | + * a screaming interrupt. Setting DOWN also prevents | |
511 | + * timers and tasks from rescheduling. | |
512 | + */ | |
513 | + set_bit(__E1000_DOWN, &adapter->flags); | |
510 | 514 | |
511 | 515 | del_timer_sync(&adapter->tx_fifo_stall_timer); |
512 | 516 | del_timer_sync(&adapter->watchdog_timer); |
drivers/net/irda/sh_sir.c
drivers/net/phy/marvell.c
... | ... | @@ -30,11 +30,14 @@ |
30 | 30 | #include <linux/ethtool.h> |
31 | 31 | #include <linux/phy.h> |
32 | 32 | #include <linux/marvell_phy.h> |
33 | +#include <linux/of.h> | |
33 | 34 | |
34 | 35 | #include <asm/io.h> |
35 | 36 | #include <asm/irq.h> |
36 | 37 | #include <asm/uaccess.h> |
37 | 38 | |
39 | +#define MII_MARVELL_PHY_PAGE 22 | |
40 | + | |
38 | 41 | #define MII_M1011_IEVENT 0x13 |
39 | 42 | #define MII_M1011_IEVENT_CLEAR 0x0000 |
40 | 43 | |
... | ... | @@ -80,7 +83,6 @@ |
80 | 83 | #define MII_88E1121_PHY_LED_CTRL 16 |
81 | 84 | #define MII_88E1121_PHY_LED_PAGE 3 |
82 | 85 | #define MII_88E1121_PHY_LED_DEF 0x0030 |
83 | -#define MII_88E1121_PHY_PAGE 22 | |
84 | 86 | |
85 | 87 | #define MII_M1011_PHY_STATUS 0x11 |
86 | 88 | #define MII_M1011_PHY_STATUS_1000 0x8000 |
87 | 89 | |
88 | 90 | |
... | ... | @@ -186,13 +188,94 @@ |
186 | 188 | return 0; |
187 | 189 | } |
188 | 190 | |
191 | +#ifdef CONFIG_OF_MDIO | |
192 | +/* | |
193 | + * Set and/or override some configuration registers based on the | |
194 | + * marvell,reg-init property stored in the of_node for the phydev. | |
195 | + * | |
196 | + * marvell,reg-init = <reg-page reg mask value>,...; | |
197 | + * | |
198 | + * There may be one or more sets of <reg-page reg mask value>: | |
199 | + * | |
200 | + * reg-page: which register bank to use. | |
201 | + * reg: the register. | |
202 | + * mask: if non-zero, ANDed with existing register value. | |
203 | + * value: ORed with the masked value and written to the regiser. | |
204 | + * | |
205 | + */ | |
206 | +static int marvell_of_reg_init(struct phy_device *phydev) | |
207 | +{ | |
208 | + const __be32 *paddr; | |
209 | + int len, i, saved_page, current_page, page_changed, ret; | |
210 | + | |
211 | + if (!phydev->dev.of_node) | |
212 | + return 0; | |
213 | + | |
214 | + paddr = of_get_property(phydev->dev.of_node, "marvell,reg-init", &len); | |
215 | + if (!paddr || len < (4 * sizeof(*paddr))) | |
216 | + return 0; | |
217 | + | |
218 | + saved_page = phy_read(phydev, MII_MARVELL_PHY_PAGE); | |
219 | + if (saved_page < 0) | |
220 | + return saved_page; | |
221 | + page_changed = 0; | |
222 | + current_page = saved_page; | |
223 | + | |
224 | + ret = 0; | |
225 | + len /= sizeof(*paddr); | |
226 | + for (i = 0; i < len - 3; i += 4) { | |
227 | + u16 reg_page = be32_to_cpup(paddr + i); | |
228 | + u16 reg = be32_to_cpup(paddr + i + 1); | |
229 | + u16 mask = be32_to_cpup(paddr + i + 2); | |
230 | + u16 val_bits = be32_to_cpup(paddr + i + 3); | |
231 | + int val; | |
232 | + | |
233 | + if (reg_page != current_page) { | |
234 | + current_page = reg_page; | |
235 | + page_changed = 1; | |
236 | + ret = phy_write(phydev, MII_MARVELL_PHY_PAGE, reg_page); | |
237 | + if (ret < 0) | |
238 | + goto err; | |
239 | + } | |
240 | + | |
241 | + val = 0; | |
242 | + if (mask) { | |
243 | + val = phy_read(phydev, reg); | |
244 | + if (val < 0) { | |
245 | + ret = val; | |
246 | + goto err; | |
247 | + } | |
248 | + val &= mask; | |
249 | + } | |
250 | + val |= val_bits; | |
251 | + | |
252 | + ret = phy_write(phydev, reg, val); | |
253 | + if (ret < 0) | |
254 | + goto err; | |
255 | + | |
256 | + } | |
257 | +err: | |
258 | + if (page_changed) { | |
259 | + i = phy_write(phydev, MII_MARVELL_PHY_PAGE, saved_page); | |
260 | + if (ret == 0) | |
261 | + ret = i; | |
262 | + } | |
263 | + return ret; | |
264 | +} | |
265 | +#else | |
266 | +static int marvell_of_reg_init(struct phy_device *phydev) | |
267 | +{ | |
268 | + return 0; | |
269 | +} | |
270 | +#endif /* CONFIG_OF_MDIO */ | |
271 | + | |
189 | 272 | static int m88e1121_config_aneg(struct phy_device *phydev) |
190 | 273 | { |
191 | 274 | int err, oldpage, mscr; |
192 | 275 | |
193 | - oldpage = phy_read(phydev, MII_88E1121_PHY_PAGE); | |
276 | + oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); | |
194 | 277 | |
195 | - err = phy_write(phydev, MII_88E1121_PHY_PAGE, | |
278 | + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
196 | 279 | MII_88E1121_PHY_MSCR_PAGE); |
197 | 280 | if (err < 0) |
198 | 281 | return err; |
... | ... | @@ -218,7 +301,7 @@ |
218 | 301 | return err; |
219 | 302 | } |
220 | 303 | |
221 | - phy_write(phydev, MII_88E1121_PHY_PAGE, oldpage); | |
304 | + phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); | |
222 | 305 | |
223 | 306 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); |
224 | 307 | if (err < 0) |
225 | 308 | |
226 | 309 | |
... | ... | @@ -229,11 +312,11 @@ |
229 | 312 | if (err < 0) |
230 | 313 | return err; |
231 | 314 | |
232 | - oldpage = phy_read(phydev, MII_88E1121_PHY_PAGE); | |
315 | + oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); | |
233 | 316 | |
234 | - phy_write(phydev, MII_88E1121_PHY_PAGE, MII_88E1121_PHY_LED_PAGE); | |
317 | + phy_write(phydev, MII_MARVELL_PHY_PAGE, MII_88E1121_PHY_LED_PAGE); | |
235 | 318 | phy_write(phydev, MII_88E1121_PHY_LED_CTRL, MII_88E1121_PHY_LED_DEF); |
236 | - phy_write(phydev, MII_88E1121_PHY_PAGE, oldpage); | |
319 | + phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); | |
237 | 320 | |
238 | 321 | err = genphy_config_aneg(phydev); |
239 | 322 | |
240 | 323 | |
... | ... | @@ -244,9 +327,9 @@ |
244 | 327 | { |
245 | 328 | int err, oldpage, mscr; |
246 | 329 | |
247 | - oldpage = phy_read(phydev, MII_88E1121_PHY_PAGE); | |
330 | + oldpage = phy_read(phydev, MII_MARVELL_PHY_PAGE); | |
248 | 331 | |
249 | - err = phy_write(phydev, MII_88E1121_PHY_PAGE, | |
332 | + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, | |
250 | 333 | MII_88E1121_PHY_MSCR_PAGE); |
251 | 334 | if (err < 0) |
252 | 335 | return err; |
... | ... | @@ -258,7 +341,7 @@ |
258 | 341 | if (err < 0) |
259 | 342 | return err; |
260 | 343 | |
261 | - err = phy_write(phydev, MII_88E1121_PHY_PAGE, oldpage); | |
344 | + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, oldpage); | |
262 | 345 | if (err < 0) |
263 | 346 | return err; |
264 | 347 | |
... | ... | @@ -368,6 +451,9 @@ |
368 | 451 | return err; |
369 | 452 | } |
370 | 453 | |
454 | + err = marvell_of_reg_init(phydev); | |
455 | + if (err < 0) | |
456 | + return err; | |
371 | 457 | |
372 | 458 | err = phy_write(phydev, MII_BMCR, BMCR_RESET); |
373 | 459 | if (err < 0) |
... | ... | @@ -398,7 +484,7 @@ |
398 | 484 | int err; |
399 | 485 | |
400 | 486 | /* Change address */ |
401 | - err = phy_write(phydev, 0x16, 0x0002); | |
487 | + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); | |
402 | 488 | if (err < 0) |
403 | 489 | return err; |
404 | 490 | |
... | ... | @@ -408,7 +494,7 @@ |
408 | 494 | return err; |
409 | 495 | |
410 | 496 | /* Change address */ |
411 | - err = phy_write(phydev, 0x16, 0x0003); | |
497 | + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0003); | |
412 | 498 | if (err < 0) |
413 | 499 | return err; |
414 | 500 | |
415 | 501 | |
... | ... | @@ -420,8 +506,12 @@ |
420 | 506 | if (err < 0) |
421 | 507 | return err; |
422 | 508 | |
509 | + err = marvell_of_reg_init(phydev); | |
510 | + if (err < 0) | |
511 | + return err; | |
512 | + | |
423 | 513 | /* Reset address */ |
424 | - err = phy_write(phydev, 0x16, 0x0); | |
514 | + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); | |
425 | 515 | if (err < 0) |
426 | 516 | return err; |
427 | 517 | |
... | ... | @@ -432,6 +522,36 @@ |
432 | 522 | return 0; |
433 | 523 | } |
434 | 524 | |
525 | +static int m88e1149_config_init(struct phy_device *phydev) | |
526 | +{ | |
527 | + int err; | |
528 | + | |
529 | + /* Change address */ | |
530 | + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0002); | |
531 | + if (err < 0) | |
532 | + return err; | |
533 | + | |
534 | + /* Enable 1000 Mbit */ | |
535 | + err = phy_write(phydev, 0x15, 0x1048); | |
536 | + if (err < 0) | |
537 | + return err; | |
538 | + | |
539 | + err = marvell_of_reg_init(phydev); | |
540 | + if (err < 0) | |
541 | + return err; | |
542 | + | |
543 | + /* Reset address */ | |
544 | + err = phy_write(phydev, MII_MARVELL_PHY_PAGE, 0x0); | |
545 | + if (err < 0) | |
546 | + return err; | |
547 | + | |
548 | + err = phy_write(phydev, MII_BMCR, BMCR_RESET); | |
549 | + if (err < 0) | |
550 | + return err; | |
551 | + | |
552 | + return 0; | |
553 | +} | |
554 | + | |
435 | 555 | static int m88e1145_config_init(struct phy_device *phydev) |
436 | 556 | { |
437 | 557 | int err; |
... | ... | @@ -491,6 +611,10 @@ |
491 | 611 | } |
492 | 612 | } |
493 | 613 | |
614 | + err = marvell_of_reg_init(phydev); | |
615 | + if (err < 0) | |
616 | + return err; | |
617 | + | |
494 | 618 | return 0; |
495 | 619 | } |
496 | 620 | |
... | ... | @@ -685,6 +809,19 @@ |
685 | 809 | .driver = { .owner = THIS_MODULE }, |
686 | 810 | }, |
687 | 811 | { |
812 | + .phy_id = MARVELL_PHY_ID_88E1149R, | |
813 | + .phy_id_mask = MARVELL_PHY_ID_MASK, | |
814 | + .name = "Marvell 88E1149R", | |
815 | + .features = PHY_GBIT_FEATURES, | |
816 | + .flags = PHY_HAS_INTERRUPT, | |
817 | + .config_init = &m88e1149_config_init, | |
818 | + .config_aneg = &m88e1118_config_aneg, | |
819 | + .read_status = &genphy_read_status, | |
820 | + .ack_interrupt = &marvell_ack_interrupt, | |
821 | + .config_intr = &marvell_config_intr, | |
822 | + .driver = { .owner = THIS_MODULE }, | |
823 | + }, | |
824 | + { | |
688 | 825 | .phy_id = MARVELL_PHY_ID_88E1240, |
689 | 826 | .phy_id_mask = MARVELL_PHY_ID_MASK, |
690 | 827 | .name = "Marvell 88E1240", |
... | ... | @@ -735,6 +872,7 @@ |
735 | 872 | { 0x01410e10, 0xfffffff0 }, |
736 | 873 | { 0x01410cb0, 0xfffffff0 }, |
737 | 874 | { 0x01410cd0, 0xfffffff0 }, |
875 | + { 0x01410e50, 0xfffffff0 }, | |
738 | 876 | { 0x01410e30, 0xfffffff0 }, |
739 | 877 | { 0x01410e90, 0xfffffff0 }, |
740 | 878 | { } |
drivers/net/qlge/qlge_main.c
... | ... | @@ -62,15 +62,15 @@ |
62 | 62 | /* NETIF_MSG_PKTDATA | */ |
63 | 63 | NETIF_MSG_HW | NETIF_MSG_WOL | 0; |
64 | 64 | |
65 | -static int debug = 0x00007fff; /* defaults above */ | |
66 | -module_param(debug, int, 0); | |
65 | +static int debug = -1; /* defaults above */ | |
66 | +module_param(debug, int, 0664); | |
67 | 67 | MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)"); |
68 | 68 | |
69 | 69 | #define MSIX_IRQ 0 |
70 | 70 | #define MSI_IRQ 1 |
71 | 71 | #define LEG_IRQ 2 |
72 | 72 | static int qlge_irq_type = MSIX_IRQ; |
73 | -module_param(qlge_irq_type, int, MSIX_IRQ); | |
73 | +module_param(qlge_irq_type, int, 0664); | |
74 | 74 | MODULE_PARM_DESC(qlge_irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy."); |
75 | 75 | |
76 | 76 | static int qlge_mpi_coredump; |
include/linux/marvell_phy.h
... | ... | @@ -11,6 +11,7 @@ |
11 | 11 | #define MARVELL_PHY_ID_88E1118 0x01410e10 |
12 | 12 | #define MARVELL_PHY_ID_88E1121R 0x01410cb0 |
13 | 13 | #define MARVELL_PHY_ID_88E1145 0x01410cd0 |
14 | +#define MARVELL_PHY_ID_88E1149R 0x01410e50 | |
14 | 15 | #define MARVELL_PHY_ID_88E1240 0x01410e30 |
15 | 16 | #define MARVELL_PHY_ID_88E1318S 0x01410e90 |
16 | 17 |
net/ceph/buffer.c
net/core/request_sock.c
... | ... | @@ -45,9 +45,7 @@ |
45 | 45 | nr_table_entries = roundup_pow_of_two(nr_table_entries + 1); |
46 | 46 | lopt_size += nr_table_entries * sizeof(struct request_sock *); |
47 | 47 | if (lopt_size > PAGE_SIZE) |
48 | - lopt = __vmalloc(lopt_size, | |
49 | - GFP_KERNEL | __GFP_HIGHMEM | __GFP_ZERO, | |
50 | - PAGE_KERNEL); | |
48 | + lopt = vzalloc(lopt_size); | |
51 | 49 | else |
52 | 50 | lopt = kzalloc(lopt_size, GFP_KERNEL); |
53 | 51 | if (lopt == NULL) |
net/ipv4/fib_trie.c
net/ipv6/addrconf.c
... | ... | @@ -2758,13 +2758,13 @@ |
2758 | 2758 | ifa->state = INET6_IFADDR_STATE_DEAD; |
2759 | 2759 | spin_unlock_bh(&ifa->state_lock); |
2760 | 2760 | |
2761 | - if (state == INET6_IFADDR_STATE_DEAD) { | |
2762 | - in6_ifa_put(ifa); | |
2763 | - } else { | |
2761 | + if (state != INET6_IFADDR_STATE_DEAD) { | |
2764 | 2762 | __ipv6_ifa_notify(RTM_DELADDR, ifa); |
2765 | 2763 | atomic_notifier_call_chain(&inet6addr_chain, |
2766 | 2764 | NETDEV_DOWN, ifa); |
2767 | 2765 | } |
2766 | + | |
2767 | + in6_ifa_put(ifa); | |
2768 | 2768 | write_lock_bh(&idev->lock); |
2769 | 2769 | } |
2770 | 2770 | } |
net/xfrm/xfrm_hash.c
... | ... | @@ -19,7 +19,7 @@ |
19 | 19 | if (sz <= PAGE_SIZE) |
20 | 20 | n = kzalloc(sz, GFP_KERNEL); |
21 | 21 | else if (hashdist) |
22 | - n = __vmalloc(sz, GFP_KERNEL | __GFP_ZERO, PAGE_KERNEL); | |
22 | + n = vzalloc(sz); | |
23 | 23 | else |
24 | 24 | n = (struct hlist_head *) |
25 | 25 | __get_free_pages(GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO, |