ixgbe: fix semaphore lock for I2C read/writes on 82598

ixgbe_read/write_i2c_phy_82598() does not hold the SWFW_SYNC semaphore for the entire function. Instead the lock is held only during the phy.ops.read/write_reg operations. As result when the function is being called simultaneously the I2C read/writes can be corrupted. The following patch introduces the SWFW_SYNC semaphore for the entire ixgbe_read/write_i2c_phy_82598() function. To accomplish this I had to create 2 separate functions: ixgbe_read_phy_reg_mdi() ixgbe_write_phy_reg_mdi() Those functions are identical to ixgbe_read/write_phy_reg_generic() sans the locking, and can be used in ixgbe_read/write_i2c_phy_82598() with the SWFW_SYNC semaphore being held. Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

ixgbe: fix semaphore lock for I2C read/writes on 82598
ixgbe_read/write_i2c_phy_82598() does not hold the SWFW_SYNC semaphore for the entire function. Instead the lock is held only during the phy.ops.read/write_reg operations. As result when the function is being called simultaneously the I2C read/writes can be corrupted. The following patch introduces the SWFW_SYNC semaphore for the entire ixgbe_read/write_i2c_phy_82598() function. To accomplish this I had to create 2 separate functions: ixgbe_read_phy_reg_mdi() ixgbe_write_phy_reg_mdi() Those functions are identical to ixgbe_read/write_phy_reg_generic() sans the locking, and can be used in ixgbe_read/write_i2c_phy_82598() with the SWFW_SYNC semaphore being held. Signed-off-by: Emil Tantilov <emil.s.tantilov@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Emil Tantilov · Jeff Kirsher
1 parent 93ac03be0d
Showing 4 changed files with 182 additions and 148 deletions Side-by-side Diff
drivers/net/ethernet/intel/ixgbe/ixgbe_82598.c
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.c
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
@@ -1018,8 +1018,17 @@
 	u16 sfp_addr = 0;
 	u16 sfp_data = 0;
 	u16 sfp_stat = 0;
+	u16 gssr;
 	u32 i;
  
+	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
+		gssr = IXGBE_GSSR_PHY1_SM;
+	else
+		gssr = IXGBE_GSSR_PHY0_SM;
+
+	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
+		return IXGBE_ERR_SWFW_SYNC;
+
 	if (hw->phy.type == ixgbe_phy_nl) {
 		/*
 		 * phy SDA/SCL registers are at addresses 0xC30A to
  
@@ -1028,17 +1037,17 @@
 		 */
 		sfp_addr = (dev_addr << 8) + byte_offset;
 		sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
-		hw->phy.ops.write_reg(hw,
-		                      IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
-		                      MDIO_MMD_PMAPMD,
-		                      sfp_addr);
+		hw->phy.ops.write_reg_mdi(hw,
+					  IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
+					  MDIO_MMD_PMAPMD,
+					  sfp_addr);
  
 		/* Poll status */
 		for (i = 0; i < 100; i++) {
-			hw->phy.ops.read_reg(hw,
-			                     IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
-			                     MDIO_MMD_PMAPMD,
-			                     &sfp_stat);
+			hw->phy.ops.read_reg_mdi(hw,
+						IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
+						MDIO_MMD_PMAPMD,
+						&sfp_stat);
 			sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
 			if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
 				break;
@@ -1052,8 +1061,8 @@
 		}
  
 		/* Read data */
-		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
-		                     MDIO_MMD_PMAPMD, &sfp_data);
+		hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
+					MDIO_MMD_PMAPMD, &sfp_data);
  
 		*eeprom_data = (u8)(sfp_data >> 8);
 	} else {
@@ -1061,6 +1070,7 @@
 	}
  
 out:
+	hw->mac.ops.release_swfw_sync(hw, gssr);
 	return status;
 }
  
@@ -1326,6 +1336,8 @@
 	.reset			= &ixgbe_reset_phy_generic,
 	.read_reg		= &ixgbe_read_phy_reg_generic,
 	.write_reg		= &ixgbe_write_phy_reg_generic,
+	.read_reg_mdi		= &ixgbe_read_phy_reg_mdi,
+	.write_reg_mdi		= &ixgbe_write_phy_reg_mdi,
 	.setup_link		= &ixgbe_setup_phy_link_generic,
 	.setup_link_speed	= &ixgbe_setup_phy_link_speed_generic,
 	.read_i2c_sff8472	= &ixgbe_read_i2c_sff8472_82598,
@@ -204,7 +204,83 @@
 }
  
 /**
+ *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
+ *  the SWFW lock
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit address of PHY register to read
+ *  @phy_data: Pointer to read data from PHY register
+ **/
+s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
+		       u16 *phy_data)
+{
+	u32 i, data, command;
+
+	/* Setup and write the address cycle command */
+	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
+		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
+
+	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
+
+	/* Check every 10 usec to see if the address cycle completed.
+	 * The MDI Command bit will clear when the operation is
+	 * complete
+	 */
+	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
+		udelay(10);
+
+		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
+				break;
+	}
+
+
+	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
+		hw_dbg(hw, "PHY address command did not complete.\n");
+		return IXGBE_ERR_PHY;
+	}
+
+	/* Address cycle complete, setup and write the read
+	 * command
+	 */
+	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
+		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+		   (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
+
+	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
+
+	/* Check every 10 usec to see if the address cycle
+	 * completed. The MDI Command bit will clear when the
+	 * operation is complete
+	 */
+	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
+		udelay(10);
+
+		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
+			break;
+	}
+
+	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
+		hw_dbg(hw, "PHY read command didn't complete\n");
+		return IXGBE_ERR_PHY;
+	}
+
+	/* Read operation is complete.  Get the data
+	 * from MSRWD
+	 */
+	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
+	data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
+	*phy_data = (u16)(data);
+
+	return 0;
+}
+
+/**
  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
+ *  using the SWFW lock - this function is needed in most cases
  *  @hw: pointer to hardware structure
  *  @reg_addr: 32 bit address of PHY register to read
  *  @phy_data: Pointer to read data from PHY register
@@ -212,10 +288,7 @@
 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                                u32 device_type, u16 *phy_data)
 {
-	u32 command;
-	u32 i;
-	u32 data;
-	s32 status = 0;
+	s32 status;
 	u16 gssr;
  
 	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
  
@@ -223,86 +296,93 @@
 	else
 		gssr = IXGBE_GSSR_PHY0_SM;
  
-	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
+	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
+		status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
+						phy_data);
+		hw->mac.ops.release_swfw_sync(hw, gssr);
+	} else {
 		status = IXGBE_ERR_SWFW_SYNC;
+	}
  
-	if (status == 0) {
-		/* Setup and write the address cycle command */
-		command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-		           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-		           (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
-		           (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
+	return status;
+}
  
-		IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
+/**
+ *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
+ *  without SWFW lock
+ *  @hw: pointer to hardware structure
+ *  @reg_addr: 32 bit PHY register to write
+ *  @device_type: 5 bit device type
+ *  @phy_data: Data to write to the PHY register
+ **/
+s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
+				u32 device_type, u16 phy_data)
+{
+	u32 i, command;
  
-		/*
-		 * Check every 10 usec to see if the address cycle completed.
-		 * The MDI Command bit will clear when the operation is
-		 * complete
-		 */
-		for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
-			udelay(10);
+	/* Put the data in the MDI single read and write data register*/
+	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
  
-			command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+	/* Setup and write the address cycle command */
+	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
+		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
  
-			if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
-				break;
-		}
+	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
  
-		if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
-			hw_dbg(hw, "PHY address command did not complete.\n");
-			status = IXGBE_ERR_PHY;
-		}
+	/*
+	 * Check every 10 usec to see if the address cycle completed.
+	 * The MDI Command bit will clear when the operation is
+	 * complete
+	 */
+	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
+		udelay(10);
  
-		if (status == 0) {
-			/*
-			 * Address cycle complete, setup and write the read
-			 * command
-			 */
-			command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-			           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-			           (hw->phy.mdio.prtad <<
-				    IXGBE_MSCA_PHY_ADDR_SHIFT) |
-			           (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
+		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
+			break;
+	}
  
-			IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
+	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
+		hw_dbg(hw, "PHY address cmd didn't complete\n");
+		return IXGBE_ERR_PHY;
+	}
  
-			/*
-			 * Check every 10 usec to see if the address cycle
-			 * completed. The MDI Command bit will clear when the
-			 * operation is complete
-			 */
-			for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
-				udelay(10);
+	/*
+	 * Address cycle complete, setup and write the write
+	 * command
+	 */
+	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
+		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
+		   (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
+		   (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
  
-				command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
  
-				if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
-					break;
-			}
+	/* Check every 10 usec to see if the address cycle
+	 * completed. The MDI Command bit will clear when the
+	 * operation is complete
+	 */
+	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
+		udelay(10);
  
-			if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
-				hw_dbg(hw, "PHY read command didn't complete\n");
-				status = IXGBE_ERR_PHY;
-			} else {
-				/*
-				 * Read operation is complete.  Get the data
-				 * from MSRWD
-				 */
-				data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
-				data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
-				*phy_data = (u16)(data);
-			}
-		}
+		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
+		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
+			break;
+	}
  
-		hw->mac.ops.release_swfw_sync(hw, gssr);
+	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
+		hw_dbg(hw, "PHY write cmd didn't complete\n");
+		return IXGBE_ERR_PHY;
 	}
  
-	return status;
+	return 0;
 }
  
 /**
  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
+ *  using SWFW lock- this function is needed in most cases
  *  @hw: pointer to hardware structure
  *  @reg_addr: 32 bit PHY register to write
  *  @device_type: 5 bit device type
@@ -311,9 +391,7 @@
 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                                 u32 device_type, u16 phy_data)
 {
-	u32 command;
-	u32 i;
-	s32 status = 0;
+	s32 status;
 	u16 gssr;
  
 	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
  
@@ -321,74 +399,12 @@
 	else
 		gssr = IXGBE_GSSR_PHY0_SM;
  
-	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
-		status = IXGBE_ERR_SWFW_SYNC;
-
-	if (status == 0) {
-		/* Put the data in the MDI single read and write data register*/
-		IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
-
-		/* Setup and write the address cycle command */
-		command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-		           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-		           (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) |
-		           (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
-
-		IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
-
-		/*
-		 * Check every 10 usec to see if the address cycle completed.
-		 * The MDI Command bit will clear when the operation is
-		 * complete
-		 */
-		for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
-			udelay(10);
-
-			command = IXGBE_READ_REG(hw, IXGBE_MSCA);
-
-			if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
-				break;
-		}
-
-		if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
-			hw_dbg(hw, "PHY address cmd didn't complete\n");
-			status = IXGBE_ERR_PHY;
-		}
-
-		if (status == 0) {
-			/*
-			 * Address cycle complete, setup and write the write
-			 * command
-			 */
-			command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
-			           (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
-			           (hw->phy.mdio.prtad <<
-				    IXGBE_MSCA_PHY_ADDR_SHIFT) |
-			           (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
-
-			IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
-
-			/*
-			 * Check every 10 usec to see if the address cycle
-			 * completed. The MDI Command bit will clear when the
-			 * operation is complete
-			 */
-			for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
-				udelay(10);
-
-				command = IXGBE_READ_REG(hw, IXGBE_MSCA);
-
-				if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
-					break;
-			}
-
-			if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
-				hw_dbg(hw, "PHY address cmd didn't complete\n");
-				status = IXGBE_ERR_PHY;
-			}
-		}
-
+	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
+		status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
+						 phy_data);
 		hw->mac.ops.release_swfw_sync(hw, gssr);
+	} else {
+		status = IXGBE_ERR_SWFW_SYNC;
 	}
  
 	return status;
@@ -107,6 +107,10 @@
                                u32 device_type, u16 *phy_data);
 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                                 u32 device_type, u16 phy_data);
+s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
+			   u32 device_type, u16 *phy_data);
+s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
+			    u32 device_type, u16 phy_data);
 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
                                        ixgbe_link_speed speed,
@@ -2886,6 +2886,8 @@
 	s32 (*reset)(struct ixgbe_hw *);
 	s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
 	s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
+	s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *);
+	s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16);
 	s32 (*setup_link)(struct ixgbe_hw *);
 	s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
 	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
...	...	@@ -1018,8 +1018,17 @@
1018	1018	u16 sfp_addr = 0;
1019	1019	u16 sfp_data = 0;
1020	1020	u16 sfp_stat = 0;
	1021	+ u16 gssr;
1021	1022	u32 i;
1022	1023
	1024	+ if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
	1025	+ gssr = IXGBE_GSSR_PHY1_SM;
	1026	+ else
	1027	+ gssr = IXGBE_GSSR_PHY0_SM;
	1028	+
	1029	+ if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
	1030	+ return IXGBE_ERR_SWFW_SYNC;
	1031	+
1023	1032	if (hw->phy.type == ixgbe_phy_nl) {
1024	1033	/*
1025	1034	* phy SDA/SCL registers are at addresses 0xC30A to
1026	1035
...	...	@@ -1028,17 +1037,17 @@
1028	1037	*/
1029	1038	sfp_addr = (dev_addr << 8) + byte_offset;
1030	1039	sfp_addr = (sfp_addr \| IXGBE_I2C_EEPROM_READ_MASK);
1031		- hw->phy.ops.write_reg(hw,
1032		- IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1033		- MDIO_MMD_PMAPMD,
1034		- sfp_addr);
	1040	+ hw->phy.ops.write_reg_mdi(hw,
	1041	+ IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
	1042	+ MDIO_MMD_PMAPMD,
	1043	+ sfp_addr);
1035	1044
1036	1045	/* Poll status */
1037	1046	for (i = 0; i < 100; i++) {
1038		- hw->phy.ops.read_reg(hw,
1039		- IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1040		- MDIO_MMD_PMAPMD,
1041		- &sfp_stat);
	1047	+ hw->phy.ops.read_reg_mdi(hw,
	1048	+ IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
	1049	+ MDIO_MMD_PMAPMD,
	1050	+ &sfp_stat);
1042	1051	sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1043	1052	if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1044	1053	break;
...	...	@@ -1052,8 +1061,8 @@
1052	1061	}
1053	1062
1054	1063	/* Read data */
1055		- hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1056		- MDIO_MMD_PMAPMD, &sfp_data);
	1064	+ hw->phy.ops.read_reg_mdi(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
	1065	+ MDIO_MMD_PMAPMD, &sfp_data);
1057	1066
1058	1067	*eeprom_data = (u8)(sfp_data >> 8);
1059	1068	} else {
...	...	@@ -1061,6 +1070,7 @@
1061	1070	}
1062	1071
1063	1072	out:
	1073	+ hw->mac.ops.release_swfw_sync(hw, gssr);
1064	1074	return status;
1065	1075	}
1066	1076
...	...	@@ -1326,6 +1336,8 @@
1326	1336	.reset = &ixgbe_reset_phy_generic,
1327	1337	.read_reg = &ixgbe_read_phy_reg_generic,
1328	1338	.write_reg = &ixgbe_write_phy_reg_generic,
	1339	+ .read_reg_mdi = &ixgbe_read_phy_reg_mdi,
	1340	+ .write_reg_mdi = &ixgbe_write_phy_reg_mdi,
1329	1341	.setup_link = &ixgbe_setup_phy_link_generic,
1330	1342	.setup_link_speed = &ixgbe_setup_phy_link_speed_generic,
1331	1343	.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_82598,
...	...	@@ -204,7 +204,83 @@
204	204	}
205	205
206	206	/**
	207	+ * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
	208	+ * the SWFW lock
	209	+ * @hw: pointer to hardware structure
	210	+ * @reg_addr: 32 bit address of PHY register to read
	211	+ * @phy_data: Pointer to read data from PHY register
	212	+ **/
	213	+s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
	214	+ u16 *phy_data)
	215	+{
	216	+ u32 i, data, command;
	217	+
	218	+ /* Setup and write the address cycle command */
	219	+ command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
	220	+ (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	221	+ (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	222	+ (IXGBE_MSCA_ADDR_CYCLE \| IXGBE_MSCA_MDI_COMMAND));
	223	+
	224	+ IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	225	+
	226	+ /* Check every 10 usec to see if the address cycle completed.
	227	+ * The MDI Command bit will clear when the operation is
	228	+ * complete
	229	+ */
	230	+ for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
	231	+ udelay(10);
	232	+
	233	+ command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	234	+ if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
	235	+ break;
	236	+ }
	237	+
	238	+
	239	+ if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
	240	+ hw_dbg(hw, "PHY address command did not complete.\n");
	241	+ return IXGBE_ERR_PHY;
	242	+ }
	243	+
	244	+ /* Address cycle complete, setup and write the read
	245	+ * command
	246	+ */
	247	+ command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
	248	+ (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	249	+ (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	250	+ (IXGBE_MSCA_READ \| IXGBE_MSCA_MDI_COMMAND));
	251	+
	252	+ IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	253	+
	254	+ /* Check every 10 usec to see if the address cycle
	255	+ * completed. The MDI Command bit will clear when the
	256	+ * operation is complete
	257	+ */
	258	+ for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
	259	+ udelay(10);
	260	+
	261	+ command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	262	+ if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
	263	+ break;
	264	+ }
	265	+
	266	+ if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
	267	+ hw_dbg(hw, "PHY read command didn't complete\n");
	268	+ return IXGBE_ERR_PHY;
	269	+ }
	270	+
	271	+ /* Read operation is complete. Get the data
	272	+ * from MSRWD
	273	+ */
	274	+ data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
	275	+ data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
	276	+ *phy_data = (u16)(data);
	277	+
	278	+ return 0;
	279	+}
	280	+
	281	+/**
207	282	* ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
	283	+ * using the SWFW lock - this function is needed in most cases
208	284	* @hw: pointer to hardware structure
209	285	* @reg_addr: 32 bit address of PHY register to read
210	286	* @phy_data: Pointer to read data from PHY register
...	...	@@ -212,10 +288,7 @@
212	288	s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
213	289	u32 device_type, u16 *phy_data)
214	290	{
215		- u32 command;
216		- u32 i;
217		- u32 data;
218		- s32 status = 0;
	291	+ s32 status;
219	292	u16 gssr;
220	293
221	294	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
222	295
223	296
224	297
225	298
226	299
227	300
228	301
229	302
230	303
231	304
232	305
233	306
234	307
235	308
236	309
237	310
...	...	@@ -223,86 +296,93 @@
223	296	else
224	297	gssr = IXGBE_GSSR_PHY0_SM;
225	298
226		- if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
	299	+ if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
	300	+ status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
	301	+ phy_data);
	302	+ hw->mac.ops.release_swfw_sync(hw, gssr);
	303	+ } else {
227	304	status = IXGBE_ERR_SWFW_SYNC;
	305	+ }
228	306
229		- if (status == 0) {
230		- /* Setup and write the address cycle command */
231		- command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
232		- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
233		- (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
234		- (IXGBE_MSCA_ADDR_CYCLE \| IXGBE_MSCA_MDI_COMMAND));
	307	+ return status;
	308	+}
235	309
236		- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	310	+/**
	311	+ * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
	312	+ * without SWFW lock
	313	+ * @hw: pointer to hardware structure
	314	+ * @reg_addr: 32 bit PHY register to write
	315	+ * @device_type: 5 bit device type
	316	+ * @phy_data: Data to write to the PHY register
	317	+ **/
	318	+s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
	319	+ u32 device_type, u16 phy_data)
	320	+{
	321	+ u32 i, command;
237	322
238		- /*
239		- * Check every 10 usec to see if the address cycle completed.
240		- * The MDI Command bit will clear when the operation is
241		- * complete
242		- */
243		- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
244		- udelay(10);
	323	+ /* Put the data in the MDI single read and write data register*/
	324	+ IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
245	325
246		- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	326	+ /* Setup and write the address cycle command */
	327	+ command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
	328	+ (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	329	+ (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	330	+ (IXGBE_MSCA_ADDR_CYCLE \| IXGBE_MSCA_MDI_COMMAND));
247	331
248		- if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
249		- break;
250		- }
	332	+ IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
251	333
252		- if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
253		- hw_dbg(hw, "PHY address command did not complete.\n");
254		- status = IXGBE_ERR_PHY;
255		- }
	334	+ /*
	335	+ * Check every 10 usec to see if the address cycle completed.
	336	+ * The MDI Command bit will clear when the operation is
	337	+ * complete
	338	+ */
	339	+ for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
	340	+ udelay(10);
256	341
257		- if (status == 0) {
258		- /*
259		- * Address cycle complete, setup and write the read
260		- * command
261		- */
262		- command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
263		- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
264		- (hw->phy.mdio.prtad <<
265		- IXGBE_MSCA_PHY_ADDR_SHIFT) \|
266		- (IXGBE_MSCA_READ \| IXGBE_MSCA_MDI_COMMAND));
	342	+ command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	343	+ if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
	344	+ break;
	345	+ }
267	346
268		- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
	347	+ if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
	348	+ hw_dbg(hw, "PHY address cmd didn't complete\n");
	349	+ return IXGBE_ERR_PHY;
	350	+ }
269	351
270		- /*
271		- * Check every 10 usec to see if the address cycle
272		- * completed. The MDI Command bit will clear when the
273		- * operation is complete
274		- */
275		- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
276		- udelay(10);
	352	+ /*
	353	+ * Address cycle complete, setup and write the write
	354	+ * command
	355	+ */
	356	+ command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
	357	+ (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
	358	+ (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
	359	+ (IXGBE_MSCA_WRITE \| IXGBE_MSCA_MDI_COMMAND));
277	360
278		- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	361	+ IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
279	362
280		- if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
281		- break;
282		- }
	363	+ /* Check every 10 usec to see if the address cycle
	364	+ * completed. The MDI Command bit will clear when the
	365	+ * operation is complete
	366	+ */
	367	+ for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
	368	+ udelay(10);
283	369
284		- if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
285		- hw_dbg(hw, "PHY read command didn't complete\n");
286		- status = IXGBE_ERR_PHY;
287		- } else {
288		- /*
289		- * Read operation is complete. Get the data
290		- * from MSRWD
291		- */
292		- data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
293		- data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
294		- *phy_data = (u16)(data);
295		- }
296		- }
	370	+ command = IXGBE_READ_REG(hw, IXGBE_MSCA);
	371	+ if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
	372	+ break;
	373	+ }
297	374
298		- hw->mac.ops.release_swfw_sync(hw, gssr);
	375	+ if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
	376	+ hw_dbg(hw, "PHY write cmd didn't complete\n");
	377	+ return IXGBE_ERR_PHY;
299	378	}
300	379
301		- return status;
	380	+ return 0;
302	381	}
303	382
304	383	/**
305	384	* ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
	385	+ * using SWFW lock- this function is needed in most cases
306	386	* @hw: pointer to hardware structure
307	387	* @reg_addr: 32 bit PHY register to write
308	388	* @device_type: 5 bit device type
...	...	@@ -311,9 +391,7 @@
311	391	s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
312	392	u32 device_type, u16 phy_data)
313	393	{
314		- u32 command;
315		- u32 i;
316		- s32 status = 0;
	394	+ s32 status;
317	395	u16 gssr;
318	396
319	397	if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
320	398
...	...	@@ -321,74 +399,12 @@
321	399	else
322	400	gssr = IXGBE_GSSR_PHY0_SM;
323	401
324		- if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0)
325		- status = IXGBE_ERR_SWFW_SYNC;
326		-
327		- if (status == 0) {
328		- /* Put the data in the MDI single read and write data register*/
329		- IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
330		-
331		- /* Setup and write the address cycle command */
332		- command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
333		- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
334		- (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) \|
335		- (IXGBE_MSCA_ADDR_CYCLE \| IXGBE_MSCA_MDI_COMMAND));
336		-
337		- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
338		-
339		- /*
340		- * Check every 10 usec to see if the address cycle completed.
341		- * The MDI Command bit will clear when the operation is
342		- * complete
343		- */
344		- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
345		- udelay(10);
346		-
347		- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
348		-
349		- if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
350		- break;
351		- }
352		-
353		- if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
354		- hw_dbg(hw, "PHY address cmd didn't complete\n");
355		- status = IXGBE_ERR_PHY;
356		- }
357		-
358		- if (status == 0) {
359		- /*
360		- * Address cycle complete, setup and write the write
361		- * command
362		- */
363		- command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) \|
364		- (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) \|
365		- (hw->phy.mdio.prtad <<
366		- IXGBE_MSCA_PHY_ADDR_SHIFT) \|
367		- (IXGBE_MSCA_WRITE \| IXGBE_MSCA_MDI_COMMAND));
368		-
369		- IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
370		-
371		- /*
372		- * Check every 10 usec to see if the address cycle
373		- * completed. The MDI Command bit will clear when the
374		- * operation is complete
375		- */
376		- for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
377		- udelay(10);
378		-
379		- command = IXGBE_READ_REG(hw, IXGBE_MSCA);
380		-
381		- if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
382		- break;
383		- }
384		-
385		- if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
386		- hw_dbg(hw, "PHY address cmd didn't complete\n");
387		- status = IXGBE_ERR_PHY;
388		- }
389		- }
390		-
	402	+ if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == 0) {
	403	+ status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
	404	+ phy_data);
391	405	hw->mac.ops.release_swfw_sync(hw, gssr);
	406	+ } else {
	407	+ status = IXGBE_ERR_SWFW_SYNC;
392	408	}
393	409
394	410	return status;
...	...	@@ -107,6 +107,10 @@
107	107	u32 device_type, u16 *phy_data);
108	108	s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
109	109	u32 device_type, u16 phy_data);
	110	+s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
	111	+ u32 device_type, u16 *phy_data);
	112	+s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
	113	+ u32 device_type, u16 phy_data);
110	114	s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
111	115	s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
112	116	ixgbe_link_speed speed,
...	...	@@ -2886,6 +2886,8 @@
2886	2886	s32 (reset)(struct ixgbe_hw );
2887	2887	s32 (read_reg)(struct ixgbe_hw , u32, u32, u16 *);
2888	2888	s32 (write_reg)(struct ixgbe_hw , u32, u32, u16);
	2889	+ s32 (read_reg_mdi)(struct ixgbe_hw , u32, u32, u16 *);
	2890	+ s32 (write_reg_mdi)(struct ixgbe_hw , u32, u32, u16);
2889	2891	s32 (setup_link)(struct ixgbe_hw );
2890	2892	s32 (setup_link_speed)(struct ixgbe_hw , ixgbe_link_speed, bool);
2891	2893	s32 (check_link)(struct ixgbe_hw , ixgbe_link_speed , bool );