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Commit 40c0764b18342f2e99e92779330cb4612a971420

Authored by Peter Ujfalusi
Committed by Liam Girdwood
1 parent 73c9522e76
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

ARM: OMAP2+: McBSP: Correct CLKR/FSR clock source mux configuration 

On OMAP2/3 McBSP1 port has 6 pin setup, while on OMAP4 the port is McBSP4.
Implement the CLKR/FSR clock mux selection for OMAP4, and make sure that
we add the correct callback for the correct port across supported OMAP
versions.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Jarkko Nikula <jarkko.nikula@bitmer.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Liam Girdwood <lrg@ti.com>

Showing 1 changed file with 44 additions and 2 deletions Inline Diff

arch/arm/mach-omap2/mcbsp.c
Diff comments   View file @ 40c0764
1 /* 1 /*
2 * linux/arch/arm/mach-omap2/mcbsp.c 2 * linux/arch/arm/mach-omap2/mcbsp.c
3 * 3 *
4 * Copyright (C) 2008 Instituto Nokia de Tecnologia 4 * Copyright (C) 2008 Instituto Nokia de Tecnologia
5 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br> 5 * Contact: Eduardo Valentin <eduardo.valentin@indt.org.br>
6 * 6 *
7 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 * 10 *
11 * Multichannel mode not supported. 11 * Multichannel mode not supported.
12 */ 12 */
13 #include <linux/module.h> 13 #include <linux/module.h>
14 #include <linux/init.h> 14 #include <linux/init.h>
15 #include <linux/clk.h> 15 #include <linux/clk.h>
16 #include <linux/err.h> 16 #include <linux/err.h>
17 #include <linux/io.h> 17 #include <linux/io.h>
18 #include <linux/platform_device.h> 18 #include <linux/platform_device.h>
19 #include <linux/slab.h> 19 #include <linux/slab.h>
20 20
21 #include <mach/irqs.h> 21 #include <mach/irqs.h>
22 #include <plat/dma.h> 22 #include <plat/dma.h>
23 #include <plat/cpu.h> 23 #include <plat/cpu.h>
24 #include <plat/mcbsp.h> 24 #include <plat/mcbsp.h>
25 #include <plat/omap_device.h> 25 #include <plat/omap_device.h>
26 #include <linux/pm_runtime.h> 26 #include <linux/pm_runtime.h>
27 27
28 #include "control.h" 28 #include "control.h"
29 29
30 /* 30 /*
31 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle. 31 * FIXME: Find a mechanism to enable/disable runtime the McBSP ICLK autoidle.
32 * Sidetone needs non-gated ICLK and sidetone autoidle is broken. 32 * Sidetone needs non-gated ICLK and sidetone autoidle is broken.
33 */ 33 */
34 #include "cm2xxx_3xxx.h" 34 #include "cm2xxx_3xxx.h"
35 #include "cm-regbits-34xx.h" 35 #include "cm-regbits-34xx.h"
36 36
37 /* McBSP internal signal muxing function */ 37 /* McBSP1 internal signal muxing function for OMAP2/3 */
38 static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal, 38 static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal,
39 const char *src) 39 const char *src)
40 { 40 {
41 u32 v; 41 u32 v;
42 42
43 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0); 43 v = omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0);
44 44
45 if (!strcmp(signal, "clkr")) { 45 if (!strcmp(signal, "clkr")) {
46 if (!strcmp(src, "clkr")) 46 if (!strcmp(src, "clkr"))
47 v &= ~OMAP2_MCBSP1_CLKR_MASK; 47 v &= ~OMAP2_MCBSP1_CLKR_MASK;
48 else if (!strcmp(src, "clkx")) 48 else if (!strcmp(src, "clkx"))
49 v |= OMAP2_MCBSP1_CLKR_MASK; 49 v |= OMAP2_MCBSP1_CLKR_MASK;
50 else 50 else
51 return -EINVAL; 51 return -EINVAL;
52 } else if (!strcmp(signal, "fsr")) { 52 } else if (!strcmp(signal, "fsr")) {
53 if (!strcmp(src, "fsr")) 53 if (!strcmp(src, "fsr"))
54 v &= ~OMAP2_MCBSP1_FSR_MASK; 54 v &= ~OMAP2_MCBSP1_FSR_MASK;
55 else if (!strcmp(src, "fsx")) 55 else if (!strcmp(src, "fsx"))
56 v |= OMAP2_MCBSP1_FSR_MASK; 56 v |= OMAP2_MCBSP1_FSR_MASK;
57 else 57 else
58 return -EINVAL; 58 return -EINVAL;
59 } else { 59 } else {
60 return -EINVAL; 60 return -EINVAL;
61 } 61 }
62 62
63 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0); 63 omap_ctrl_writel(v, OMAP2_CONTROL_DEVCONF0);
64 64
65 return 0; 65 return 0;
66 } 66 }
67 67
68 /* McBSP4 internal signal muxing function for OMAP4 */
69 #define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31)
70 #define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30)
71 static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal,
72 const char *src)
73 {
74 u32 v;
75
76 /*
77 * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR
78 * mux) is used */
79 v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
80
81 if (!strcmp(signal, "clkr")) {
82 if (!strcmp(src, "clkr"))
83 v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
84 else if (!strcmp(src, "clkx"))
85 v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX;
86 else
87 return -EINVAL;
88 } else if (!strcmp(signal, "fsr")) {
89 if (!strcmp(src, "fsr"))
90 v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
91 else if (!strcmp(src, "fsx"))
92 v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX;
93 else
94 return -EINVAL;
95 } else {
96 return -EINVAL;
97 }
98
99 omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP);
100
101 return 0;
102 }
103
68 /* McBSP CLKS source switching function */ 104 /* McBSP CLKS source switching function */
69 static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk, 105 static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk,
70 const char *src) 106 const char *src)
71 { 107 {
72 struct clk *fck_src; 108 struct clk *fck_src;
73 char *fck_src_name; 109 char *fck_src_name;
74 int r; 110 int r;
75 111
76 if (!strcmp(src, "clks_ext")) 112 if (!strcmp(src, "clks_ext"))
77 fck_src_name = "pad_fck"; 113 fck_src_name = "pad_fck";
78 else if (!strcmp(src, "clks_fclk")) 114 else if (!strcmp(src, "clks_fclk"))
79 fck_src_name = "prcm_fck"; 115 fck_src_name = "prcm_fck";
80 else 116 else
81 return -EINVAL; 117 return -EINVAL;
82 118
83 fck_src = clk_get(dev, fck_src_name); 119 fck_src = clk_get(dev, fck_src_name);
84 if (IS_ERR_OR_NULL(fck_src)) { 120 if (IS_ERR_OR_NULL(fck_src)) {
85 pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks", 121 pr_err("omap-mcbsp: %s: could not clk_get() %s\n", "clks",
86 fck_src_name); 122 fck_src_name);
87 return -EINVAL; 123 return -EINVAL;
88 } 124 }
89 125
90 pm_runtime_put_sync(dev); 126 pm_runtime_put_sync(dev);
91 127
92 r = clk_set_parent(clk, fck_src); 128 r = clk_set_parent(clk, fck_src);
93 if (IS_ERR_VALUE(r)) { 129 if (IS_ERR_VALUE(r)) {
94 pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n", 130 pr_err("omap-mcbsp: %s: could not clk_set_parent() to %s\n",
95 "clks", fck_src_name); 131 "clks", fck_src_name);
96 clk_put(fck_src); 132 clk_put(fck_src);
97 return -EINVAL; 133 return -EINVAL;
98 } 134 }
99 135
100 pm_runtime_get_sync(dev); 136 pm_runtime_get_sync(dev);
101 137
102 clk_put(fck_src); 138 clk_put(fck_src);
103 139
104 return 0; 140 return 0;
105 } 141 }
106 142
107 static int omap3_enable_st_clock(unsigned int id, bool enable) 143 static int omap3_enable_st_clock(unsigned int id, bool enable)
108 { 144 {
109 unsigned int w; 145 unsigned int w;
110 146
111 /* 147 /*
112 * Sidetone uses McBSP ICLK - which must not idle when sidetones 148 * Sidetone uses McBSP ICLK - which must not idle when sidetones
113 * are enabled or sidetones start sounding ugly. 149 * are enabled or sidetones start sounding ugly.
114 */ 150 */
115 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); 151 w = omap2_cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE);
116 if (enable) 152 if (enable)
117 w &= ~(1 << (id - 2)); 153 w &= ~(1 << (id - 2));
118 else 154 else
119 w |= 1 << (id - 2); 155 w |= 1 << (id - 2);
120 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE); 156 omap2_cm_write_mod_reg(w, OMAP3430_PER_MOD, CM_AUTOIDLE);
121 157
122 return 0; 158 return 0;
123 } 159 }
124 160
125 static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused) 161 static int omap_init_mcbsp(struct omap_hwmod *oh, void *unused)
126 { 162 {
127 int id, count = 1; 163 int id, count = 1;
128 char *name = "omap-mcbsp"; 164 char *name = "omap-mcbsp";
129 struct omap_hwmod *oh_device[2]; 165 struct omap_hwmod *oh_device[2];
130 struct omap_mcbsp_platform_data *pdata = NULL; 166 struct omap_mcbsp_platform_data *pdata = NULL;
131 struct platform_device *pdev; 167 struct platform_device *pdev;
132 168
133 sscanf(oh->name, "mcbsp%d", &id); 169 sscanf(oh->name, "mcbsp%d", &id);
134 170
135 pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL); 171 pdata = kzalloc(sizeof(struct omap_mcbsp_platform_data), GFP_KERNEL);
136 if (!pdata) { 172 if (!pdata) {
137 pr_err("%s: No memory for mcbsp\n", __func__); 173 pr_err("%s: No memory for mcbsp\n", __func__);
138 return -ENOMEM; 174 return -ENOMEM;
139 } 175 }
140 176
141 pdata->reg_step = 4; 177 pdata->reg_step = 4;
142 if (oh->class->rev < MCBSP_CONFIG_TYPE2) { 178 if (oh->class->rev < MCBSP_CONFIG_TYPE2) {
143 pdata->reg_size = 2; 179 pdata->reg_size = 2;
144 } else { 180 } else {
145 pdata->reg_size = 4; 181 pdata->reg_size = 4;
146 pdata->has_ccr = true; 182 pdata->has_ccr = true;
147 } 183 }
148 pdata->set_clk_src = omap2_mcbsp_set_clk_src; 184 pdata->set_clk_src = omap2_mcbsp_set_clk_src;
149 if (id == 1) 185
186 /* On OMAP2/3 the McBSP1 port has 6 pin configuration */
187 if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4)
150 pdata->mux_signal = omap2_mcbsp1_mux_rx_clk; 188 pdata->mux_signal = omap2_mcbsp1_mux_rx_clk;
189
190 /* On OMAP4 the McBSP4 port has 6 pin configuration */
191 if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4)
192 pdata->mux_signal = omap4_mcbsp4_mux_rx_clk;
151 193
152 if (oh->class->rev == MCBSP_CONFIG_TYPE3) { 194 if (oh->class->rev == MCBSP_CONFIG_TYPE3) {
153 if (id == 2) 195 if (id == 2)
154 /* The FIFO has 1024 + 256 locations */ 196 /* The FIFO has 1024 + 256 locations */
155 pdata->buffer_size = 0x500; 197 pdata->buffer_size = 0x500;
156 else 198 else
157 /* The FIFO has 128 locations */ 199 /* The FIFO has 128 locations */
158 pdata->buffer_size = 0x80; 200 pdata->buffer_size = 0x80;
159 } else if (oh->class->rev == MCBSP_CONFIG_TYPE4) { 201 } else if (oh->class->rev == MCBSP_CONFIG_TYPE4) {
160 /* The FIFO has 128 locations for all instances */ 202 /* The FIFO has 128 locations for all instances */
161 pdata->buffer_size = 0x80; 203 pdata->buffer_size = 0x80;
162 } 204 }
163 205
164 if (oh->class->rev >= MCBSP_CONFIG_TYPE3) 206 if (oh->class->rev >= MCBSP_CONFIG_TYPE3)
165 pdata->has_wakeup = true; 207 pdata->has_wakeup = true;
166 208
167 oh_device[0] = oh; 209 oh_device[0] = oh;
168 210
169 if (oh->dev_attr) { 211 if (oh->dev_attr) {
170 oh_device[1] = omap_hwmod_lookup(( 212 oh_device[1] = omap_hwmod_lookup((
171 (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone); 213 (struct omap_mcbsp_dev_attr *)(oh->dev_attr))->sidetone);
172 pdata->enable_st_clock = omap3_enable_st_clock; 214 pdata->enable_st_clock = omap3_enable_st_clock;
173 count++; 215 count++;
174 } 216 }
175 pdev = omap_device_build_ss(name, id, oh_device, count, pdata, 217 pdev = omap_device_build_ss(name, id, oh_device, count, pdata,
176 sizeof(*pdata), NULL, 0, false); 218 sizeof(*pdata), NULL, 0, false);
177 kfree(pdata); 219 kfree(pdata);
178 if (IS_ERR(pdev)) { 220 if (IS_ERR(pdev)) {
179 pr_err("%s: Can't build omap_device for %s:%s.\n", __func__, 221 pr_err("%s: Can't build omap_device for %s:%s.\n", __func__,
180 name, oh->name); 222 name, oh->name);
181 return PTR_ERR(pdev); 223 return PTR_ERR(pdev);
182 } 224 }
183 return 0; 225 return 0;
184 } 226 }
185 227
186 static int __init omap2_mcbsp_init(void) 228 static int __init omap2_mcbsp_init(void)
187 { 229 {
188 omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL); 230 omap_hwmod_for_each_by_class("mcbsp", omap_init_mcbsp, NULL);
189 231
190 return 0; 232 return 0;
191 } 233 }
192 arch_initcall(omap2_mcbsp_init); 234 arch_initcall(omap2_mcbsp_init);
193 235