Commit 40c0764b18342f2e99e92779330cb4612a971420
Committed by
Liam Girdwood
Liam Girdwood
1 parent
73c9522e76
Exists in
smarc-l5.0.0_1.0.0-ga
and in
5 other branches
ARM: OMAP2+: McBSP: Correct CLKR/FSR clock source mux configuration
On OMAP2/3 McBSP1 port has 6 pin setup, while on OMAP4 the port is McBSP4. Implement the CLKR/FSR clock mux selection for OMAP4, and make sure that we add the correct callback for the correct port across supported OMAP versions. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Acked-by: Jarkko Nikula <jarkko.nikula@bitmer.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Liam Girdwood <lrg@ti.com>
Showing 1 changed file with 44 additions and 2 deletions Side-by-side Diff
arch/arm/mach-omap2/mcbsp.c
| ... | ... | @@ -34,7 +34,7 @@ |
| 34 | 34 | #include "cm2xxx_3xxx.h" |
| 35 | 35 | #include "cm-regbits-34xx.h" |
| 36 | 36 | |
| 37 | -/* McBSP internal signal muxing function */ | |
| 37 | +/* McBSP1 internal signal muxing function for OMAP2/3 */ | |
| 38 | 38 | static int omap2_mcbsp1_mux_rx_clk(struct device *dev, const char *signal, |
| 39 | 39 | const char *src) |
| 40 | 40 | { |
| ... | ... | @@ -65,6 +65,42 @@ |
| 65 | 65 | return 0; |
| 66 | 66 | } |
| 67 | 67 | |
| 68 | +/* McBSP4 internal signal muxing function for OMAP4 */ | |
| 69 | +#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX (1 << 31) | |
| 70 | +#define OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX (1 << 30) | |
| 71 | +static int omap4_mcbsp4_mux_rx_clk(struct device *dev, const char *signal, | |
| 72 | + const char *src) | |
| 73 | +{ | |
| 74 | + u32 v; | |
| 75 | + | |
| 76 | + /* | |
| 77 | + * In CONTROL_MCBSPLP register only bit 30 (CLKR mux), and bit 31 (FSR | |
| 78 | + * mux) is used */ | |
| 79 | + v = omap4_ctrl_pad_readl(OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP); | |
| 80 | + | |
| 81 | + if (!strcmp(signal, "clkr")) { | |
| 82 | + if (!strcmp(src, "clkr")) | |
| 83 | + v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX; | |
| 84 | + else if (!strcmp(src, "clkx")) | |
| 85 | + v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_CLKX; | |
| 86 | + else | |
| 87 | + return -EINVAL; | |
| 88 | + } else if (!strcmp(signal, "fsr")) { | |
| 89 | + if (!strcmp(src, "fsr")) | |
| 90 | + v &= ~OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX; | |
| 91 | + else if (!strcmp(src, "fsx")) | |
| 92 | + v |= OMAP4_CONTROL_MCBSPLP_ALBCTRLRX_FSX; | |
| 93 | + else | |
| 94 | + return -EINVAL; | |
| 95 | + } else { | |
| 96 | + return -EINVAL; | |
| 97 | + } | |
| 98 | + | |
| 99 | + omap4_ctrl_pad_writel(v, OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP); | |
| 100 | + | |
| 101 | + return 0; | |
| 102 | +} | |
| 103 | + | |
| 68 | 104 | /* McBSP CLKS source switching function */ |
| 69 | 105 | static int omap2_mcbsp_set_clk_src(struct device *dev, struct clk *clk, |
| 70 | 106 | const char *src) |
| 71 | 107 | |
| ... | ... | @@ -146,8 +182,14 @@ |
| 146 | 182 | pdata->has_ccr = true; |
| 147 | 183 | } |
| 148 | 184 | pdata->set_clk_src = omap2_mcbsp_set_clk_src; |
| 149 | - if (id == 1) | |
| 185 | + | |
| 186 | + /* On OMAP2/3 the McBSP1 port has 6 pin configuration */ | |
| 187 | + if (id == 1 && oh->class->rev < MCBSP_CONFIG_TYPE4) | |
| 150 | 188 | pdata->mux_signal = omap2_mcbsp1_mux_rx_clk; |
| 189 | + | |
| 190 | + /* On OMAP4 the McBSP4 port has 6 pin configuration */ | |
| 191 | + if (id == 4 && oh->class->rev == MCBSP_CONFIG_TYPE4) | |
| 192 | + pdata->mux_signal = omap4_mcbsp4_mux_rx_clk; | |
| 151 | 193 | |
| 152 | 194 | if (oh->class->rev == MCBSP_CONFIG_TYPE3) { |
| 153 | 195 | if (id == 2) |