Commit 41babf753cc82ab6208903625a084bf305c32d06

Authored by Jaehoon Chung
Committed by Chris Ball
1 parent e7054ba1f7

mmc: dw_mmc: support DDR mode

This patch adds DDR mode support to dw_mmc.

If we set any bit in UHS_REG bit[16:31], the card of that slot is
supported for DDR mode.  For example, if UHS_REG[16] is set, card
number 0 is DDR mode.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Will Newton <will.newton@imgtec.com>
Signed-off-by: Chris Ball <cjb@laptop.org>

Showing 2 changed files with 9 additions and 1 deletions Side-by-side Diff

drivers/mmc/host/dw_mmc.c
... ... @@ -662,6 +662,7 @@
662 662 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
663 663 {
664 664 struct dw_mci_slot *slot = mmc_priv(mmc);
  665 + u32 regs;
665 666  
666 667 /* set default 1 bit mode */
667 668 slot->ctype = SDMMC_CTYPE_1BIT;
... ... @@ -676,6 +677,13 @@
676 677 case MMC_BUS_WIDTH_8:
677 678 slot->ctype = SDMMC_CTYPE_8BIT;
678 679 break;
  680 + }
  681 +
  682 + /* DDR mode set */
  683 + if (ios->ddr) {
  684 + regs = mci_readl(slot->host, UHS_REG);
  685 + regs |= (0x1 << slot->id) << 16;
  686 + mci_writel(slot->host, UHS_REG, regs);
679 687 }
680 688  
681 689 if (ios->clock) {
drivers/mmc/host/dw_mmc.h
... ... @@ -43,6 +43,7 @@
43 43 #define SDMMC_USRID 0x068
44 44 #define SDMMC_VERID 0x06c
45 45 #define SDMMC_HCON 0x070
  46 +#define SDMMC_UHS_REG 0x074
46 47 #define SDMMC_BMOD 0x080
47 48 #define SDMMC_PLDMND 0x084
48 49 #define SDMMC_DBADDR 0x088
... ... @@ -51,7 +52,6 @@
51 52 #define SDMMC_DSCADDR 0x094
52 53 #define SDMMC_BUFADDR 0x098
53 54 #define SDMMC_DATA 0x100
54   -#define SDMMC_DATA_ADR 0x100
55 55  
56 56 /* shift bit field */
57 57 #define _SBF(f, v) ((v) << (f))