Commit 438a76167959061e371025f727fabec2ad9e70a7
Committed by
Russell King
1 parent
b3402cf50e
Exists in
master
and in
7 other branches
[PATCH] ARM: Fix VFP to use do_div()
VFP used __divdi3 64-bit division needlessly. Convert it to use our 64-bit by 32-bit division instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Showing 3 changed files with 27 additions and 4 deletions Side-by-side Diff
arch/arm/vfp/vfp.h
... | ... | @@ -117,7 +117,13 @@ |
117 | 117 | if (nh >= m) |
118 | 118 | return ~0ULL; |
119 | 119 | mh = m >> 32; |
120 | - z = (mh << 32 <= nh) ? 0xffffffff00000000ULL : (nh / mh) << 32; | |
120 | + if (mh << 32 <= nh) { | |
121 | + z = 0xffffffff00000000ULL; | |
122 | + } else { | |
123 | + z = nh; | |
124 | + do_div(z, mh); | |
125 | + z <<= 32; | |
126 | + } | |
121 | 127 | mul64to128(&termh, &terml, m, z); |
122 | 128 | sub128(&remh, &reml, nh, nl, termh, terml); |
123 | 129 | ml = m << 32; |
... | ... | @@ -126,7 +132,12 @@ |
126 | 132 | add128(&remh, &reml, remh, reml, mh, ml); |
127 | 133 | } |
128 | 134 | remh = (remh << 32) | (reml >> 32); |
129 | - z |= (mh << 32 <= remh) ? 0xffffffff : remh / mh; | |
135 | + if (mh << 32 <= remh) { | |
136 | + z |= 0xffffffff; | |
137 | + } else { | |
138 | + do_div(remh, mh); | |
139 | + z |= remh; | |
140 | + } | |
130 | 141 | return z; |
131 | 142 | } |
132 | 143 |
arch/arm/vfp/vfpdouble.c
arch/arm/vfp/vfpsingle.c
... | ... | @@ -32,6 +32,8 @@ |
32 | 32 | */ |
33 | 33 | #include <linux/kernel.h> |
34 | 34 | #include <linux/bitops.h> |
35 | + | |
36 | +#include <asm/div64.h> | |
35 | 37 | #include <asm/ptrace.h> |
36 | 38 | #include <asm/vfp.h> |
37 | 39 | |
... | ... | @@ -303,7 +305,11 @@ |
303 | 305 | if (z <= a) |
304 | 306 | return (s32)a >> 1; |
305 | 307 | } |
306 | - return (u32)(((u64)a << 31) / z) + (z >> 1); | |
308 | + { | |
309 | + u64 v = (u64)a << 31; | |
310 | + do_div(v, z); | |
311 | + return v + (z >> 1); | |
312 | + } | |
307 | 313 | } |
308 | 314 | |
309 | 315 | static u32 vfp_single_fsqrt(int sd, int unused, s32 m, u32 fpscr) |
... | ... | @@ -1107,7 +1113,11 @@ |
1107 | 1113 | vsn.significand >>= 1; |
1108 | 1114 | vsd.exponent++; |
1109 | 1115 | } |
1110 | - vsd.significand = ((u64)vsn.significand << 32) / vsm.significand; | |
1116 | + { | |
1117 | + u64 significand = (u64)vsn.significand << 32; | |
1118 | + do_div(significand, vsm.significand); | |
1119 | + vsd.significand = significand; | |
1120 | + } | |
1111 | 1121 | if ((vsd.significand & 0x3f) == 0) |
1112 | 1122 | vsd.significand |= ((u64)vsm.significand * vsd.significand != (u64)vsn.significand << 32); |
1113 | 1123 |