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Commit 4457af67337112733b65a66c3d56ca5518e1adbb

Authored by Manuel Lauss
Committed by Ralf Baechle
1 parent 8e0d7372f5
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

MIPS: perf: Fix build failure in XLP perf support. 

Commit 4be3d2f3966b9f010bb997dcab25e7af489a841e ("MIPS: perf: Add XLP
support for hardware perf.") added UNSUPPORTED_PERF_EVENT_ID which was
removed a while back.

Cc: Zi Shen Lim <zlim@netlogicmicro.com>
Cc: Jayachandran C <jchandra@broadcom.com>
Cc: Linux-MIPS <linux-mips@linux-mips.org>
Cc: John Crispin <blogic@openwrt.org>
Cc: Zi Shen Lim <zlim@netlogicmicro.com>
Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com>
Acked-by: Jayachandran C <jchandra@broadcom.com>
Patchwork: https://patchwork.linux-mips.org/patch/4730/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 1 changed file with 0 additions and 38 deletions Side-by-side Diff

arch/mips/kernel/perf_event_mipsxx.c
Diff comments   View file @ 4457af6
... ... @@ -847,7 +847,6 @@
847 847 [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
848 848 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
849 849 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
850   - [PERF_COUNT_HW_BUS_CYCLES] = { UNSUPPORTED_PERF_EVENT_ID },
851 850 };
852 851  
853 852 /* 24K/34K/1004K cores can share the same cache event map. */
854 853  
... ... @@ -1115,24 +1114,12 @@
1115 1114 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1116 1115 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1117 1116 },
1118   - [C(OP_PREFETCH)] = {
1119   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1120   - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1121   - },
1122 1117 },
1123 1118 [C(L1I)] = {
1124 1119 [C(OP_READ)] = {
1125 1120 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1126 1121 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1127 1122 },
1128   - [C(OP_WRITE)] = {
1129   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1130   - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1131   - },
1132   - [C(OP_PREFETCH)] = {
1133   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1134   - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1135   - },
1136 1123 },
1137 1124 [C(LL)] = {
1138 1125 [C(OP_READ)] = {
... ... @@ -1143,10 +1130,6 @@
1143 1130 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1144 1131 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1145 1132 },
1146   - [C(OP_PREFETCH)] = {
1147   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1148   - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1149   - },
1150 1133 },
1151 1134 [C(DTLB)] = {
1152 1135 /*
1153 1136  
1154 1137  
1155 1138  
1156 1139  
1157 1140  
1158 1141  
1159 1142  
... ... @@ -1154,44 +1137,23 @@
1154 1137 * read and write.
1155 1138 */
1156 1139 [C(OP_READ)] = {
1157   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1158 1140 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1159 1141 },
1160 1142 [C(OP_WRITE)] = {
1161   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1162 1143 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1163 1144 },
1164   - [C(OP_PREFETCH)] = {
1165   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1166   - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1167   - },
1168 1145 },
1169 1146 [C(ITLB)] = {
1170 1147 [C(OP_READ)] = {
1171   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1172 1148 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1173 1149 },
1174 1150 [C(OP_WRITE)] = {
1175   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1176 1151 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1177 1152 },
1178   - [C(OP_PREFETCH)] = {
1179   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1180   - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1181   - },
1182 1153 },
1183 1154 [C(BPU)] = {
1184 1155 [C(OP_READ)] = {
1185   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1186 1156 [C(RESULT_MISS)] = { 0x25, CNTR_ALL },
1187   - },
1188   - [C(OP_WRITE)] = {
1189   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1190   - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1191   - },
1192   - [C(OP_PREFETCH)] = {
1193   - [C(RESULT_ACCESS)] = { UNSUPPORTED_PERF_EVENT_ID },
1194   - [C(RESULT_MISS)] = { UNSUPPORTED_PERF_EVENT_ID },
1195 1157 },
1196 1158 },
1197 1159 };