[ARM] 4311/1: ixp4xx: add KIXRP435 platform

Add Intel KIXRP435 Reference Platform based on IXP43x processor. Fixed after review : access to cp15 removed in identification functions, used access to global processor_id instead Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Ruslan Sushko <rsushko@ru.mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

[ARM] 4311/1: ixp4xx: add KIXRP435 platform
Add Intel KIXRP435 Reference Platform based on IXP43x processor. Fixed after review : access to cp15 removed in identification functions, used access to global processor_id instead Signed-off-by: Vladimir Barinov <vbarinov@ru.mvista.com> Signed-off-by: Ruslan Sushko <rsushko@ru.mvista.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Ruslan V. Sushko · Russell King
1 parent 25735d10ba
Showing 12 changed files with 106 additions and 19 deletions Side-by-side Diff
arch/arm/configs/ixp4xx_defconfig
arch/arm/mach-ixp4xx/Kconfig
arch/arm/mach-ixp4xx/common-pci.c
arch/arm/mach-ixp4xx/common.c
arch/arm/mach-ixp4xx/ixdp425-pci.c
arch/arm/mach-ixp4xx/ixdp425-setup.c
arch/arm/mm/proc-xscale.S
include/asm-arm/arch-ixp4xx/entry-macro.S
include/asm-arm/arch-ixp4xx/hardware.h
include/asm-arm/arch-ixp4xx/io.h
include/asm-arm/arch-ixp4xx/irqs.h
include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -117,11 +117,13 @@
 CONFIG_ARCH_IXDP425=y
 CONFIG_MACH_IXDPG425=y
 CONFIG_MACH_IXDP465=y
+CONFIG_MACH_KIXRP435=y
 CONFIG_ARCH_IXCDP1100=y
 CONFIG_ARCH_PRPMC1100=y
 CONFIG_MACH_NAS100D=y
 CONFIG_ARCH_IXDP4XX=y
 CONFIG_CPU_IXP46X=y
+CONFIG_CPU_IXP43X=y
 # CONFIG_MACH_GTWX5715 is not set
  
 #
@@ -62,6 +62,12 @@
 	  IXDP465 Development Platform (Also known as BMP).
 	  For more information on this platform, see <file:Documentation/arm/IXP4xx>.
  
+config MACH_KIXRP435
+	bool "KIXRP435"
+	help
+	  Say 'Y' here if you want your kernel to support Intel's
+	  KIXRP435 Reference Platform.
+	  For more information on this platform, see <file:Documentation/arm/IXP4xx>.
  
 #
 # IXCDP1100 is the exact same HW as IXDP425, but with a different machine 
@@ -94,7 +100,7 @@
 #
 config	ARCH_IXDP4XX
 	bool
-	depends on ARCH_IXDP425 || MACH_IXDP465
+	depends on ARCH_IXDP425 || MACH_IXDP465 || MACH_KIXRP435
 	default y
  
 #
@@ -103,6 +109,11 @@
 config CPU_IXP46X
 	bool
 	depends on MACH_IXDP465
+	default y
+
+config CPU_IXP43X
+	bool
+	depends on MACH_KIXRP435
 	default y
  
 config MACH_GTWX5715
@@ -374,7 +374,7 @@
 	 * Determine which PCI read method to use.
 	 * Rev 0 IXP425 requires workaround.
 	 */
-	if (!(processor_id & 0xf) && !cpu_is_ixp46x()) {
+	if (!(processor_id & 0xf) && cpu_is_ixp42x()) {
 		printk("PCI: IXP42x A0 silicon detected - "
 			"PCI Non-Prefetch Workaround Enabled\n");
 		ixp4xx_pci_read = ixp4xx_pci_read_errata;
@@ -480,7 +480,7 @@
 	res[0].flags = IORESOURCE_IO;
  
 	res[1].name = "PCI Memory Space";
-	res[1].start = 0x48000000;
+	res[1].start = PCIBIOS_MIN_MEM;
 #ifndef CONFIG_IXP4XX_INDIRECT_PCI
 	res[1].end = 0x4bffffff;
 #else
@@ -192,7 +192,7 @@
  
 static void ixp4xx_irq_mask(unsigned int irq)
 {
-	if (cpu_is_ixp46x() && irq >= 32)
+	if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
 		*IXP4XX_ICMR2 &= ~(1 << (irq - 32));
 	else
 		*IXP4XX_ICMR &= ~(1 << irq);
@@ -215,7 +215,7 @@
 	if (!(ixp4xx_irq_edge & (1 << irq)))
 		ixp4xx_irq_ack(irq);
  
-	if (cpu_is_ixp46x() && irq >= 32)
+	if ((cpu_is_ixp46x() || cpu_is_ixp43x()) && irq >= 32)
 		*IXP4XX_ICMR2 |= (1 << (irq - 32));
 	else
 		*IXP4XX_ICMR |= (1 << irq);
@@ -239,7 +239,7 @@
 	/* Disable all interrupt */
 	*IXP4XX_ICMR = 0x0; 
  
-	if (cpu_is_ixp46x()) {
+	if (cpu_is_ixp46x() || cpu_is_ixp43x()) {
 		/* Route upper 32 sources to IRQ instead of FIQ */
 		*IXP4XX_ICLR2 = 0x00;
  
@@ -66,7 +66,7 @@
 int __init ixdp425_pci_init(void)
 {
 	if (machine_is_ixdp425() || machine_is_ixcdp1100() ||
-			machine_is_ixdp465())
+			machine_is_ixdp465() || machine_is_kixrp435())
 		pci_common_init(&ixdp425_pci);
 	return 0;
 }
@@ -115,6 +115,11 @@
 	ixdp425_flash_resource.end =
 		IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
  
+	if (cpu_is_ixp43x()) {
+		ixdp425_uart.num_resources = 1;
+		ixdp425_uart_data[1].flags = 0;
+	}
+
 	platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
 }
  
@@ -146,6 +151,19 @@
  
 #ifdef CONFIG_ARCH_PRPMC1100
 MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
+	/* Maintainer: MontaVista Software, Inc. */
+	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
+	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
+	.map_io		= ixp4xx_map_io,
+	.init_irq	= ixp4xx_init_irq,
+	.timer		= &ixp4xx_timer,
+	.boot_params	= 0x0100,
+	.init_machine	= ixdp425_init,
+MACHINE_END
+#endif
+
+#ifdef CONFIG_MACH_KIXRP435
+MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
 	/* Maintainer: MontaVista Software, Inc. */
 	.phys_io	= IXP4XX_PERIPHERAL_BASE_PHYS,
 	.io_pg_offst	= ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
@@ -584,6 +584,11 @@
 	.asciz	"XScale-IXP42x Family"
 	.size	cpu_ixp42x_name, . - cpu_ixp42x_name
  
+	.type	cpu_ixp43x_name, #object
+cpu_ixp43x_name:
+	.asciz	"XScale-IXP43x Family"
+	.size	cpu_ixp43x_name, . - cpu_ixp43x_name
+
 	.type	cpu_ixp46x_name, #object
 cpu_ixp46x_name:
 	.asciz	"XScale-IXP46x Family"
@@ -842,6 +847,29 @@
 	.long	xscale_mc_user_fns
 	.long	xscale_cache_fns
 	.size   __ixp42x_proc_info, . - __ixp42x_proc_info                
+
+	.type   __ixp43x_proc_info, #object
+__ixp43x_proc_info:
+	.long   0x69054040
+	.long   0xfffffff0
+	.long   PMD_TYPE_SECT | \
+		PMD_SECT_BUFFERABLE | \
+		PMD_SECT_CACHEABLE | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ
+	.long   PMD_TYPE_SECT | \
+		PMD_SECT_AP_WRITE | \
+		PMD_SECT_AP_READ
+	b       __xscale_setup
+	.long   cpu_arch_name
+	.long   cpu_elf_name
+	.long   HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
+	.long   cpu_ixp43x_name
+	.long   xscale_processor_functions
+	.long   v4wbi_tlb_fns
+	.long   xscale_mc_user_fns
+	.long   xscale_cache_fns
+	.size   __ixp43x_proc_info, . - __ixp43x_proc_info
  
 	.type	__ixp46x_proc_info, #object
 __ixp46x_proc_info:
@@ -31,9 +31,9 @@
  
 1001:
 		/*
-		 * IXP465 has an upper IRQ status register
+		 * IXP465/IXP435 has an upper IRQ status register
 		 */
-#if defined(CONFIG_CPU_IXP46X)
+#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
 		ldr	\irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
 		ldr	\irqstat, [\irqstat]		@ get upper interrupts
 		mov	\irqnr, #63
@@ -17,8 +17,8 @@
 #ifndef __ASM_ARCH_HARDWARE_H__
 #define __ASM_ARCH_HARDWARE_H__
  
-#define PCIBIOS_MIN_IO			0x00001000
-#define PCIBIOS_MIN_MEM			0x48000000
+#define PCIBIOS_MIN_IO		0x00001000
+#define PCIBIOS_MIN_MEM		(cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
  
 /*
  * We override the standard dma-mask routines for bouncing.
@@ -61,7 +61,7 @@
 static inline void __iomem *
 __ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags)
 {
-	if((addr < 0x48000000) || (addr > 0x4fffffff))
+	if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
 		return __ioremap(addr, size, flags);
  
 	return (void *)addr;
@@ -62,10 +62,10 @@
 /*
  * Only first 32 sources are valid if running on IXP42x systems
  */
-#ifndef	CONFIG_CPU_IXP46X
-#define NR_IRQS			32
-#else
+#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
 #define NR_IRQS			64
+#else
+#define NR_IRQS			32
 #endif
  
 #define	XSCALE_PMU_IRQ		(IRQ_IXP4XX_XSCALE_PMU)
@@ -607,15 +607,43 @@
  
 #define DCMD_LENGTH	0x01fff		/* length mask (max = 8K - 1) */
  
+/* Processor id value in CP15 Register 0 */
+#define IXP425_PROCESSOR_ID_VALUE	0x690541c0
+#define IXP435_PROCESSOR_ID_VALUE	0x69054040
+#define IXP465_PROCESSOR_ID_VALUE	0x69054200
+#define IXP4XX_PROCESSOR_ID_MASK	0xfffffff0
+
 #ifndef __ASSEMBLY__
+static inline int cpu_is_ixp42x(void)
+{
+	extern unsigned int processor_id;
+
+	if ((processor_id & IXP4XX_PROCESSOR_ID_MASK) ==
+	     IXP425_PROCESSOR_ID_VALUE )
+		return 1;
+
+	return 0;
+}
+
+static inline int cpu_is_ixp43x(void)
+{
+#ifdef CONFIG_CPU_IXP43X
+	extern unsigned int processor_id;
+
+	if ((processor_id & IXP4XX_PROCESSOR_ID_MASK) ==
+	     IXP435_PROCESSOR_ID_VALUE )
+		return 1;
+#endif
+	return 0;
+}
+
 static inline int cpu_is_ixp46x(void)
 {
 #ifdef CONFIG_CPU_IXP46X
-	unsigned int processor_id;
+	extern unsigned int processor_id;
  
-	asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
-
-	if ((processor_id & 0xffffff00) == 0x69054200)
+	if ((processor_id & IXP4XX_PROCESSOR_ID_MASK) ==
+	     IXP465_PROCESSOR_ID_VALUE )
 		return 1;
 #endif
 	return 0;
...	...	@@ -117,11 +117,13 @@
117	117	CONFIG_ARCH_IXDP425=y
118	118	CONFIG_MACH_IXDPG425=y
119	119	CONFIG_MACH_IXDP465=y
	120	+CONFIG_MACH_KIXRP435=y
120	121	CONFIG_ARCH_IXCDP1100=y
121	122	CONFIG_ARCH_PRPMC1100=y
122	123	CONFIG_MACH_NAS100D=y
123	124	CONFIG_ARCH_IXDP4XX=y
124	125	CONFIG_CPU_IXP46X=y
	126	+CONFIG_CPU_IXP43X=y
125	127	# CONFIG_MACH_GTWX5715 is not set
126	128
127	129	#
...	...	@@ -62,6 +62,12 @@
62	62	IXDP465 Development Platform (Also known as BMP).
63	63	For more information on this platform, see <file:Documentation/arm/IXP4xx>.
64	64
	65	+config MACH_KIXRP435
	66	+ bool "KIXRP435"
	67	+ help
	68	+ Say 'Y' here if you want your kernel to support Intel's
	69	+ KIXRP435 Reference Platform.
	70	+ For more information on this platform, see <file:Documentation/arm/IXP4xx>.
65	71
66	72	#
67	73	# IXCDP1100 is the exact same HW as IXDP425, but with a different machine
...	...	@@ -94,7 +100,7 @@
94	100	#
95	101	config ARCH_IXDP4XX
96	102	bool
97		- depends on ARCH_IXDP425 \|\| MACH_IXDP465
	103	+ depends on ARCH_IXDP425 \|\| MACH_IXDP465 \|\| MACH_KIXRP435
98	104	default y
99	105
100	106	#
...	...	@@ -103,6 +109,11 @@
103	109	config CPU_IXP46X
104	110	bool
105	111	depends on MACH_IXDP465
	112	+ default y
	113	+
	114	+config CPU_IXP43X
	115	+ bool
	116	+ depends on MACH_KIXRP435
106	117	default y
107	118
108	119	config MACH_GTWX5715
...	...	@@ -374,7 +374,7 @@
374	374	* Determine which PCI read method to use.
375	375	* Rev 0 IXP425 requires workaround.
376	376	*/
377		- if (!(processor_id & 0xf) && !cpu_is_ixp46x()) {
	377	+ if (!(processor_id & 0xf) && cpu_is_ixp42x()) {
378	378	printk("PCI: IXP42x A0 silicon detected - "
379	379	"PCI Non-Prefetch Workaround Enabled\n");
380	380	ixp4xx_pci_read = ixp4xx_pci_read_errata;
...	...	@@ -480,7 +480,7 @@
480	480	res[0].flags = IORESOURCE_IO;
481	481
482	482	res[1].name = "PCI Memory Space";
483		- res[1].start = 0x48000000;
	483	+ res[1].start = PCIBIOS_MIN_MEM;
484	484	#ifndef CONFIG_IXP4XX_INDIRECT_PCI
485	485	res[1].end = 0x4bffffff;
486	486	#else
...	...	@@ -192,7 +192,7 @@
192	192
193	193	static void ixp4xx_irq_mask(unsigned int irq)
194	194	{
195		- if (cpu_is_ixp46x() && irq >= 32)
	195	+ if ((cpu_is_ixp46x() \|\| cpu_is_ixp43x()) && irq >= 32)
196	196	*IXP4XX_ICMR2 &= ~(1 << (irq - 32));
197	197	else
198	198	*IXP4XX_ICMR &= ~(1 << irq);
...	...	@@ -215,7 +215,7 @@
215	215	if (!(ixp4xx_irq_edge & (1 << irq)))
216	216	ixp4xx_irq_ack(irq);
217	217
218		- if (cpu_is_ixp46x() && irq >= 32)
	218	+ if ((cpu_is_ixp46x() \|\| cpu_is_ixp43x()) && irq >= 32)
219	219	*IXP4XX_ICMR2 \|= (1 << (irq - 32));
220	220	else
221	221	*IXP4XX_ICMR \|= (1 << irq);
...	...	@@ -239,7 +239,7 @@
239	239	/* Disable all interrupt */
240	240	*IXP4XX_ICMR = 0x0;
241	241
242		- if (cpu_is_ixp46x()) {
	242	+ if (cpu_is_ixp46x() \|\| cpu_is_ixp43x()) {
243	243	/* Route upper 32 sources to IRQ instead of FIQ */
244	244	*IXP4XX_ICLR2 = 0x00;
245	245
...	...	@@ -66,7 +66,7 @@
66	66	int __init ixdp425_pci_init(void)
67	67	{
68	68	if (machine_is_ixdp425() \|\| machine_is_ixcdp1100() \|\|
69		- machine_is_ixdp465())
	69	+ machine_is_ixdp465() \|\| machine_is_kixrp435())
70	70	pci_common_init(&ixdp425_pci);
71	71	return 0;
72	72	}
...	...	@@ -115,6 +115,11 @@
115	115	ixdp425_flash_resource.end =
116	116	IXP4XX_EXP_BUS_BASE(0) + ixp4xx_exp_bus_size - 1;
117	117
	118	+ if (cpu_is_ixp43x()) {
	119	+ ixdp425_uart.num_resources = 1;
	120	+ ixdp425_uart_data[1].flags = 0;
	121	+ }
	122	+
118	123	platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
119	124	}
120	125
...	...	@@ -146,6 +151,19 @@
146	151
147	152	#ifdef CONFIG_ARCH_PRPMC1100
148	153	MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
	154	+ /* Maintainer: MontaVista Software, Inc. */
	155	+ .phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
	156	+ .io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
	157	+ .map_io = ixp4xx_map_io,
	158	+ .init_irq = ixp4xx_init_irq,
	159	+ .timer = &ixp4xx_timer,
	160	+ .boot_params = 0x0100,
	161	+ .init_machine = ixdp425_init,
	162	+MACHINE_END
	163	+#endif
	164	+
	165	+#ifdef CONFIG_MACH_KIXRP435
	166	+MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
149	167	/* Maintainer: MontaVista Software, Inc. */
150	168	.phys_io = IXP4XX_PERIPHERAL_BASE_PHYS,
151	169	.io_pg_offst = ((IXP4XX_PERIPHERAL_BASE_VIRT) >> 18) & 0xfffc,
...	...	@@ -584,6 +584,11 @@
584	584	.asciz "XScale-IXP42x Family"
585	585	.size cpu_ixp42x_name, . - cpu_ixp42x_name
586	586
	587	+ .type cpu_ixp43x_name, #object
	588	+cpu_ixp43x_name:
	589	+ .asciz "XScale-IXP43x Family"
	590	+ .size cpu_ixp43x_name, . - cpu_ixp43x_name
	591	+
587	592	.type cpu_ixp46x_name, #object
588	593	cpu_ixp46x_name:
589	594	.asciz "XScale-IXP46x Family"
...	...	@@ -842,6 +847,29 @@
842	847	.long xscale_mc_user_fns
843	848	.long xscale_cache_fns
844	849	.size __ixp42x_proc_info, . - __ixp42x_proc_info
	850	+
	851	+ .type __ixp43x_proc_info, #object
	852	+__ixp43x_proc_info:
	853	+ .long 0x69054040
	854	+ .long 0xfffffff0
	855	+ .long PMD_TYPE_SECT \| \
	856	+ PMD_SECT_BUFFERABLE \| \
	857	+ PMD_SECT_CACHEABLE \| \
	858	+ PMD_SECT_AP_WRITE \| \
	859	+ PMD_SECT_AP_READ
	860	+ .long PMD_TYPE_SECT \| \
	861	+ PMD_SECT_AP_WRITE \| \
	862	+ PMD_SECT_AP_READ
	863	+ b __xscale_setup
	864	+ .long cpu_arch_name
	865	+ .long cpu_elf_name
	866	+ .long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP
	867	+ .long cpu_ixp43x_name
	868	+ .long xscale_processor_functions
	869	+ .long v4wbi_tlb_fns
	870	+ .long xscale_mc_user_fns
	871	+ .long xscale_cache_fns
	872	+ .size __ixp43x_proc_info, . - __ixp43x_proc_info
845	873
846	874	.type __ixp46x_proc_info, #object
847	875	__ixp46x_proc_info:
...	...	@@ -31,9 +31,9 @@
31	31
32	32	1001:
33	33	/*
34		- * IXP465 has an upper IRQ status register
	34	+ * IXP465/IXP435 has an upper IRQ status register
35	35	*/
36		-#if defined(CONFIG_CPU_IXP46X)
	36	+#if defined(CONFIG_CPU_IXP46X) \|\| defined(CONFIG_CPU_IXP43X)
37	37	ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
38	38	ldr \irqstat, [\irqstat] @ get upper interrupts
39	39	mov \irqnr, #63
...	...	@@ -17,8 +17,8 @@
17	17	#ifndef __ASM_ARCH_HARDWARE_H__
18	18	#define __ASM_ARCH_HARDWARE_H__
19	19
20		-#define PCIBIOS_MIN_IO 0x00001000
21		-#define PCIBIOS_MIN_MEM 0x48000000
	20	+#define PCIBIOS_MIN_IO 0x00001000
	21	+#define PCIBIOS_MIN_MEM (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
22	22
23	23	/*
24	24	* We override the standard dma-mask routines for bouncing.
...	...	@@ -61,7 +61,7 @@
61	61	static inline void __iomem *
62	62	__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags)
63	63	{
64		- if((addr < 0x48000000) \|\| (addr > 0x4fffffff))
	64	+ if((addr < PCIBIOS_MIN_MEM) \|\| (addr > 0x4fffffff))
65	65	return __ioremap(addr, size, flags);
66	66
67	67	return (void *)addr;