Commit 4981d01eada5354d81c8929d5b2836829ba3df7b
Committed by
Ingo Molnar
Ingo Molnar
1 parent
e8e999cf3c
Exists in
master
and in
7 other branches
x86: Flush TLB if PGD entry is changed in i386 PAE mode
According to intel CPU manual, every time PGD entry is changed in i386 PAE mode, we need do a full TLB flush. Current code follows this and there is comment for this too in the code. But current code misses the multi-threaded case. A changed page table might be used by several CPUs, every such CPU should flush TLB. Usually this isn't a problem, because we prepopulate all PGD entries at process fork. But when the process does munmap and follows new mmap, this issue will be triggered. When it happens, some CPUs keep doing page faults: http://marc.info/?l=linux-kernel&m=129915020508238&w=2 Reported-by: Yasunori Goto<y-goto@jp.fujitsu.com> Tested-by: Yasunori Goto<y-goto@jp.fujitsu.com> Reviewed-by: Rik van Riel <riel@redhat.com> Signed-off-by: Shaohua Li<shaohua.li@intel.com> Cc: Mallick Asit K <asit.k.mallick@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: linux-mm <linux-mm@kvack.org> Cc: stable <stable@kernel.org> LKML-Reference: <1300246649.2337.95.camel@sli10-conroe> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Showing 2 changed files with 4 additions and 10 deletions Side-by-side Diff
arch/x86/include/asm/pgtable-3level.h
| ... | ... | @@ -69,8 +69,6 @@ |
| 69 | 69 | |
| 70 | 70 | static inline void pud_clear(pud_t *pudp) |
| 71 | 71 | { |
| 72 | - unsigned long pgd; | |
| 73 | - | |
| 74 | 72 | set_pud(pudp, __pud(0)); |
| 75 | 73 | |
| 76 | 74 | /* |
| 77 | 75 | |
| ... | ... | @@ -79,13 +77,10 @@ |
| 79 | 77 | * section 8.1: in PAE mode we explicitly have to flush the |
| 80 | 78 | * TLB via cr3 if the top-level pgd is changed... |
| 81 | 79 | * |
| 82 | - * Make sure the pud entry we're updating is within the | |
| 83 | - * current pgd to avoid unnecessary TLB flushes. | |
| 80 | + * Currently all places where pud_clear() is called either have | |
| 81 | + * flush_tlb_mm() followed or don't need TLB flush (x86_64 code or | |
| 82 | + * pud_clear_bad()), so we don't need TLB flush here. | |
| 84 | 83 | */ |
| 85 | - pgd = read_cr3(); | |
| 86 | - if (__pa(pudp) >= pgd && __pa(pudp) < | |
| 87 | - (pgd + sizeof(pgd_t)*PTRS_PER_PGD)) | |
| 88 | - write_cr3(pgd); | |
| 89 | 84 | } |
| 90 | 85 | |
| 91 | 86 | #ifdef CONFIG_SMP |
arch/x86/mm/pgtable.c
| ... | ... | @@ -168,8 +168,7 @@ |
| 168 | 168 | * section 8.1: in PAE mode we explicitly have to flush the |
| 169 | 169 | * TLB via cr3 if the top-level pgd is changed... |
| 170 | 170 | */ |
| 171 | - if (mm == current->active_mm) | |
| 172 | - write_cr3(read_cr3()); | |
| 171 | + flush_tlb_mm(mm); | |
| 173 | 172 | } |
| 174 | 173 | #else /* !CONFIG_X86_PAE */ |
| 175 | 174 |