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Commit 4b724efdde0287d7ba616bd2badc63fca414f978

Authored by Ralf Baechle
1 parent 3fccc0150e
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

Get rid of SINGLE_ONLY_FPU. Linux does not support half FPU other than 

by emulation of a full FPU.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 1 changed file with 8 additions and 62 deletions Side-by-side Diff

arch/mips/math-emu/cp1emu.c
Diff comments   View file @ 4b724ef
... ... @@ -256,7 +256,6 @@
256 256 emul:
257 257 fpuemustats.emulated++;
258 258 switch (MIPSInst_OPCODE(ir)) {
259   -#ifndef SINGLE_ONLY_FPU
260 259 case ldc1_op:{
261 260 u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] +
262 261 MIPSInst_SIMM(ir));
... ... @@ -284,7 +283,6 @@
284 283 }
285 284 break;
286 285 }
287   -#endif
288 286  
289 287 case lwc1_op:{
290 288 u32 __user *va = (u32 __user *) (xcp->regs[MIPSInst_RS(ir)] +
... ... @@ -296,12 +294,6 @@
296 294 fpuemustats.errors++;
297 295 return SIGBUS;
298 296 }
299   -#ifdef SINGLE_ONLY_FPU
300   - if (MIPSInst_RT(ir) & 1) {
301   - /* illegal register in single-float mode */
302   - return SIGILL;
303   - }
304   -#endif
305 297 SITOREG(val, MIPSInst_RT(ir));
306 298 break;
307 299 }
... ... @@ -312,12 +304,6 @@
312 304 u32 val;
313 305  
314 306 fpuemustats.stores++;
315   -#ifdef SINGLE_ONLY_FPU
316   - if (MIPSInst_RT(ir) & 1) {
317   - /* illegal register in single-float mode */
318   - return SIGILL;
319   - }
320   -#endif
321 307 SIFROMREG(val, MIPSInst_RT(ir));
322 308 if (put_user(val, va)) {
323 309 fpuemustats.errors++;
... ... @@ -329,7 +315,7 @@
329 315 case cop1_op:
330 316 switch (MIPSInst_RS(ir)) {
331 317  
332   -#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
  318 +#if defined(__mips64)
333 319 case dmfc_op:
334 320 /* copregister fs -> gpr[rt] */
335 321 if (MIPSInst_RT(ir) != 0) {
... ... @@ -346,12 +332,6 @@
346 332  
347 333 case mfc_op:
348 334 /* copregister rd -> gpr[rt] */
349   -#ifdef SINGLE_ONLY_FPU
350   - if (MIPSInst_RD(ir) & 1) {
351   - /* illegal register in single-float mode */
352   - return SIGILL;
353   - }
354   -#endif
355 335 if (MIPSInst_RT(ir) != 0) {
356 336 SIFROMREG(xcp->regs[MIPSInst_RT(ir)],
357 337 MIPSInst_RD(ir));
... ... @@ -360,12 +340,6 @@
360 340  
361 341 case mtc_op:
362 342 /* copregister rd <- rt */
363   -#ifdef SINGLE_ONLY_FPU
364   - if (MIPSInst_RD(ir) & 1) {
365   - /* illegal register in single-float mode */
366   - return SIGILL;
367   - }
368   -#endif
369 343 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir));
370 344 break;
371 345  
... ... @@ -467,7 +441,7 @@
467 441 switch (MIPSInst_OPCODE(ir)) {
468 442 case lwc1_op:
469 443 case swc1_op:
470   -#if (__mips >= 2 || defined(__mips64)) && !defined(SINGLE_ONLY_FPU)
  444 +#if (__mips >= 2 || defined(__mips64))
471 445 case ldc1_op:
472 446 case sdc1_op:
473 447 #endif
... ... @@ -646,14 +620,6 @@
646 620 fpuemustats.errors++;
647 621 return SIGBUS;
648 622 }
649   -#ifdef SINGLE_ONLY_FPU
650   - if (MIPSInst_FD(ir) & 1) {
651   - /* illegal register in single-float
652   - * mode
653   - */
654   - return SIGILL;
655   - }
656   -#endif
657 623 SITOREG(val, MIPSInst_FD(ir));
658 624 break;
659 625  
... ... @@ -662,14 +628,6 @@
662 628 xcp->regs[MIPSInst_FT(ir)]);
663 629  
664 630 fpuemustats.stores++;
665   -#ifdef SINGLE_ONLY_FPU
666   - if (MIPSInst_FS(ir) & 1) {
667   - /* illegal register in single-float
668   - * mode
669   - */
670   - return SIGILL;
671   - }
672   -#endif
673 631  
674 632 SIFROMREG(val, MIPSInst_FS(ir));
675 633 if (put_user(val, va)) {
... ... @@ -723,7 +681,6 @@
723 681 break;
724 682 }
725 683  
726   -#ifndef SINGLE_ONLY_FPU
727 684 case d_fmt:{ /* 1 */
728 685 ieee754dp(*handler) (ieee754dp, ieee754dp, ieee754dp);
729 686 ieee754dp fd, fr, fs, ft;
... ... @@ -781,7 +738,6 @@
781 738 }
782 739 break;
783 740 }
784   -#endif
785 741  
786 742 case 0x7: /* 7 */
787 743 if (MIPSInst_FUNC(ir) != pfetch_op) {
... ... @@ -921,9 +877,6 @@
921 877 case fcvts_op:
922 878 return SIGILL; /* not defined */
923 879 case fcvtd_op:{
924   -#ifdef SINGLE_ONLY_FPU
925   - return SIGILL; /* not defined */
926   -#else
927 880 ieee754sp fs;
928 881  
929 882 SPFROMREG(fs, MIPSInst_FS(ir));
... ... @@ -931,7 +884,6 @@
931 884 rfmt = d_fmt;
932 885 goto copcsr;
933 886 }
934   -#endif
935 887 case fcvtw_op:{
936 888 ieee754sp fs;
937 889  
... ... @@ -958,7 +910,7 @@
958 910 }
959 911 #endif /* __mips >= 2 */
960 912  
961   -#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
  913 +#if defined(__mips64)
962 914 case fcvtl_op:{
963 915 ieee754sp fs;
964 916  
... ... @@ -982,7 +934,7 @@
982 934 rfmt = l_fmt;
983 935 goto copcsr;
984 936 }
985   -#endif /* defined(__mips64) && !fpu(single) */
  937 +#endif /* defined(__mips64) */
986 938  
987 939 default:
988 940 if (MIPSInst_FUNC(ir) >= fcmp_op) {
... ... @@ -1009,7 +961,6 @@
1009 961 break;
1010 962 }
1011 963  
1012   -#ifndef SINGLE_ONLY_FPU
1013 964 case d_fmt:{
1014 965 union {
1015 966 ieee754dp(*b) (ieee754dp, ieee754dp);
... ... @@ -1133,7 +1084,7 @@
1133 1084 }
1134 1085 #endif
1135 1086  
1136   -#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
  1087 +#if defined(__mips64)
1137 1088 case fcvtl_op:{
1138 1089 ieee754dp fs;
1139 1090  
... ... @@ -1157,7 +1108,7 @@
1157 1108 rfmt = l_fmt;
1158 1109 goto copcsr;
1159 1110 }
1160   -#endif /* __mips >= 3 && !fpu(single) */
  1111 +#endif /* __mips >= 3 */
1161 1112  
1162 1113 default:
1163 1114 if (MIPSInst_FUNC(ir) >= fcmp_op) {
... ... @@ -1185,7 +1136,6 @@
1185 1136 }
1186 1137 break;
1187 1138 }
1188   -#endif /* ifndef SINGLE_ONLY_FPU */
1189 1139  
1190 1140 case w_fmt:{
1191 1141 ieee754sp fs;
1192 1142  
1193 1143  
... ... @@ -1197,21 +1147,19 @@
1197 1147 rv.s = ieee754sp_fint(fs.bits);
1198 1148 rfmt = s_fmt;
1199 1149 goto copcsr;
1200   -#ifndef SINGLE_ONLY_FPU
1201 1150 case fcvtd_op:
1202 1151 /* convert word to double precision real */
1203 1152 SPFROMREG(fs, MIPSInst_FS(ir));
1204 1153 rv.d = ieee754dp_fint(fs.bits);
1205 1154 rfmt = d_fmt;
1206 1155 goto copcsr;
1207   -#endif
1208 1156 default:
1209 1157 return SIGILL;
1210 1158 }
1211 1159 break;
1212 1160 }
1213 1161  
1214   -#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
  1162 +#if defined(__mips64)
1215 1163 case l_fmt:{
1216 1164 switch (MIPSInst_FUNC(ir)) {
1217 1165 case fcvts_op:
1218 1166  
1219 1167  
... ... @@ -1264,18 +1212,16 @@
1264 1212 ctx->fcr31 &= ~cond;
1265 1213 break;
1266 1214 }
1267   -#ifndef SINGLE_ONLY_FPU
1268 1215 case d_fmt:
1269 1216 DPTOREG(rv.d, MIPSInst_FD(ir));
1270 1217 break;
1271   -#endif
1272 1218 case s_fmt:
1273 1219 SPTOREG(rv.s, MIPSInst_FD(ir));
1274 1220 break;
1275 1221 case w_fmt:
1276 1222 SITOREG(rv.w, MIPSInst_FD(ir));
1277 1223 break;
1278   -#if defined(__mips64) && !defined(SINGLE_ONLY_FPU)
  1224 +#if defined(__mips64)
1279 1225 case l_fmt:
1280 1226 DITOREG(rv.l, MIPSInst_FD(ir));
1281 1227 break;