Commit 4ca2c04085a1caa903e92a5fc0da25362150aac2

Authored by Thomas Petazzoni
Committed by Jason Cooper
1 parent c5d0ecc98c

ARM: orion5x: Move to ID based window creation

With the introduction of the ID based MBus API, it's better
to switch to use it instead of the current name based scheme.

This will allow to deprecate the name based API, once every
user is removed.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>

Showing 22 changed files with 137 additions and 70 deletions Side-by-side Diff

arch/arm/mach-orion5x/common.c
... ... @@ -174,8 +174,10 @@
174 174 ****************************************************************************/
175 175 static void __init orion5x_crypto_init(void)
176 176 {
177   - mvebu_mbus_add_window("sram", ORION5X_SRAM_PHYS_BASE,
178   - ORION5X_SRAM_SIZE);
  177 + mvebu_mbus_add_window_by_id(ORION_MBUS_SRAM_TARGET,
  178 + ORION_MBUS_SRAM_ATTR,
  179 + ORION5X_SRAM_PHYS_BASE,
  180 + ORION5X_SRAM_SIZE);
179 181 orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
180 182 SZ_8K, IRQ_ORION5X_CESA);
181 183 }
182 184  
183 185  
... ... @@ -222,22 +224,24 @@
222 224 * The PCIe windows will no longer be statically allocated
223 225 * here once Orion5x is migrated to the pci-mvebu driver.
224 226 */
225   - mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_IO_PHYS_BASE,
  227 + mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCIE_IO_TARGET,
  228 + ORION_MBUS_PCIE_IO_ATTR,
  229 + ORION5X_PCIE_IO_PHYS_BASE,
226 230 ORION5X_PCIE_IO_SIZE,
227   - ORION5X_PCIE_IO_BUS_BASE,
228   - MVEBU_MBUS_PCI_IO);
229   - mvebu_mbus_add_window_remap_flags("pcie0.0", ORION5X_PCIE_MEM_PHYS_BASE,
230   - ORION5X_PCIE_MEM_SIZE,
231   - MVEBU_MBUS_NO_REMAP,
232   - MVEBU_MBUS_PCI_MEM);
233   - mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_IO_PHYS_BASE,
  231 + ORION5X_PCIE_IO_BUS_BASE);
  232 + mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_MEM_TARGET,
  233 + ORION_MBUS_PCIE_MEM_ATTR,
  234 + ORION5X_PCIE_MEM_PHYS_BASE,
  235 + ORION5X_PCIE_MEM_SIZE);
  236 + mvebu_mbus_add_window_remap_by_id(ORION_MBUS_PCI_IO_TARGET,
  237 + ORION_MBUS_PCI_IO_ATTR,
  238 + ORION5X_PCI_IO_PHYS_BASE,
234 239 ORION5X_PCI_IO_SIZE,
235   - ORION5X_PCI_IO_BUS_BASE,
236   - MVEBU_MBUS_PCI_IO);
237   - mvebu_mbus_add_window_remap_flags("pci0.0", ORION5X_PCI_MEM_PHYS_BASE,
238   - ORION5X_PCI_MEM_SIZE,
239   - MVEBU_MBUS_NO_REMAP,
240   - MVEBU_MBUS_PCI_MEM);
  240 + ORION5X_PCI_IO_BUS_BASE);
  241 + mvebu_mbus_add_window_by_id(ORION_MBUS_PCI_MEM_TARGET,
  242 + ORION_MBUS_PCI_MEM_ATTR,
  243 + ORION5X_PCI_MEM_PHYS_BASE,
  244 + ORION5X_PCI_MEM_SIZE);
241 245 }
242 246  
243 247 int orion5x_tclk;
arch/arm/mach-orion5x/common.h
... ... @@ -7,6 +7,23 @@
7 7 struct mv643xx_eth_platform_data;
8 8 struct mv_sata_platform_data;
9 9  
  10 +#define ORION_MBUS_PCIE_MEM_TARGET 0x04
  11 +#define ORION_MBUS_PCIE_MEM_ATTR 0x59
  12 +#define ORION_MBUS_PCIE_IO_TARGET 0x04
  13 +#define ORION_MBUS_PCIE_IO_ATTR 0x51
  14 +#define ORION_MBUS_PCIE_WA_TARGET 0x04
  15 +#define ORION_MBUS_PCIE_WA_ATTR 0x79
  16 +#define ORION_MBUS_PCI_MEM_TARGET 0x03
  17 +#define ORION_MBUS_PCI_MEM_ATTR 0x59
  18 +#define ORION_MBUS_PCI_IO_TARGET 0x03
  19 +#define ORION_MBUS_PCI_IO_ATTR 0x51
  20 +#define ORION_MBUS_DEVBUS_BOOT_TARGET 0x01
  21 +#define ORION_MBUS_DEVBUS_BOOT_ATTR 0x0f
  22 +#define ORION_MBUS_DEVBUS_TARGET(cs) 0x01
  23 +#define ORION_MBUS_DEVBUS_ATTR(cs) (~(1 << cs))
  24 +#define ORION_MBUS_SRAM_TARGET 0x00
  25 +#define ORION_MBUS_SRAM_ATTR 0x00
  26 +
10 27 /*
11 28 * Basic Orion init functions used early by machine-setup.
12 29 */
arch/arm/mach-orion5x/d2net-setup.c
... ... @@ -317,8 +317,10 @@
317 317 d2net_sata_power_init();
318 318 orion5x_sata_init(&d2net_sata_data);
319 319  
320   - mvebu_mbus_add_window("devbus-boot", D2NET_NOR_BOOT_BASE,
321   - D2NET_NOR_BOOT_SIZE);
  320 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  321 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  322 + D2NET_NOR_BOOT_BASE,
  323 + D2NET_NOR_BOOT_SIZE);
322 324 platform_device_register(&d2net_nor_flash);
323 325  
324 326 platform_device_register(&d2net_gpio_buttons);
arch/arm/mach-orion5x/db88f5281-setup.c
... ... @@ -340,19 +340,27 @@
340 340 orion5x_uart0_init();
341 341 orion5x_uart1_init();
342 342  
343   - mvebu_mbus_add_window("devbus-boot", DB88F5281_NOR_BOOT_BASE,
344   - DB88F5281_NOR_BOOT_SIZE);
  343 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  344 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  345 + DB88F5281_NOR_BOOT_BASE,
  346 + DB88F5281_NOR_BOOT_SIZE);
345 347 platform_device_register(&db88f5281_boot_flash);
346 348  
347   - mvebu_mbus_add_window("devbus-cs0", DB88F5281_7SEG_BASE,
348   - DB88F5281_7SEG_SIZE);
  349 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
  350 + ORION_MBUS_DEVBUS_ATTR(0),
  351 + DB88F5281_7SEG_BASE,
  352 + DB88F5281_7SEG_SIZE);
349 353  
350   - mvebu_mbus_add_window("devbus-cs1", DB88F5281_NOR_BASE,
351   - DB88F5281_NOR_SIZE);
  354 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
  355 + ORION_MBUS_DEVBUS_ATTR(1),
  356 + DB88F5281_NOR_BASE,
  357 + DB88F5281_NOR_SIZE);
352 358 platform_device_register(&db88f5281_nor_flash);
353 359  
354   - mvebu_mbus_add_window("devbus-cs2", DB88F5281_NAND_BASE,
355   - DB88F5281_NAND_SIZE);
  360 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(2),
  361 + ORION_MBUS_DEVBUS_ATTR(2),
  362 + DB88F5281_NAND_BASE,
  363 + DB88F5281_NAND_SIZE);
356 364 platform_device_register(&db88f5281_nand_flash);
357 365  
358 366 i2c_register_board_info(0, &db88f5281_i2c_rtc, 1);
arch/arm/mach-orion5x/dns323-setup.c
... ... @@ -611,8 +611,10 @@
611 611 /* setup flash mapping
612 612 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
613 613 */
614   - mvebu_mbus_add_window("devbus-boot", DNS323_NOR_BOOT_BASE,
615   - DNS323_NOR_BOOT_SIZE);
  614 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  615 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  616 + DNS323_NOR_BOOT_BASE,
  617 + DNS323_NOR_BOOT_SIZE);
616 618 platform_device_register(&dns323_nor_flash);
617 619  
618 620 /* Sort out LEDs, Buttons and i2c devices */
arch/arm/mach-orion5x/edmini_v2-setup.c
... ... @@ -154,8 +154,10 @@
154 154 orion5x_ehci0_init();
155 155 orion5x_eth_init(&edmini_v2_eth_data);
156 156  
157   - mvebu_mbus_add_window("devbus-boot", EDMINI_V2_NOR_BOOT_BASE,
158   - EDMINI_V2_NOR_BOOT_SIZE);
  157 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  158 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  159 + EDMINI_V2_NOR_BOOT_BASE,
  160 + EDMINI_V2_NOR_BOOT_SIZE);
159 161 platform_device_register(&edmini_v2_nor_flash);
160 162  
161 163 pr_notice("edmini_v2: USB device port, flash write and power-off "
arch/arm/mach-orion5x/kurobox_pro-setup.c
... ... @@ -359,13 +359,17 @@
359 359 orion5x_uart1_init();
360 360 orion5x_xor_init();
361 361  
362   - mvebu_mbus_add_window("devbus-boot", KUROBOX_PRO_NOR_BOOT_BASE,
363   - KUROBOX_PRO_NOR_BOOT_SIZE);
  362 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  363 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  364 + KUROBOX_PRO_NOR_BOOT_BASE,
  365 + KUROBOX_PRO_NOR_BOOT_SIZE);
364 366 platform_device_register(&kurobox_pro_nor_flash);
365 367  
366 368 if (machine_is_kurobox_pro()) {
367   - mvebu_mbus_add_window("devbus-cs0", KUROBOX_PRO_NAND_BASE,
368   - KUROBOX_PRO_NAND_SIZE);
  369 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(0),
  370 + ORION_MBUS_DEVBUS_ATTR(0),
  371 + KUROBOX_PRO_NAND_BASE,
  372 + KUROBOX_PRO_NAND_SIZE);
369 373 platform_device_register(&kurobox_pro_nand_flash);
370 374 }
371 375  
arch/arm/mach-orion5x/ls-chl-setup.c
... ... @@ -294,8 +294,10 @@
294 294 orion5x_uart0_init();
295 295 orion5x_xor_init();
296 296  
297   - mvebu_mbus_add_window("devbus-boot", LSCHL_NOR_BOOT_BASE,
298   - LSCHL_NOR_BOOT_SIZE);
  297 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  298 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  299 + LSCHL_NOR_BOOT_BASE,
  300 + LSCHL_NOR_BOOT_SIZE);
299 301 platform_device_register(&lschl_nor_flash);
300 302  
301 303 platform_device_register(&lschl_leds);
arch/arm/mach-orion5x/ls_hgl-setup.c
... ... @@ -243,8 +243,10 @@
243 243 orion5x_uart0_init();
244 244 orion5x_xor_init();
245 245  
246   - mvebu_mbus_add_window("devbus-boot", LS_HGL_NOR_BOOT_BASE,
247   - LS_HGL_NOR_BOOT_SIZE);
  246 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  247 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  248 + LS_HGL_NOR_BOOT_BASE,
  249 + LS_HGL_NOR_BOOT_SIZE);
248 250 platform_device_register(&ls_hgl_nor_flash);
249 251  
250 252 platform_device_register(&ls_hgl_button_device);
arch/arm/mach-orion5x/lsmini-setup.c
... ... @@ -244,8 +244,10 @@
244 244 orion5x_uart0_init();
245 245 orion5x_xor_init();
246 246  
247   - mvebu_mbus_add_window("devbus-boot", LSMINI_NOR_BOOT_BASE,
248   - LSMINI_NOR_BOOT_SIZE);
  247 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  248 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  249 + LSMINI_NOR_BOOT_BASE,
  250 + LSMINI_NOR_BOOT_SIZE);
249 251 platform_device_register(&lsmini_nor_flash);
250 252  
251 253 platform_device_register(&lsmini_button_device);
arch/arm/mach-orion5x/mss2-setup.c
... ... @@ -241,8 +241,10 @@
241 241 orion5x_uart0_init();
242 242 orion5x_xor_init();
243 243  
244   - mvebu_mbus_add_window("devbus-boot", MSS2_NOR_BOOT_BASE,
245   - MSS2_NOR_BOOT_SIZE);
  244 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  245 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  246 + MSS2_NOR_BOOT_BASE,
  247 + MSS2_NOR_BOOT_SIZE);
246 248 platform_device_register(&mss2_nor_flash);
247 249  
248 250 platform_device_register(&mss2_button_device);
arch/arm/mach-orion5x/mv2120-setup.c
... ... @@ -204,8 +204,10 @@
204 204 orion5x_uart0_init();
205 205 orion5x_xor_init();
206 206  
207   - mvebu_mbus_add_window("devbus-boot", MV2120_NOR_BOOT_BASE,
208   - MV2120_NOR_BOOT_SIZE);
  207 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  208 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  209 + MV2120_NOR_BOOT_BASE,
  210 + MV2120_NOR_BOOT_SIZE);
209 211 platform_device_register(&mv2120_nor_flash);
210 212  
211 213 platform_device_register(&mv2120_button_device);
arch/arm/mach-orion5x/net2big-setup.c
... ... @@ -397,8 +397,10 @@
397 397 net2big_sata_power_init();
398 398 orion5x_sata_init(&net2big_sata_data);
399 399  
400   - mvebu_mbus_add_window("devbus-boot", NET2BIG_NOR_BOOT_BASE,
401   - NET2BIG_NOR_BOOT_SIZE);
  400 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  401 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  402 + NET2BIG_NOR_BOOT_BASE,
  403 + NET2BIG_NOR_BOOT_SIZE);
402 404 platform_device_register(&net2big_nor_flash);
403 405  
404 406 platform_device_register(&net2big_gpio_buttons);
arch/arm/mach-orion5x/pci.c
... ... @@ -157,11 +157,10 @@
157 157 if (dev == MV88F5181_DEV_ID || dev == MV88F5182_DEV_ID) {
158 158 printk(KERN_NOTICE "Applying Orion-1/Orion-NAS PCIe config "
159 159 "read transaction workaround\n");
160   - mvebu_mbus_add_window_remap_flags("pcie0.0",
161   - ORION5X_PCIE_WA_PHYS_BASE,
162   - ORION5X_PCIE_WA_SIZE,
163   - MVEBU_MBUS_NO_REMAP,
164   - MVEBU_MBUS_PCI_WA);
  160 + mvebu_mbus_add_window_by_id(ORION_MBUS_PCIE_WA_TARGET,
  161 + ORION_MBUS_PCIE_WA_ATTR,
  162 + ORION5X_PCIE_WA_PHYS_BASE,
  163 + ORION5X_PCIE_WA_SIZE);
165 164 pcie_ops.read = pcie_rd_conf_wa;
166 165 }
167 166  
arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
... ... @@ -123,8 +123,10 @@
123 123 orion5x_eth_switch_init(&rd88f5181l_fxo_switch_plat_data, NO_IRQ);
124 124 orion5x_uart0_init();
125 125  
126   - mvebu_mbus_add_window("devbus-boot", RD88F5181L_FXO_NOR_BOOT_BASE,
127   - RD88F5181L_FXO_NOR_BOOT_SIZE);
  126 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  127 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  128 + RD88F5181L_FXO_NOR_BOOT_BASE,
  129 + RD88F5181L_FXO_NOR_BOOT_SIZE);
128 130 platform_device_register(&rd88f5181l_fxo_nor_boot_flash);
129 131 }
130 132  
arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
... ... @@ -130,8 +130,10 @@
130 130 orion5x_i2c_init();
131 131 orion5x_uart0_init();
132 132  
133   - mvebu_mbus_add_window("devbus-boot", RD88F5181L_GE_NOR_BOOT_BASE,
134   - RD88F5181L_GE_NOR_BOOT_SIZE);
  133 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  134 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  135 + RD88F5181L_GE_NOR_BOOT_BASE,
  136 + RD88F5181L_GE_NOR_BOOT_SIZE);
135 137 platform_device_register(&rd88f5181l_ge_nor_boot_flash);
136 138  
137 139 i2c_register_board_info(0, &rd88f5181l_ge_i2c_rtc, 1);
arch/arm/mach-orion5x/rd88f5182-setup.c
... ... @@ -264,11 +264,14 @@
264 264 orion5x_uart0_init();
265 265 orion5x_xor_init();
266 266  
267   - mvebu_mbus_add_window("devbus-boot", RD88F5182_NOR_BOOT_BASE,
268   - RD88F5182_NOR_BOOT_SIZE);
269   -
270   - mvebu_mbus_add_window("devbus-cs1", RD88F5182_NOR_BASE,
271   - RD88F5182_NOR_SIZE);
  267 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  268 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  269 + RD88F5182_NOR_BOOT_BASE,
  270 + RD88F5182_NOR_BOOT_SIZE);
  271 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_TARGET(1),
  272 + ORION_MBUS_DEVBUS_ATTR(1),
  273 + RD88F5182_NOR_BASE,
  274 + RD88F5182_NOR_SIZE);
272 275 platform_device_register(&rd88f5182_nor_flash);
273 276 platform_device_register(&rd88f5182_gpio_leds);
274 277  
arch/arm/mach-orion5x/terastation_pro2-setup.c
... ... @@ -329,8 +329,10 @@
329 329 /*
330 330 * Configure peripherals.
331 331 */
332   - mvebu_mbus_add_window("devbus-boot", TSP2_NOR_BOOT_BASE,
333   - TSP2_NOR_BOOT_SIZE);
  332 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  333 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  334 + TSP2_NOR_BOOT_BASE,
  335 + TSP2_NOR_BOOT_SIZE);
334 336 platform_device_register(&tsp2_nor_flash);
335 337  
336 338 orion5x_ehci0_init();
arch/arm/mach-orion5x/ts209-setup.c
... ... @@ -286,8 +286,10 @@
286 286 /*
287 287 * Configure peripherals.
288 288 */
289   - mvebu_mbus_add_window("devbus-boot", QNAP_TS209_NOR_BOOT_BASE,
290   - QNAP_TS209_NOR_BOOT_SIZE);
  289 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  290 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  291 + QNAP_TS209_NOR_BOOT_BASE,
  292 + QNAP_TS209_NOR_BOOT_SIZE);
291 293 platform_device_register(&qnap_ts209_nor_flash);
292 294  
293 295 orion5x_ehci0_init();
arch/arm/mach-orion5x/ts409-setup.c
... ... @@ -277,8 +277,10 @@
277 277 /*
278 278 * Configure peripherals.
279 279 */
280   - mvebu_mbus_add_window("devbus-boot", QNAP_TS409_NOR_BOOT_BASE,
281   - QNAP_TS409_NOR_BOOT_SIZE);
  280 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  281 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  282 + QNAP_TS409_NOR_BOOT_BASE,
  283 + QNAP_TS409_NOR_BOOT_SIZE);
282 284 platform_device_register(&qnap_ts409_nor_flash);
283 285  
284 286 orion5x_ehci0_init();
arch/arm/mach-orion5x/wnr854t-setup.c
... ... @@ -127,8 +127,10 @@
127 127 orion5x_eth_switch_init(&wnr854t_switch_plat_data, NO_IRQ);
128 128 orion5x_uart0_init();
129 129  
130   - mvebu_mbus_add_window("devbus-boot", WNR854T_NOR_BOOT_BASE,
131   - WNR854T_NOR_BOOT_SIZE);
  130 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  131 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  132 + WNR854T_NOR_BOOT_BASE,
  133 + WNR854T_NOR_BOOT_SIZE);
132 134 platform_device_register(&wnr854t_nor_flash);
133 135 }
134 136  
arch/arm/mach-orion5x/wrt350n-v2-setup.c
... ... @@ -213,8 +213,10 @@
213 213 orion5x_eth_switch_init(&wrt350n_v2_switch_plat_data, NO_IRQ);
214 214 orion5x_uart0_init();
215 215  
216   - mvebu_mbus_add_window("devbus-boot", WRT350N_V2_NOR_BOOT_BASE,
217   - WRT350N_V2_NOR_BOOT_SIZE);
  216 + mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
  217 + ORION_MBUS_DEVBUS_BOOT_ATTR,
  218 + WRT350N_V2_NOR_BOOT_BASE,
  219 + WRT350N_V2_NOR_BOOT_SIZE);
218 220 platform_device_register(&wrt350n_v2_nor_flash);
219 221 platform_device_register(&wrt350n_v2_leds);
220 222 platform_device_register(&wrt350n_v2_button_device);