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Commit 4e8e1bca6e2584f2b29744f4cfdbb9bbf151d177

Authored by Don Skidmore 2013-07-31 10:17:40 +0800

Committed by Jeff Kirsher 2013-07-31 08:35:21 +0800

Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch

ixgbe: add new media type.

This patch adds support for a new media type fiber_fixed. This is useful
to avoid all the SFP+ hot plug support path on devices who's fix fiber need
not worry about such things. This patch is needed for a following patch
that adds support for "fiber_fixed" devices.

v2: cleaned up logging message based on feedback from David Miller

Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

Showing 4 changed files with 95 additions and 7 deletions Inline Diff

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c

Diff comments View file @ 4e8e1bc

 /*******************************************************************************
   Intel 10 Gigabit PCI Express Linux driver
   Copyright(c) 1999 - 2013 Intel Corporation.
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
   version 2, as published by the Free Software Foundation.
   This program is distributed in the hope it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
   You should have received a copy of the GNU General Public License along with
   this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   The full GNU General Public License is included in this distribution in
   the file called "COPYING".
   Contact Information:
   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *******************************************************************************/
 #include <linux/pci.h>
 #include <linux/delay.h>
 #include <linux/sched.h>
 #include "ixgbe.h"
 #include "ixgbe_phy.h"
 #include "ixgbe_mbx.h"
 #define IXGBE_82599_MAX_TX_QUEUES 128
 #define IXGBE_82599_MAX_RX_QUEUES 128
 #define IXGBE_82599_RAR_ENTRIES   128
 #define IXGBE_82599_MC_TBL_SIZE   128
 #define IXGBE_82599_VFT_TBL_SIZE  128
 #define IXGBE_82599_RX_PB_SIZE	  512
 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
 						 ixgbe_link_speed speed,
 						 bool autoneg_wait_to_complete);
 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
                                            ixgbe_link_speed speed,
                                            bool autoneg_wait_to_complete);
 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
 				      bool autoneg_wait_to_complete);
 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
                                ixgbe_link_speed speed,
                                bool autoneg_wait_to_complete);
 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
                                          ixgbe_link_speed speed,
                                          bool autoneg_wait_to_complete);
 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
 static bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
 {
 	u32 fwsm, manc, factps;
 	fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
 	if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
 		return false;
 	manc = IXGBE_READ_REG(hw, IXGBE_MANC);
 	if (!(manc & IXGBE_MANC_RCV_TCO_EN))
 		return false;
 	factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
 	if (factps & IXGBE_FACTPS_MNGCG)
 		return false;
 	return true;
 }
 static void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	/* enable the laser control functions for SFP+ fiber
 	 * and MNG not enabled
 	 */
 	if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
 	    !hw->mng_fw_enabled) {
 		mac->ops.disable_tx_laser =
 		                       &ixgbe_disable_tx_laser_multispeed_fiber;
 		mac->ops.enable_tx_laser =
 		                        &ixgbe_enable_tx_laser_multispeed_fiber;
 		mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
 	} else {
 		mac->ops.disable_tx_laser = NULL;
 		mac->ops.enable_tx_laser = NULL;
 		mac->ops.flap_tx_laser = NULL;
 	}
 	if (hw->phy.multispeed_fiber) {
 		/* Set up dual speed SFP+ support */
 		mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
 	} else {
 		if ((mac->ops.get_media_type(hw) ==
 		     ixgbe_media_type_backplane) &&
 		    (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
 		     hw->phy.smart_speed == ixgbe_smart_speed_on) &&
 		     !ixgbe_verify_lesm_fw_enabled_82599(hw))
 			mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
 		else
 			mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
 	}
 }
 static s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
 {
 	s32 ret_val = 0;
 	u16 list_offset, data_offset, data_value;
 	bool got_lock = false;
 	if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
 		ixgbe_init_mac_link_ops_82599(hw);
 		hw->phy.ops.reset = NULL;
 		ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 		                                              &data_offset);
 		if (ret_val != 0)
 			goto setup_sfp_out;
 		/* PHY config will finish before releasing the semaphore */
 		ret_val = hw->mac.ops.acquire_swfw_sync(hw,
 		                                        IXGBE_GSSR_MAC_CSR_SM);
 		if (ret_val != 0) {
 			ret_val = IXGBE_ERR_SWFW_SYNC;
 			goto setup_sfp_out;
 		}
 		hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 		while (data_value != 0xffff) {
 			IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
 			IXGBE_WRITE_FLUSH(hw);
 			hw->eeprom.ops.read(hw, ++data_offset, &data_value);
 		}
 		/* Release the semaphore */
 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
 		/*
 		 * Delay obtaining semaphore again to allow FW access,
 		 * semaphore_delay is in ms usleep_range needs us.
 		 */
 		usleep_range(hw->eeprom.semaphore_delay * 1000,
 			     hw->eeprom.semaphore_delay * 2000);
 		/* Need SW/FW semaphore around AUTOC writes if LESM on,
 		 * likewise reset_pipeline requires lock as it also writes
 		 * AUTOC.
 		 */
 		if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
 			ret_val = hw->mac.ops.acquire_swfw_sync(hw,
 							IXGBE_GSSR_MAC_CSR_SM);
 			if (ret_val)
 				goto setup_sfp_out;
 			got_lock = true;
 		}
 		/* Restart DSP and set SFI mode */
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((hw->mac.orig_autoc) |
 				IXGBE_AUTOC_LMS_10G_SERIAL));
 		hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 		ret_val = ixgbe_reset_pipeline_82599(hw);
 		if (got_lock) {
 			hw->mac.ops.release_swfw_sync(hw,
 						      IXGBE_GSSR_MAC_CSR_SM);
 			got_lock = false;
 		}
 		if (ret_val) {
 			hw_dbg(hw, " sfp module setup not complete\n");
 			ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
 			goto setup_sfp_out;
 		}
 	}
 setup_sfp_out:
 	return ret_val;
 }
 static s32 ixgbe_get_invariants_82599(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	ixgbe_init_mac_link_ops_82599(hw);
 	mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
 	mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
 	mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
 	mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
 	mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
 	mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
 	return 0;
 }
 /**
  *  ixgbe_init_phy_ops_82599 - PHY/SFP specific init
  *  @hw: pointer to hardware structure
  *
  *  Initialize any function pointers that were not able to be
  *  set during get_invariants because the PHY/SFP type was
  *  not known.  Perform the SFP init if necessary.
  *
  **/
 static s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
 {
 	struct ixgbe_mac_info *mac = &hw->mac;
 	struct ixgbe_phy_info *phy = &hw->phy;
 	s32 ret_val = 0;
 	/* Identify the PHY or SFP module */
 	ret_val = phy->ops.identify(hw);
 	/* Setup function pointers based on detected SFP module and speeds */
 	ixgbe_init_mac_link_ops_82599(hw);
 	/* If copper media, overwrite with copper function pointers */
 	if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
 		mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
 		mac->ops.get_link_capabilities =
 			&ixgbe_get_copper_link_capabilities_generic;
 	}
 	/* Set necessary function pointers based on phy type */
 	switch (hw->phy.type) {
 	case ixgbe_phy_tn:
 		phy->ops.check_link = &ixgbe_check_phy_link_tnx;
 		phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
 		phy->ops.get_firmware_version =
 		             &ixgbe_get_phy_firmware_version_tnx;
 		break;
 	default:
 		break;
 	}
 	return ret_val;
 }
 /**
  *  ixgbe_get_link_capabilities_82599 - Determines link capabilities
  *  @hw: pointer to hardware structure
  *  @speed: pointer to link speed
  *  @autoneg: true when autoneg or autotry is enabled
  *
  *  Determines the link capabilities by reading the AUTOC register.
  **/
 static s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
                                              ixgbe_link_speed *speed,
 					     bool *autoneg)
 {
 	s32 status = 0;
 	u32 autoc = 0;
 	/* Determine 1G link capabilities off of SFP+ type */
 	if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
 	    hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
 		*autoneg = true;
 		goto out;
 	}
 	/*
 	 * Determine link capabilities based on the stored value of AUTOC,
 	 * which represents EEPROM defaults.  If AUTOC value has not been
 	 * stored, use the current register value.
 	 */
 	if (hw->mac.orig_link_settings_stored)
 		autoc = hw->mac.orig_autoc;
 	else
 		autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 	case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
 		*autoneg = false;
 		break;
 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
 		*autoneg = false;
 		break;
 	case IXGBE_AUTOC_LMS_1G_AN:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
 		*autoneg = true;
 		break;
 	case IXGBE_AUTOC_LMS_10G_SERIAL:
 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
 		*autoneg = false;
 		break;
 	case IXGBE_AUTOC_LMS_KX4_KX_KR:
 	case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
 		*speed = IXGBE_LINK_SPEED_UNKNOWN;
 		if (autoc & IXGBE_AUTOC_KR_SUPP)
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX4_SUPP)
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX_SUPP)
 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
 		*autoneg = true;
 		break;
 	case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
 		*speed = IXGBE_LINK_SPEED_100_FULL;
 		if (autoc & IXGBE_AUTOC_KR_SUPP)
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX4_SUPP)
 			*speed |= IXGBE_LINK_SPEED_10GB_FULL;
 		if (autoc & IXGBE_AUTOC_KX_SUPP)
 			*speed |= IXGBE_LINK_SPEED_1GB_FULL;
 		*autoneg = true;
 		break;
 	case IXGBE_AUTOC_LMS_SGMII_1G_100M:
 		*speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
 		*autoneg = false;
 		break;
 	default:
 		status = IXGBE_ERR_LINK_SETUP;
 		goto out;
 		break;
 	}
 	if (hw->phy.multispeed_fiber) {
 		*speed |= IXGBE_LINK_SPEED_10GB_FULL |
 		          IXGBE_LINK_SPEED_1GB_FULL;
 		*autoneg = true;
 	}
 out:
 	return status;
 }
 /**
  *  ixgbe_get_media_type_82599 - Get media type
  *  @hw: pointer to hardware structure
  *
  *  Returns the media type (fiber, copper, backplane)
  **/
 static enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
 {
 	enum ixgbe_media_type media_type;
 	/* Detect if there is a copper PHY attached. */
 	switch (hw->phy.type) {
 	case ixgbe_phy_cu_unknown:
 	case ixgbe_phy_tn:
 		media_type = ixgbe_media_type_copper;
 		goto out;
 	default:
 		break;
 	}
 	switch (hw->device_id) {
 	case IXGBE_DEV_ID_82599_KX4:
 	case IXGBE_DEV_ID_82599_KX4_MEZZ:
 	case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
 	case IXGBE_DEV_ID_82599_KR:
 	case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
 	case IXGBE_DEV_ID_82599_XAUI_LOM:
 		/* Default device ID is mezzanine card KX/KX4 */
 		media_type = ixgbe_media_type_backplane;
 		break;
 	case IXGBE_DEV_ID_82599_SFP:
 	case IXGBE_DEV_ID_82599_SFP_FCOE:
 	case IXGBE_DEV_ID_82599_SFP_EM:
 	case IXGBE_DEV_ID_82599_SFP_SF2:
 	case IXGBE_DEV_ID_82599_SFP_SF_QP:
 	case IXGBE_DEV_ID_82599EN_SFP:
 		media_type = ixgbe_media_type_fiber;
 		break;
 	case IXGBE_DEV_ID_82599_CX4:
 		media_type = ixgbe_media_type_cx4;
 		break;
 	case IXGBE_DEV_ID_82599_T3_LOM:
 		media_type = ixgbe_media_type_copper;
 		break;
 	case IXGBE_DEV_ID_82599_LS:
 		media_type = ixgbe_media_type_fiber_lco;
 		break;
 	default:
 		media_type = ixgbe_media_type_unknown;
 		break;
 	}
 out:
 	return media_type;
 }
 /**
  *  ixgbe_start_mac_link_82599 - Setup MAC link settings
  *  @hw: pointer to hardware structure
  *  @autoneg_wait_to_complete: true when waiting for completion is needed
  *
  *  Configures link settings based on values in the ixgbe_hw struct.
  *  Restarts the link.  Performs autonegotiation if needed.
  **/
 static s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
                                bool autoneg_wait_to_complete)
 {
 	u32 autoc_reg;
 	u32 links_reg;
 	u32 i;
 	s32 status = 0;
 	bool got_lock = false;
 	if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
 		status = hw->mac.ops.acquire_swfw_sync(hw,
 						IXGBE_GSSR_MAC_CSR_SM);
 		if (status)
 			goto out;
 		got_lock = true;
 	}
 	/* Restart link */
 	ixgbe_reset_pipeline_82599(hw);
 	if (got_lock)
 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
 	/* Only poll for autoneg to complete if specified to do so */
 	if (autoneg_wait_to_complete) {
 		autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 		if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 		     IXGBE_AUTOC_LMS_KX4_KX_KR ||
 		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 		     IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 		    (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
 		     IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 			links_reg = 0; /* Just in case Autoneg time = 0 */
 			for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 				links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 				if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 					break;
 				msleep(100);
 			}
 			if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 				status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 				hw_dbg(hw, "Autoneg did not complete.\n");
 			}
 		}
 	}
 	/* Add delay to filter out noises during initial link setup */
 	msleep(50);
 out:
 	return status;
 }
 /**
  *  ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
  *  @hw: pointer to hardware structure
  *
  *  The base drivers may require better control over SFP+ module
  *  PHY states.  This includes selectively shutting down the Tx
  *  laser on the PHY, effectively halting physical link.
  **/
 static void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
 {
 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 	/* Disable tx laser; allow 100us to go dark per spec */
 	esdp_reg |= IXGBE_ESDP_SDP3;
 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 	IXGBE_WRITE_FLUSH(hw);
 	udelay(100);
 }
 /**
  *  ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
  *  @hw: pointer to hardware structure
  *
  *  The base drivers may require better control over SFP+ module
  *  PHY states.  This includes selectively turning on the Tx
  *  laser on the PHY, effectively starting physical link.
  **/
 static void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
 {
 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 	/* Enable tx laser; allow 100ms to light up */
 	esdp_reg &= ~IXGBE_ESDP_SDP3;
 	IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
 	IXGBE_WRITE_FLUSH(hw);
 	msleep(100);
 }
 /**
  *  ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
  *  @hw: pointer to hardware structure
  *
  *  When the driver changes the link speeds that it can support,
  *  it sets autotry_restart to true to indicate that we need to
  *  initiate a new autotry session with the link partner.  To do
  *  so, we set the speed then disable and re-enable the tx laser, to
  *  alert the link partner that it also needs to restart autotry on its
  *  end.  This is consistent with true clause 37 autoneg, which also
  *  involves a loss of signal.
  **/
 static void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
 {
 	if (hw->mac.autotry_restart) {
 		ixgbe_disable_tx_laser_multispeed_fiber(hw);
 		ixgbe_enable_tx_laser_multispeed_fiber(hw);
 		hw->mac.autotry_restart = false;
 	}
 }
 /**
+ *  ixgbe_set_fiber_fixed_speed - Set module link speed for fixed fiber
+ *  @hw: pointer to hardware structure
+ *  @speed: link speed to set
+ *
+ *  We set the module speed differently for fixed fiber.  For other
+ *  multi-speed devices we don't have an error value so here if we
+ *  detect an error we just log it and exit.
+ */
+static void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw,
+					ixgbe_link_speed speed)
+{
+	s32 status;
+	u8 rs, eeprom_data;
+	switch (speed) {
+	case IXGBE_LINK_SPEED_10GB_FULL:
+		/* one bit mask same as setting on */
+		rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
+		break;
+	case IXGBE_LINK_SPEED_1GB_FULL:
+		rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
+		break;
+	default:
+		hw_dbg(hw, "Invalid fixed module speed\n");
+		return;
+	}
+	/* Set RS0 */
+	status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
+					   IXGBE_I2C_EEPROM_DEV_ADDR2,
+					   &eeprom_data);
+	if (status) {
+		hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
+		goto out;
+	}
+	eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
+	status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
+					    IXGBE_I2C_EEPROM_DEV_ADDR2,
+					    eeprom_data);
+	if (status) {
+		hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
+		goto out;
+	}
+	/* Set RS1 */
+	status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
+					   IXGBE_I2C_EEPROM_DEV_ADDR2,
+					   &eeprom_data);
+	if (status) {
+		hw_dbg(hw, "Failed to read Rx Rate Select RS1\n");
+		goto out;
+	}
+	eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
+	status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
+					    IXGBE_I2C_EEPROM_DEV_ADDR2,
+					    eeprom_data);
+	if (status) {
+		hw_dbg(hw, "Failed to write Rx Rate Select RS1\n");
+		goto out;
+	}
+out:
+	return;
+}
+/**
  *  ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
  *  @hw: pointer to hardware structure
  *  @speed: new link speed
  *  @autoneg_wait_to_complete: true when waiting for completion is needed
  *
  *  Set the link speed in the AUTOC register and restarts link.
  **/
 static s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
                                           ixgbe_link_speed speed,
                                           bool autoneg_wait_to_complete)
 {
 	s32 status = 0;
 	ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 	ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 	u32 speedcnt = 0;
 	u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
 	u32 i = 0;
 	bool link_up = false;
 	bool autoneg = false;
 	/* Mask off requested but non-supported speeds */
 	status = hw->mac.ops.get_link_capabilities(hw, &link_speed,
 						   &autoneg);
 	if (status != 0)
 		return status;
 	speed &= link_speed;
 	/*
 	 * Try each speed one by one, highest priority first.  We do this in
 	 * software because 10gb fiber doesn't support speed autonegotiation.
 	 */
 	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 		speedcnt++;
 		highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
 		/* If we already have link at this speed, just jump out */
 		status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
 						false);
 		if (status != 0)
 			return status;
 		if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
 			goto out;
 		/* Set the module link speed */
-		esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
+		if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
-		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
+			ixgbe_set_fiber_fixed_speed(hw,
-		IXGBE_WRITE_FLUSH(hw);
+					IXGBE_LINK_SPEED_10GB_FULL);
+		} else {
+			esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
+			IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
+			IXGBE_WRITE_FLUSH(hw);
+		}
 		/* Allow module to change analog characteristics (1G->10G) */
 		msleep(40);
 		status = ixgbe_setup_mac_link_82599(hw,
 						    IXGBE_LINK_SPEED_10GB_FULL,
 						    autoneg_wait_to_complete);
 		if (status != 0)
 			return status;
 		/* Flap the tx laser if it has not already been done */
 		if (hw->mac.ops.flap_tx_laser)
 			hw->mac.ops.flap_tx_laser(hw);
 		/*
 		 * Wait for the controller to acquire link.  Per IEEE 802.3ap,
 		 * Section 73.10.2, we may have to wait up to 500ms if KR is
 		 * attempted.  82599 uses the same timing for 10g SFI.
 		 */
 		for (i = 0; i < 5; i++) {
 			/* Wait for the link partner to also set speed */
 			msleep(100);
 			/* If we have link, just jump out */
 			status = hw->mac.ops.check_link(hw, &link_speed,
 							&link_up, false);
 			if (status != 0)
 				return status;
 			if (link_up)
 				goto out;
 		}
 	}
 	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 		speedcnt++;
 		if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
 			highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
 		/* If we already have link at this speed, just jump out */
 		status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
 						false);
 		if (status != 0)
 			return status;
 		if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
 			goto out;
 		/* Set the module link speed */
-		esdp_reg &= ~IXGBE_ESDP_SDP5;
+		if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
-		esdp_reg |= IXGBE_ESDP_SDP5_DIR;
+			ixgbe_set_fiber_fixed_speed(hw,
-		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
+						IXGBE_LINK_SPEED_1GB_FULL);
-		IXGBE_WRITE_FLUSH(hw);
+		} else {
+			esdp_reg &= ~IXGBE_ESDP_SDP5;
+			esdp_reg |= IXGBE_ESDP_SDP5_DIR;
+			IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
+			IXGBE_WRITE_FLUSH(hw);
+		}
 		/* Allow module to change analog characteristics (10G->1G) */
 		msleep(40);
 		status = ixgbe_setup_mac_link_82599(hw,
 						    IXGBE_LINK_SPEED_1GB_FULL,
 						    autoneg_wait_to_complete);
 		if (status != 0)
 			return status;
 		/* Flap the tx laser if it has not already been done */
 		if (hw->mac.ops.flap_tx_laser)
 			hw->mac.ops.flap_tx_laser(hw);
 		/* Wait for the link partner to also set speed */
 		msleep(100);
 		/* If we have link, just jump out */
 		status = hw->mac.ops.check_link(hw, &link_speed, &link_up,
 						false);
 		if (status != 0)
 			return status;
 		if (link_up)
 			goto out;
 	}
 	/*
 	 * We didn't get link.  Configure back to the highest speed we tried,
 	 * (if there was more than one).  We call ourselves back with just the
 	 * single highest speed that the user requested.
 	 */
 	if (speedcnt > 1)
 		status = ixgbe_setup_mac_link_multispeed_fiber(hw,
 		                                               highest_link_speed,
 		                                               autoneg_wait_to_complete);
 out:
 	/* Set autoneg_advertised value based on input link speed */
 	hw->phy.autoneg_advertised = 0;
 	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 	return status;
 }
 /**
  *  ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
  *  @hw: pointer to hardware structure
  *  @speed: new link speed
  *  @autoneg_wait_to_complete: true when waiting for completion is needed
  *
  *  Implements the Intel SmartSpeed algorithm.
  **/
 static s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
 				     ixgbe_link_speed speed,
 				     bool autoneg_wait_to_complete)
 {
 	s32 status = 0;
 	ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
 	s32 i, j;
 	bool link_up = false;
 	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	 /* Set autoneg_advertised value based on input link speed */
 	hw->phy.autoneg_advertised = 0;
 	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 	if (speed & IXGBE_LINK_SPEED_100_FULL)
 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 	/*
 	 * Implement Intel SmartSpeed algorithm.  SmartSpeed will reduce the
 	 * autoneg advertisement if link is unable to be established at the
 	 * highest negotiated rate.  This can sometimes happen due to integrity
 	 * issues with the physical media connection.
 	 */
 	/* First, try to get link with full advertisement */
 	hw->phy.smart_speed_active = false;
 	for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
 		status = ixgbe_setup_mac_link_82599(hw, speed,
 						    autoneg_wait_to_complete);
 		if (status != 0)
 			goto out;
 		/*
 		 * Wait for the controller to acquire link.  Per IEEE 802.3ap,
 		 * Section 73.10.2, we may have to wait up to 500ms if KR is
 		 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
 		 * Table 9 in the AN MAS.
 		 */
 		for (i = 0; i < 5; i++) {
 			mdelay(100);
 			/* If we have link, just jump out */
 			status = hw->mac.ops.check_link(hw, &link_speed,
 							&link_up, false);
 			if (status != 0)
 				goto out;
 			if (link_up)
 				goto out;
 		}
 	}
 	/*
 	 * We didn't get link.  If we advertised KR plus one of KX4/KX
 	 * (or BX4/BX), then disable KR and try again.
 	 */
 	if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
 	    ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
 		goto out;
 	/* Turn SmartSpeed on to disable KR support */
 	hw->phy.smart_speed_active = true;
 	status = ixgbe_setup_mac_link_82599(hw, speed,
 					    autoneg_wait_to_complete);
 	if (status != 0)
 		goto out;
 	/*
 	 * Wait for the controller to acquire link.  600ms will allow for
 	 * the AN link_fail_inhibit_timer as well for multiple cycles of
 	 * parallel detect, both 10g and 1g. This allows for the maximum
 	 * connect attempts as defined in the AN MAS table 73-7.
 	 */
 	for (i = 0; i < 6; i++) {
 		mdelay(100);
 		/* If we have link, just jump out */
 		status = hw->mac.ops.check_link(hw, &link_speed,
 						&link_up, false);
 		if (status != 0)
 			goto out;
 		if (link_up)
 			goto out;
 	}
 	/* We didn't get link.  Turn SmartSpeed back off. */
 	hw->phy.smart_speed_active = false;
 	status = ixgbe_setup_mac_link_82599(hw, speed,
 					    autoneg_wait_to_complete);
 out:
 	if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
 		hw_dbg(hw, "Smartspeed has downgraded the link speed from "
 		       "the maximum advertised\n");
 	return status;
 }
 /**
  *  ixgbe_setup_mac_link_82599 - Set MAC link speed
  *  @hw: pointer to hardware structure
  *  @speed: new link speed
  *  @autoneg_wait_to_complete: true when waiting for completion is needed
  *
  *  Set the link speed in the AUTOC register and restarts link.
  **/
 static s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
 				      ixgbe_link_speed speed,
 				      bool autoneg_wait_to_complete)
 {
 	s32 status = 0;
 	u32 autoc, pma_pmd_1g, link_mode, start_autoc;
 	u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 	u32 orig_autoc = 0;
 	u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
 	u32 links_reg;
 	u32 i;
 	ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
 	bool got_lock = false;
 	bool autoneg = false;
 	/* Check to see if speed passed in is supported. */
 	status = hw->mac.ops.get_link_capabilities(hw, &link_capabilities,
 						   &autoneg);
 	if (status != 0)
 		goto out;
 	speed &= link_capabilities;
 	if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
 		status = IXGBE_ERR_LINK_SETUP;
 		goto out;
 	}
 	/* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
 	if (hw->mac.orig_link_settings_stored)
 		autoc = hw->mac.orig_autoc;
 	else
 		autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	orig_autoc = autoc;
 	start_autoc = hw->mac.cached_autoc;
 	link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
 	pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
 	if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 	    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 	    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 		/* Set KX4/KX/KR support according to speed requested */
 		autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
 		if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 			if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
 				autoc |= IXGBE_AUTOC_KX4_SUPP;
 			if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
 			    (hw->phy.smart_speed_active == false))
 				autoc |= IXGBE_AUTOC_KR_SUPP;
 		}
 		if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 			autoc |= IXGBE_AUTOC_KX_SUPP;
 	} else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
 	           (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
 	            link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
 		/* Switch from 1G SFI to 10G SFI if requested */
 		if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
 		    (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
 			autoc &= ~IXGBE_AUTOC_LMS_MASK;
 			autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
 		}
 	} else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
 	           (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
 		/* Switch from 10G SFI to 1G SFI if requested */
 		if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
 		    (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
 			autoc &= ~IXGBE_AUTOC_LMS_MASK;
 			if (autoneg)
 				autoc |= IXGBE_AUTOC_LMS_1G_AN;
 			else
 				autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
 		}
 	}
 	if (autoc != start_autoc) {
 		/* Need SW/FW semaphore around AUTOC writes if LESM is on,
 		 * likewise reset_pipeline requires us to hold this lock as
 		 * it also writes to AUTOC.
 		 */
 		if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
 			status = hw->mac.ops.acquire_swfw_sync(hw,
 							IXGBE_GSSR_MAC_CSR_SM);
 			if (status != 0)
 				goto out;
 			got_lock = true;
 		}
 		/* Restart link */
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
 		hw->mac.cached_autoc = autoc;
 		ixgbe_reset_pipeline_82599(hw);
 		if (got_lock)
 			hw->mac.ops.release_swfw_sync(hw,
 						      IXGBE_GSSR_MAC_CSR_SM);
 		/* Only poll for autoneg to complete if specified to do so */
 		if (autoneg_wait_to_complete) {
 			if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
 			    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
 			    link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
 				links_reg = 0; /*Just in case Autoneg time=0*/
 				for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
 					links_reg =
 					       IXGBE_READ_REG(hw, IXGBE_LINKS);
 					if (links_reg & IXGBE_LINKS_KX_AN_COMP)
 						break;
 					msleep(100);
 				}
 				if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
 					status =
 					        IXGBE_ERR_AUTONEG_NOT_COMPLETE;
 					hw_dbg(hw, "Autoneg did not "
 					       "complete.\n");
 				}
 			}
 		}
 		/* Add delay to filter out noises during initial link setup */
 		msleep(50);
 	}
 out:
 	return status;
 }
 /**
  *  ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
  *  @hw: pointer to hardware structure
  *  @speed: new link speed
  *  @autoneg_wait_to_complete: true if waiting is needed to complete
  *
  *  Restarts link on PHY and MAC based on settings passed in.
  **/
 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
                                          ixgbe_link_speed speed,
                                          bool autoneg_wait_to_complete)
 {
 	s32 status;
 	/* Setup the PHY according to input speed */
 	status = hw->phy.ops.setup_link_speed(hw, speed,
 	                                      autoneg_wait_to_complete);
 	/* Set up MAC */
 	ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
 	return status;
 }
 /**
  *  ixgbe_reset_hw_82599 - Perform hardware reset
  *  @hw: pointer to hardware structure
  *
  *  Resets the hardware by resetting the transmit and receive units, masks
  *  and clears all interrupts, perform a PHY reset, and perform a link (MAC)
  *  reset.
  **/
 static s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
 {
 	ixgbe_link_speed link_speed;
 	s32 status;
 	u32 ctrl, i, autoc2;
 	u32 curr_lms;
 	bool link_up = false;
 	/* Call adapter stop to disable tx/rx and clear interrupts */
 	status = hw->mac.ops.stop_adapter(hw);
 	if (status != 0)
 		goto reset_hw_out;
 	/* flush pending Tx transactions */
 	ixgbe_clear_tx_pending(hw);
 	/* PHY ops must be identified and initialized prior to reset */
 	/* Identify PHY and related function pointers */
 	status = hw->phy.ops.init(hw);
 	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 		goto reset_hw_out;
 	/* Setup SFP module if there is one present. */
 	if (hw->phy.sfp_setup_needed) {
 		status = hw->mac.ops.setup_sfp(hw);
 		hw->phy.sfp_setup_needed = false;
 	}
 	if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
 		goto reset_hw_out;
 	/* Reset PHY */
 	if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
 		hw->phy.ops.reset(hw);
 	/* remember AUTOC from before we reset */
 	if (hw->mac.cached_autoc)
 		curr_lms = hw->mac.cached_autoc & IXGBE_AUTOC_LMS_MASK;
 	else
 		curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) &
 			   IXGBE_AUTOC_LMS_MASK;
 mac_reset_top:
 	/*
 	 * Issue global reset to the MAC. Needs to be SW reset if link is up.
 	 * If link reset is used when link is up, it might reset the PHY when
 	 * mng is using it.  If link is down or the flag to force full link
 	 * reset is set, then perform link reset.
 	 */
 	ctrl = IXGBE_CTRL_LNK_RST;
 	if (!hw->force_full_reset) {
 		hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
 		if (link_up)
 			ctrl = IXGBE_CTRL_RST;
 	}
 	ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
 	IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
 	IXGBE_WRITE_FLUSH(hw);
 	/* Poll for reset bit to self-clear indicating reset is complete */
 	for (i = 0; i < 10; i++) {
 		udelay(1);
 		ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
 		if (!(ctrl & IXGBE_CTRL_RST_MASK))
 			break;
 	}
 	if (ctrl & IXGBE_CTRL_RST_MASK) {
 		status = IXGBE_ERR_RESET_FAILED;
 		hw_dbg(hw, "Reset polling failed to complete.\n");
 	}
 	msleep(50);
 	/*
 	 * Double resets are required for recovery from certain error
 	 * conditions.  Between resets, it is necessary to stall to allow time
 	 * for any pending HW events to complete.
 	 */
 	if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
 		hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 		goto mac_reset_top;
 	}
 	/*
 	 * Store the original AUTOC/AUTOC2 values if they have not been
 	 * stored off yet.  Otherwise restore the stored original
 	 * values since the reset operation sets back to defaults.
 	 */
 	hw->mac.cached_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 	/* Enable link if disabled in NVM */
 	if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
 		autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
 		IXGBE_WRITE_FLUSH(hw);
 	}
 	if (hw->mac.orig_link_settings_stored == false) {
 		hw->mac.orig_autoc = hw->mac.cached_autoc;
 		hw->mac.orig_autoc2 = autoc2;
 		hw->mac.orig_link_settings_stored = true;
 	} else {
 		/* If MNG FW is running on a multi-speed device that
 		 * doesn't autoneg with out driver support we need to
 		 * leave LMS in the state it was before we MAC reset.
 		 * Likewise if we support WoL we don't want change the
 		 * LMS state either.
 		 */
 		if ((hw->phy.multispeed_fiber && hw->mng_fw_enabled) ||
 		    hw->wol_enabled)
 			hw->mac.orig_autoc =
 				(hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
 				curr_lms;
 		if (hw->mac.cached_autoc != hw->mac.orig_autoc) {
 			/* Need SW/FW semaphore around AUTOC writes if LESM is
 			 * on, likewise reset_pipeline requires us to hold
 			 * this lock as it also writes to AUTOC.
 			 */
 			bool got_lock = false;
 			if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
 				status = hw->mac.ops.acquire_swfw_sync(hw,
 							IXGBE_GSSR_MAC_CSR_SM);
 				if (status)
 					goto reset_hw_out;
 				got_lock = true;
 			}
 			IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
 			hw->mac.cached_autoc = hw->mac.orig_autoc;
 			ixgbe_reset_pipeline_82599(hw);
 			if (got_lock)
 				hw->mac.ops.release_swfw_sync(hw,
 							IXGBE_GSSR_MAC_CSR_SM);
 		}
 		if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
 		    (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
 			autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
 			autoc2 |= (hw->mac.orig_autoc2 &
 			           IXGBE_AUTOC2_UPPER_MASK);
 			IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
 		}
 	}
 	/* Store the permanent mac address */
 	hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
 	/*
 	 * Store MAC address from RAR0, clear receive address registers, and
 	 * clear the multicast table.  Also reset num_rar_entries to 128,
 	 * since we modify this value when programming the SAN MAC address.
 	 */
 	hw->mac.num_rar_entries = 128;
 	hw->mac.ops.init_rx_addrs(hw);
 	/* Store the permanent SAN mac address */
 	hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
 	/* Add the SAN MAC address to the RAR only if it's a valid address */
 	if (is_valid_ether_addr(hw->mac.san_addr)) {
 		hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
 		                    hw->mac.san_addr, 0, IXGBE_RAH_AV);
 		/* Save the SAN MAC RAR index */
 		hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
 		/* Reserve the last RAR for the SAN MAC address */
 		hw->mac.num_rar_entries--;
 	}
 	/* Store the alternative WWNN/WWPN prefix */
 	hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
 	                               &hw->mac.wwpn_prefix);
 reset_hw_out:
 	return status;
 }
 /**
  *  ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
  *  @hw: pointer to hardware structure
  **/
 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
 {
 	int i;
 	u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
 	fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
 	/*
 	 * Before starting reinitialization process,
 	 * FDIRCMD.CMD must be zero.
 	 */
 	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
 		if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
 		      IXGBE_FDIRCMD_CMD_MASK))
 			break;
 		udelay(10);
 	}
 	if (i >= IXGBE_FDIRCMD_CMD_POLL) {
 		hw_dbg(hw, "Flow Director previous command isn't complete, "
 		       "aborting table re-initialization.\n");
 		return IXGBE_ERR_FDIR_REINIT_FAILED;
 	}
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
 	IXGBE_WRITE_FLUSH(hw);
 	/*
 	 * 82599 adapters flow director init flow cannot be restarted,
 	 * Workaround 82599 silicon errata by performing the following steps
 	 * before re-writing the FDIRCTRL control register with the same value.
 	 * - write 1 to bit 8 of FDIRCMD register &
 	 * - write 0 to bit 8 of FDIRCMD register
 	 */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
 	                (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
 	                 IXGBE_FDIRCMD_CLEARHT));
 	IXGBE_WRITE_FLUSH(hw);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
 	                (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
 	                 ~IXGBE_FDIRCMD_CLEARHT));
 	IXGBE_WRITE_FLUSH(hw);
 	/*
 	 * Clear FDIR Hash register to clear any leftover hashes
 	 * waiting to be programmed.
 	 */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
 	IXGBE_WRITE_FLUSH(hw);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
 	IXGBE_WRITE_FLUSH(hw);
 	/* Poll init-done after we write FDIRCTRL register */
 	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
 		                   IXGBE_FDIRCTRL_INIT_DONE)
 			break;
 		usleep_range(1000, 2000);
 	}
 	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
 		hw_dbg(hw, "Flow Director Signature poll time exceeded!\n");
 		return IXGBE_ERR_FDIR_REINIT_FAILED;
 	}
 	/* Clear FDIR statistics registers (read to clear) */
 	IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
 	IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
 	IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
 	IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
 	IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
 	return 0;
 }
 /**
  *  ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
  *  @hw: pointer to hardware structure
  *  @fdirctrl: value to write to flow director control register
  **/
 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
 {
 	int i;
 	/* Prime the keys for hashing */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
 	/*
 	 * Poll init-done after we write the register.  Estimated times:
 	 *      10G: PBALLOC = 11b, timing is 60us
 	 *       1G: PBALLOC = 11b, timing is 600us
 	 *     100M: PBALLOC = 11b, timing is 6ms
 	 *
 	 *     Multiple these timings by 4 if under full Rx load
 	 *
 	 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
 	 * 1 msec per poll time.  If we're at line rate and drop to 100M, then
 	 * this might not finish in our poll time, but we can live with that
 	 * for now.
 	 */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
 	IXGBE_WRITE_FLUSH(hw);
 	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
 		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
 		                   IXGBE_FDIRCTRL_INIT_DONE)
 			break;
 		usleep_range(1000, 2000);
 	}
 	if (i >= IXGBE_FDIR_INIT_DONE_POLL)
 		hw_dbg(hw, "Flow Director poll time exceeded!\n");
 }
 /**
  *  ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
  *  @hw: pointer to hardware structure
  *  @fdirctrl: value to write to flow director control register, initially
  *             contains just the value of the Rx packet buffer allocation
  **/
 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
 {
 	/*
 	 * Continue setup of fdirctrl register bits:
 	 *  Move the flexible bytes to use the ethertype - shift 6 words
 	 *  Set the maximum length per hash bucket to 0xA filters
 	 *  Send interrupt when 64 filters are left
 	 */
 	fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
 		    (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
 		    (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
 	/* write hashes and fdirctrl register, poll for completion */
 	ixgbe_fdir_enable_82599(hw, fdirctrl);
 	return 0;
 }
 /**
  *  ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
  *  @hw: pointer to hardware structure
  *  @fdirctrl: value to write to flow director control register, initially
  *             contains just the value of the Rx packet buffer allocation
  **/
 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
 {
 	/*
 	 * Continue setup of fdirctrl register bits:
 	 *  Turn perfect match filtering on
 	 *  Report hash in RSS field of Rx wb descriptor
 	 *  Initialize the drop queue
 	 *  Move the flexible bytes to use the ethertype - shift 6 words
 	 *  Set the maximum length per hash bucket to 0xA filters
 	 *  Send interrupt when 64 (0x4 * 16) filters are left
 	 */
 	fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
 		    IXGBE_FDIRCTRL_REPORT_STATUS |
 		    (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
 		    (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
 		    (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
 		    (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
 	/* write hashes and fdirctrl register, poll for completion */
 	ixgbe_fdir_enable_82599(hw, fdirctrl);
 	return 0;
 }
 /*
  * These defines allow us to quickly generate all of the necessary instructions
  * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
  * for values 0 through 15
  */
 #define IXGBE_ATR_COMMON_HASH_KEY \
 		(IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
 do { \
 	u32 n = (_n); \
 	if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
 		common_hash ^= lo_hash_dword >> n; \
 	else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
 		bucket_hash ^= lo_hash_dword >> n; \
 	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
 		sig_hash ^= lo_hash_dword << (16 - n); \
 	if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
 		common_hash ^= hi_hash_dword >> n; \
 	else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
 		bucket_hash ^= hi_hash_dword >> n; \
 	else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
 		sig_hash ^= hi_hash_dword << (16 - n); \
 } while (0);
 /**
  *  ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
  *  @stream: input bitstream to compute the hash on
  *
  *  This function is almost identical to the function above but contains
  *  several optomizations such as unwinding all of the loops, letting the
  *  compiler work out all of the conditional ifs since the keys are static
  *  defines, and computing two keys at once since the hashed dword stream
  *  will be the same for both keys.
  **/
 static u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
 					    union ixgbe_atr_hash_dword common)
 {
 	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
 	u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
 	/* record the flow_vm_vlan bits as they are a key part to the hash */
 	flow_vm_vlan = ntohl(input.dword);
 	/* generate common hash dword */
 	hi_hash_dword = ntohl(common.dword);
 	/* low dword is word swapped version of common */
 	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 	/* apply flow ID/VM pool/VLAN ID bits to hash words */
 	hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 	/* Process bits 0 and 16 */
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
 	/*
 	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
 	 * delay this because bit 0 of the stream should not be processed
 	 * so we do not add the vlan until after bit 0 was processed
 	 */
 	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 	/* Process remaining 30 bit of the key */
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
 	IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
 	/* combine common_hash result with signature and bucket hashes */
 	bucket_hash ^= common_hash;
 	bucket_hash &= IXGBE_ATR_HASH_MASK;
 	sig_hash ^= common_hash << 16;
 	sig_hash &= IXGBE_ATR_HASH_MASK << 16;
 	/* return completed signature hash */
 	return sig_hash ^ bucket_hash;
 }
 /**
  *  ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
  *  @hw: pointer to hardware structure
  *  @input: unique input dword
  *  @common: compressed common input dword
  *  @queue: queue index to direct traffic to
  **/
 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
                                           union ixgbe_atr_hash_dword input,
                                           union ixgbe_atr_hash_dword common,
                                           u8 queue)
 {
 	u64  fdirhashcmd;
 	u32  fdircmd;
 	/*
 	 * Get the flow_type in order to program FDIRCMD properly
 	 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
 	 */
 	switch (input.formatted.flow_type) {
 	case IXGBE_ATR_FLOW_TYPE_TCPV4:
 	case IXGBE_ATR_FLOW_TYPE_UDPV4:
 	case IXGBE_ATR_FLOW_TYPE_SCTPV4:
 	case IXGBE_ATR_FLOW_TYPE_TCPV6:
 	case IXGBE_ATR_FLOW_TYPE_UDPV6:
 	case IXGBE_ATR_FLOW_TYPE_SCTPV6:
 		break;
 	default:
 		hw_dbg(hw, " Error on flow type input\n");
 		return IXGBE_ERR_CONFIG;
 	}
 	/* configure FDIRCMD register */
 	fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
 	          IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
 	fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
 	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
 	/*
 	 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
 	 * is for FDIRCMD.  Then do a 64-bit register write from FDIRHASH.
 	 */
 	fdirhashcmd = (u64)fdircmd << 32;
 	fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
 	IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
 	hw_dbg(hw, "Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
 	return 0;
 }
 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
 do { \
 	u32 n = (_n); \
 	if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
 		bucket_hash ^= lo_hash_dword >> n; \
 	if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
 		bucket_hash ^= hi_hash_dword >> n; \
 } while (0);
 /**
  *  ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
  *  @atr_input: input bitstream to compute the hash on
  *  @input_mask: mask for the input bitstream
  *
  *  This function serves two main purposes.  First it applys the input_mask
  *  to the atr_input resulting in a cleaned up atr_input data stream.
  *  Secondly it computes the hash and stores it in the bkt_hash field at
  *  the end of the input byte stream.  This way it will be available for
  *  future use without needing to recompute the hash.
  **/
 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
 					  union ixgbe_atr_input *input_mask)
 {
 	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
 	u32 bucket_hash = 0;
 	/* Apply masks to input data */
 	input->dword_stream[0]  &= input_mask->dword_stream[0];
 	input->dword_stream[1]  &= input_mask->dword_stream[1];
 	input->dword_stream[2]  &= input_mask->dword_stream[2];
 	input->dword_stream[3]  &= input_mask->dword_stream[3];
 	input->dword_stream[4]  &= input_mask->dword_stream[4];
 	input->dword_stream[5]  &= input_mask->dword_stream[5];
 	input->dword_stream[6]  &= input_mask->dword_stream[6];
 	input->dword_stream[7]  &= input_mask->dword_stream[7];
 	input->dword_stream[8]  &= input_mask->dword_stream[8];
 	input->dword_stream[9]  &= input_mask->dword_stream[9];
 	input->dword_stream[10] &= input_mask->dword_stream[10];
 	/* record the flow_vm_vlan bits as they are a key part to the hash */
 	flow_vm_vlan = ntohl(input->dword_stream[0]);
 	/* generate common hash dword */
 	hi_hash_dword = ntohl(input->dword_stream[1] ^
 				    input->dword_stream[2] ^
 				    input->dword_stream[3] ^
 				    input->dword_stream[4] ^
 				    input->dword_stream[5] ^
 				    input->dword_stream[6] ^
 				    input->dword_stream[7] ^
 				    input->dword_stream[8] ^
 				    input->dword_stream[9] ^
 				    input->dword_stream[10]);
 	/* low dword is word swapped version of common */
 	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
 	/* apply flow ID/VM pool/VLAN ID bits to hash words */
 	hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
 	/* Process bits 0 and 16 */
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
 	/*
 	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
 	 * delay this because bit 0 of the stream should not be processed
 	 * so we do not add the vlan until after bit 0 was processed
 	 */
 	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
 	/* Process remaining 30 bit of the key */
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
 	IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
 	/*
 	 * Limit hash to 13 bits since max bucket count is 8K.
 	 * Store result at the end of the input stream.
 	 */
 	input->formatted.bkt_hash = bucket_hash & 0x1FFF;
 }
 /**
  *  ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
  *  @input_mask: mask to be bit swapped
  *
  *  The source and destination port masks for flow director are bit swapped
  *  in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc.  In order to
  *  generate a correctly swapped value we need to bit swap the mask and that
  *  is what is accomplished by this function.
  **/
 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
 {
 	u32 mask = ntohs(input_mask->formatted.dst_port);
 	mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
 	mask |= ntohs(input_mask->formatted.src_port);
 	mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
 	mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
 	mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
 	return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
 }
 /*
  * These two macros are meant to address the fact that we have registers
  * that are either all or in part big-endian.  As a result on big-endian
  * systems we will end up byte swapping the value to little-endian before
  * it is byte swapped again and written to the hardware in the original
  * big-endian format.
  */
 #define IXGBE_STORE_AS_BE32(_value) \
 	(((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
 	 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
 	IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(ntohl(value)))
 #define IXGBE_STORE_AS_BE16(_value) \
 	ntohs(((u16)(_value) >> 8) | ((u16)(_value) << 8))
 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
 				    union ixgbe_atr_input *input_mask)
 {
 	/* mask IPv6 since it is currently not supported */
 	u32 fdirm = IXGBE_FDIRM_DIPv6;
 	u32 fdirtcpm;
 	/*
 	 * Program the relevant mask registers.  If src/dst_port or src/dst_addr
 	 * are zero, then assume a full mask for that field.  Also assume that
 	 * a VLAN of 0 is unspecified, so mask that out as well.  L4type
 	 * cannot be masked out in this implementation.
 	 *
 	 * This also assumes IPv4 only.  IPv6 masking isn't supported at this
 	 * point in time.
 	 */
 	/* verify bucket hash is cleared on hash generation */
 	if (input_mask->formatted.bkt_hash)
 		hw_dbg(hw, " bucket hash should always be 0 in mask\n");
 	/* Program FDIRM and verify partial masks */
 	switch (input_mask->formatted.vm_pool & 0x7F) {
 	case 0x0:
 		fdirm |= IXGBE_FDIRM_POOL;
 	case 0x7F:
 		break;
 	default:
 		hw_dbg(hw, " Error on vm pool mask\n");
 		return IXGBE_ERR_CONFIG;
 	}
 	switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
 	case 0x0:
 		fdirm |= IXGBE_FDIRM_L4P;
 		if (input_mask->formatted.dst_port ||
 		    input_mask->formatted.src_port) {
 			hw_dbg(hw, " Error on src/dst port mask\n");
 			return IXGBE_ERR_CONFIG;
 		}
 	case IXGBE_ATR_L4TYPE_MASK:
 		break;
 	default:
 		hw_dbg(hw, " Error on flow type mask\n");
 		return IXGBE_ERR_CONFIG;
 	}
 	switch (ntohs(input_mask->formatted.vlan_id) & 0xEFFF) {
 	case 0x0000:
 		/* mask VLAN ID, fall through to mask VLAN priority */
 		fdirm |= IXGBE_FDIRM_VLANID;
 	case 0x0FFF:
 		/* mask VLAN priority */
 		fdirm |= IXGBE_FDIRM_VLANP;
 		break;
 	case 0xE000:
 		/* mask VLAN ID only, fall through */
 		fdirm |= IXGBE_FDIRM_VLANID;
 	case 0xEFFF:
 		/* no VLAN fields masked */
 		break;
 	default:
 		hw_dbg(hw, " Error on VLAN mask\n");
 		return IXGBE_ERR_CONFIG;
 	}
 	switch (input_mask->formatted.flex_bytes & 0xFFFF) {
 	case 0x0000:
 		/* Mask Flex Bytes, fall through */
 		fdirm |= IXGBE_FDIRM_FLEX;
 	case 0xFFFF:
 		break;
 	default:
 		hw_dbg(hw, " Error on flexible byte mask\n");
 		return IXGBE_ERR_CONFIG;
 	}
 	/* Now mask VM pool and destination IPv6 - bits 5 and 2 */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
 	/* store the TCP/UDP port masks, bit reversed from port layout */
 	fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
 	/* write both the same so that UDP and TCP use the same mask */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
 	/* store source and destination IP masks (big-enian) */
 	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
 			     ~input_mask->formatted.src_ip[0]);
 	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
 			     ~input_mask->formatted.dst_ip[0]);
 	return 0;
 }
 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
 					  union ixgbe_atr_input *input,
 					  u16 soft_id, u8 queue)
 {
 	u32 fdirport, fdirvlan, fdirhash, fdircmd;
 	/* currently IPv6 is not supported, must be programmed with 0 */
 	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
 			     input->formatted.src_ip[0]);
 	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
 			     input->formatted.src_ip[1]);
 	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
 			     input->formatted.src_ip[2]);
 	/* record the source address (big-endian) */
 	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
 	/* record the first 32 bits of the destination address (big-endian) */
 	IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
 	/* record source and destination port (little-endian)*/
 	fdirport = ntohs(input->formatted.dst_port);
 	fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
 	fdirport |= ntohs(input->formatted.src_port);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
 	/* record vlan (little-endian) and flex_bytes(big-endian) */
 	fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
 	fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
 	fdirvlan |= ntohs(input->formatted.vlan_id);
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
 	/* configure FDIRHASH register */
 	fdirhash = input->formatted.bkt_hash;
 	fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
 	/*
 	 * flush all previous writes to make certain registers are
 	 * programmed prior to issuing the command
 	 */
 	IXGBE_WRITE_FLUSH(hw);
 	/* configure FDIRCMD register */
 	fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
 		  IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
 	if (queue == IXGBE_FDIR_DROP_QUEUE)
 		fdircmd |= IXGBE_FDIRCMD_DROP;
 	fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
 	fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
 	fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
 	return 0;
 }
 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
 					  union ixgbe_atr_input *input,
 					  u16 soft_id)
 {
 	u32 fdirhash;
 	u32 fdircmd = 0;
 	u32 retry_count;
 	s32 err = 0;
 	/* configure FDIRHASH register */
 	fdirhash = input->formatted.bkt_hash;
 	fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
 	/* flush hash to HW */
 	IXGBE_WRITE_FLUSH(hw);
 	/* Query if filter is present */
 	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
 	for (retry_count = 10; retry_count; retry_count--) {
 		/* allow 10us for query to process */
 		udelay(10);
 		/* verify query completed successfully */
 		fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
 		if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
 			break;
 	}
 	if (!retry_count)
 		err = IXGBE_ERR_FDIR_REINIT_FAILED;
 	/* if filter exists in hardware then remove it */
 	if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
 		IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
 		IXGBE_WRITE_FLUSH(hw);
 		IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
 				IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
 	}
 	return err;
 }
 /**
  *  ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
  *  @hw: pointer to hardware structure
  *  @reg: analog register to read
  *  @val: read value
  *
  *  Performs read operation to Omer analog register specified.
  **/
 static s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
 {
 	u32  core_ctl;
 	IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
 	                (reg << 8));
 	IXGBE_WRITE_FLUSH(hw);
 	udelay(10);
 	core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
 	*val = (u8)core_ctl;
 	return 0;
 }
 /**
  *  ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
  *  @hw: pointer to hardware structure
  *  @reg: atlas register to write
  *  @val: value to write
  *
  *  Performs write operation to Omer analog register specified.
  **/
 static s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
 {
 	u32  core_ctl;
 	core_ctl = (reg << 8) | val;
 	IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
 	IXGBE_WRITE_FLUSH(hw);
 	udelay(10);
 	return 0;
 }
 /**
  *  ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
  *  @hw: pointer to hardware structure
  *
  *  Starts the hardware using the generic start_hw function
  *  and the generation start_hw function.
  *  Then performs revision-specific operations, if any.
  **/
 static s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
 {
 	s32 ret_val = 0;
 	ret_val = ixgbe_start_hw_generic(hw);
 	if (ret_val != 0)
 		goto out;
 	ret_val = ixgbe_start_hw_gen2(hw);
 	if (ret_val != 0)
 		goto out;
 	/* We need to run link autotry after the driver loads */
 	hw->mac.autotry_restart = true;
 	hw->mac.rx_pb_size = IXGBE_82599_RX_PB_SIZE;
 	if (ret_val == 0)
 		ret_val = ixgbe_verify_fw_version_82599(hw);
 out:
 	return ret_val;
 }
 /**
  *  ixgbe_identify_phy_82599 - Get physical layer module
  *  @hw: pointer to hardware structure
  *
  *  Determines the physical layer module found on the current adapter.
  *  If PHY already detected, maintains current PHY type in hw struct,
  *  otherwise executes the PHY detection routine.
  **/
 static s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 	/* Detect PHY if not unknown - returns success if already detected. */
 	status = ixgbe_identify_phy_generic(hw);
 	if (status != 0) {
 		/* 82599 10GBASE-T requires an external PHY */
 		if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
 			goto out;
 		else
 			status = ixgbe_identify_sfp_module_generic(hw);
 	}
 	/* Set PHY type none if no PHY detected */
 	if (hw->phy.type == ixgbe_phy_unknown) {
 		hw->phy.type = ixgbe_phy_none;
 		status = 0;
 	}
 	/* Return error if SFP module has been detected but is not supported */
 	if (hw->phy.type == ixgbe_phy_sfp_unsupported)
 		status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 out:
 	return status;
 }
 /**
  *  ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
  *  @hw: pointer to hardware structure
  *
  *  Determines physical layer capabilities of the current configuration.
  **/
 static u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
 {
 	u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
 	u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 	u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
 	u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
 	u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
 	u16 ext_ability = 0;
 	u8 comp_codes_10g = 0;
 	u8 comp_codes_1g = 0;
 	hw->phy.ops.identify(hw);
 	switch (hw->phy.type) {
 	case ixgbe_phy_tn:
 	case ixgbe_phy_cu_unknown:
 		hw->phy.ops.read_reg(hw, MDIO_PMA_EXTABLE, MDIO_MMD_PMAPMD,
 							 &ext_ability);
 		if (ext_ability & MDIO_PMA_EXTABLE_10GBT)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
 		if (ext_ability & MDIO_PMA_EXTABLE_1000BT)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
 		if (ext_ability & MDIO_PMA_EXTABLE_100BTX)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
 		goto out;
 	default:
 		break;
 	}
 	switch (autoc & IXGBE_AUTOC_LMS_MASK) {
 	case IXGBE_AUTOC_LMS_1G_AN:
 	case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
 		if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
 			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
 			    IXGBE_PHYSICAL_LAYER_1000BASE_BX;
 			goto out;
 		} else
 			/* SFI mode so read SFP module */
 			goto sfp_check;
 		break;
 	case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
 		if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
 		else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
 		else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
 		goto out;
 		break;
 	case IXGBE_AUTOC_LMS_10G_SERIAL:
 		if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
 			goto out;
 		} else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
 			goto sfp_check;
 		break;
 	case IXGBE_AUTOC_LMS_KX4_KX_KR:
 	case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
 		if (autoc & IXGBE_AUTOC_KX_SUPP)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
 		if (autoc & IXGBE_AUTOC_KX4_SUPP)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
 		if (autoc & IXGBE_AUTOC_KR_SUPP)
 			physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
 		goto out;
 		break;
 	default:
 		goto out;
 		break;
 	}
 sfp_check:
 	/* SFP check must be done last since DA modules are sometimes used to
 	 * test KR mode -  we need to id KR mode correctly before SFP module.
 	 * Call identify_sfp because the pluggable module may have changed */
 	hw->phy.ops.identify_sfp(hw);
 	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
 		goto out;
 	switch (hw->phy.type) {
 	case ixgbe_phy_sfp_passive_tyco:
 	case ixgbe_phy_sfp_passive_unknown:
 		physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
 		break;
 	case ixgbe_phy_sfp_ftl_active:
 	case ixgbe_phy_sfp_active_unknown:
 		physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
 		break;
 	case ixgbe_phy_sfp_avago:
 	case ixgbe_phy_sfp_ftl:
 	case ixgbe_phy_sfp_intel:
 	case ixgbe_phy_sfp_unknown:
 		hw->phy.ops.read_i2c_eeprom(hw,
 		      IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
 		hw->phy.ops.read_i2c_eeprom(hw,
 		      IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
 		if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
 		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
 		else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
 			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
 		break;
 	default:
 		break;
 	}
 out:
 	return physical_layer;
 }
 /**
  *  ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
  *  @hw: pointer to hardware structure
  *  @regval: register value to write to RXCTRL
  *
  *  Enables the Rx DMA unit for 82599
  **/
 static s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
 {
 	/*
 	 * Workaround for 82599 silicon errata when enabling the Rx datapath.
 	 * If traffic is incoming before we enable the Rx unit, it could hang
 	 * the Rx DMA unit.  Therefore, make sure the security engine is
 	 * completely disabled prior to enabling the Rx unit.
 	 */
 	hw->mac.ops.disable_rx_buff(hw);
 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
 	hw->mac.ops.enable_rx_buff(hw);
 	return 0;
 }
 /**
  *  ixgbe_verify_fw_version_82599 - verify fw version for 82599
  *  @hw: pointer to hardware structure
  *
  *  Verifies that installed the firmware version is 0.6 or higher
  *  for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
  *
  *  Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
  *  if the FW version is not supported.
  **/
 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_EEPROM_VERSION;
 	u16 fw_offset, fw_ptp_cfg_offset;
 	u16 fw_version = 0;
 	/* firmware check is only necessary for SFI devices */
 	if (hw->phy.media_type != ixgbe_media_type_fiber) {
 		status = 0;
 		goto fw_version_out;
 	}
 	/* get the offset to the Firmware Module block */
 	hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
 	if ((fw_offset == 0) || (fw_offset == 0xFFFF))
 		goto fw_version_out;
 	/* get the offset to the Pass Through Patch Configuration block */
 	hw->eeprom.ops.read(hw, (fw_offset +
 	                         IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
 	                         &fw_ptp_cfg_offset);
 	if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
 		goto fw_version_out;
 	/* get the firmware version */
 	hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
 	                         IXGBE_FW_PATCH_VERSION_4),
 	                         &fw_version);
 	if (fw_version > 0x5)
 		status = 0;
 fw_version_out:
 	return status;
 }
 /**
  *  ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
  *  @hw: pointer to hardware structure
  *
  *  Returns true if the LESM FW module is present and enabled. Otherwise
  *  returns false. Smart Speed must be disabled if LESM FW module is enabled.
  **/
 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
 {
 	bool lesm_enabled = false;
 	u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
 	s32 status;
 	/* get the offset to the Firmware Module block */
 	status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
 	if ((status != 0) ||
 	    (fw_offset == 0) || (fw_offset == 0xFFFF))
 		goto out;
 	/* get the offset to the LESM Parameters block */
 	status = hw->eeprom.ops.read(hw, (fw_offset +
 				     IXGBE_FW_LESM_PARAMETERS_PTR),
 				     &fw_lesm_param_offset);
 	if ((status != 0) ||
 	    (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
 		goto out;
 	/* get the lesm state word */
 	status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
 				     IXGBE_FW_LESM_STATE_1),
 				     &fw_lesm_state);
 	if ((status == 0) &&
 	    (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
 		lesm_enabled = true;
 out:
 	return lesm_enabled;
 }
 /**
  *  ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
  *  fastest available method
  *
  *  @hw: pointer to hardware structure
  *  @offset: offset of  word in EEPROM to read
  *  @words: number of words
  *  @data: word(s) read from the EEPROM
  *
  *  Retrieves 16 bit word(s) read from EEPROM
  **/
 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
 					  u16 words, u16 *data)
 {
 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 	s32 ret_val = IXGBE_ERR_CONFIG;
 	/*
 	 * If EEPROM is detected and can be addressed using 14 bits,
 	 * use EERD otherwise use bit bang
 	 */
 	if ((eeprom->type == ixgbe_eeprom_spi) &&
 	    (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
 		ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
 							 data);
 	else
 		ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
 								    words,
 								    data);
 	return ret_val;
 }
 /**
  *  ixgbe_read_eeprom_82599 - Read EEPROM word using
  *  fastest available method
  *
  *  @hw: pointer to hardware structure
  *  @offset: offset of  word in the EEPROM to read
  *  @data: word read from the EEPROM
  *
  *  Reads a 16 bit word from the EEPROM
  **/
 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
 				   u16 offset, u16 *data)
 {
 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 	s32 ret_val = IXGBE_ERR_CONFIG;
 	/*
 	 * If EEPROM is detected and can be addressed using 14 bits,
 	 * use EERD otherwise use bit bang
 	 */
 	if ((eeprom->type == ixgbe_eeprom_spi) &&
 	    (offset <= IXGBE_EERD_MAX_ADDR))
 		ret_val = ixgbe_read_eerd_generic(hw, offset, data);
 	else
 		ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
 	return ret_val;
 }
 /**
  * ixgbe_reset_pipeline_82599 - perform pipeline reset
  *
  * @hw: pointer to hardware structure
  *
  * Reset pipeline by asserting Restart_AN together with LMS change to ensure
  * full pipeline reset.  Note - We must hold the SW/FW semaphore before writing
  * to AUTOC, so this function assumes the semaphore is held.
  **/
 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
 {
 	s32 ret_val;
 	u32 anlp1_reg = 0;
 	u32 i, autoc_reg, autoc2_reg;
 	/* Enable link if disabled in NVM */
 	autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
 	if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
 		autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
 		IXGBE_WRITE_FLUSH(hw);
 	}
 	autoc_reg = hw->mac.cached_autoc;
 	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 	/* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
 	/* Wait for AN to leave state 0 */
 	for (i = 0; i < 10; i++) {
 		usleep_range(4000, 8000);
 		anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
 		if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
 			break;
 	}
 	if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
 		hw_dbg(hw, "auto negotiation not completed\n");
 		ret_val = IXGBE_ERR_RESET_FAILED;
 		goto reset_pipeline_out;
 	}
 	ret_val = 0;
 reset_pipeline_out:
 	/* Write AUTOC register with original LMS field and Restart_AN */
 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 	IXGBE_WRITE_FLUSH(hw);
 	return ret_val;
 }
 static struct ixgbe_mac_operations mac_ops_82599 = {
 	.init_hw                = &ixgbe_init_hw_generic,
 	.reset_hw               = &ixgbe_reset_hw_82599,
 	.start_hw               = &ixgbe_start_hw_82599,
 	.clear_hw_cntrs         = &ixgbe_clear_hw_cntrs_generic,
 	.get_media_type         = &ixgbe_get_media_type_82599,
 	.get_supported_physical_layer = &ixgbe_get_supported_physical_layer_82599,
 	.enable_rx_dma          = &ixgbe_enable_rx_dma_82599,
 	.disable_rx_buff	= &ixgbe_disable_rx_buff_generic,
 	.enable_rx_buff		= &ixgbe_enable_rx_buff_generic,
 	.get_mac_addr           = &ixgbe_get_mac_addr_generic,
 	.get_san_mac_addr       = &ixgbe_get_san_mac_addr_generic,
 	.get_device_caps        = &ixgbe_get_device_caps_generic,
 	.get_wwn_prefix         = &ixgbe_get_wwn_prefix_generic,
 	.stop_adapter           = &ixgbe_stop_adapter_generic,
 	.get_bus_info           = &ixgbe_get_bus_info_generic,
 	.set_lan_id             = &ixgbe_set_lan_id_multi_port_pcie,
 	.read_analog_reg8       = &ixgbe_read_analog_reg8_82599,
 	.write_analog_reg8      = &ixgbe_write_analog_reg8_82599,
 	.setup_link             = &ixgbe_setup_mac_link_82599,
 	.set_rxpba		= &ixgbe_set_rxpba_generic,
 	.check_link             = &ixgbe_check_mac_link_generic,
 	.get_link_capabilities  = &ixgbe_get_link_capabilities_82599,
 	.led_on                 = &ixgbe_led_on_generic,
 	.led_off                = &ixgbe_led_off_generic,
 	.blink_led_start        = &ixgbe_blink_led_start_generic,
 	.blink_led_stop         = &ixgbe_blink_led_stop_generic,
 	.set_rar                = &ixgbe_set_rar_generic,
 	.clear_rar              = &ixgbe_clear_rar_generic,
 	.set_vmdq               = &ixgbe_set_vmdq_generic,
 	.set_vmdq_san_mac	= &ixgbe_set_vmdq_san_mac_generic,
 	.clear_vmdq             = &ixgbe_clear_vmdq_generic,
 	.init_rx_addrs          = &ixgbe_init_rx_addrs_generic,
 	.update_mc_addr_list    = &ixgbe_update_mc_addr_list_generic,
 	.enable_mc              = &ixgbe_enable_mc_generic,
 	.disable_mc             = &ixgbe_disable_mc_generic,
 	.clear_vfta             = &ixgbe_clear_vfta_generic,
 	.set_vfta               = &ixgbe_set_vfta_generic,
 	.fc_enable              = &ixgbe_fc_enable_generic,
 	.set_fw_drv_ver         = &ixgbe_set_fw_drv_ver_generic,
 	.init_uta_tables        = &ixgbe_init_uta_tables_generic,
 	.setup_sfp              = &ixgbe_setup_sfp_modules_82599,
 	.set_mac_anti_spoofing  = &ixgbe_set_mac_anti_spoofing,
 	.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing,
 	.acquire_swfw_sync      = &ixgbe_acquire_swfw_sync,
 	.release_swfw_sync      = &ixgbe_release_swfw_sync,
 	.get_thermal_sensor_data = &ixgbe_get_thermal_sensor_data_generic,
 	.init_thermal_sensor_thresh = &ixgbe_init_thermal_sensor_thresh_generic,
 	.mng_fw_enabled		= &ixgbe_mng_enabled,
 };
 static struct ixgbe_eeprom_operations eeprom_ops_82599 = {
 	.init_params		= &ixgbe_init_eeprom_params_generic,
 	.read			= &ixgbe_read_eeprom_82599,
 	.read_buffer		= &ixgbe_read_eeprom_buffer_82599,
 	.write			= &ixgbe_write_eeprom_generic,
 	.write_buffer		= &ixgbe_write_eeprom_buffer_bit_bang_generic,
 	.calc_checksum		= &ixgbe_calc_eeprom_checksum_generic,
 	.validate_checksum	= &ixgbe_validate_eeprom_checksum_generic,
 	.update_checksum	= &ixgbe_update_eeprom_checksum_generic,
 };
 static struct ixgbe_phy_operations phy_ops_82599 = {
 	.identify		= &ixgbe_identify_phy_82599,
 	.identify_sfp		= &ixgbe_identify_sfp_module_generic,
 	.init			= &ixgbe_init_phy_ops_82599,
 	.reset			= &ixgbe_reset_phy_generic,
 	.read_reg		= &ixgbe_read_phy_reg_generic,
 	.write_reg		= &ixgbe_write_phy_reg_generic,
 	.setup_link		= &ixgbe_setup_phy_link_generic,
 	.setup_link_speed	= &ixgbe_setup_phy_link_speed_generic,
 	.read_i2c_byte		= &ixgbe_read_i2c_byte_generic,
 	.write_i2c_byte		= &ixgbe_write_i2c_byte_generic,
 	.read_i2c_sff8472	= &ixgbe_read_i2c_sff8472_generic,
 	.read_i2c_eeprom	= &ixgbe_read_i2c_eeprom_generic,
 	.write_i2c_eeprom	= &ixgbe_write_i2c_eeprom_generic,
 	.check_overtemp		= &ixgbe_tn_check_overtemp,
 };
 struct ixgbe_info ixgbe_82599_info = {
 	.mac                    = ixgbe_mac_82599EB,
 	.get_invariants         = &ixgbe_get_invariants_82599,
 	.mac_ops                = &mac_ops_82599,
 	.eeprom_ops             = &eeprom_ops_82599,
 	.phy_ops                = &phy_ops_82599,
 	.mbx_ops                = &mbx_ops_generic,
 };

drivers/net/ethernet/intel/ixgbe/ixgbe_common.c

Diff comments View file @ 4e8e1bc

 /*******************************************************************************
   Intel 10 Gigabit PCI Express Linux driver
   Copyright(c) 1999 - 2013 Intel Corporation.
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
   version 2, as published by the Free Software Foundation.
   This program is distributed in the hope it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
   You should have received a copy of the GNU General Public License along with
   this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   The full GNU General Public License is included in this distribution in
   the file called "COPYING".
   Contact Information:
   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *******************************************************************************/
 #include <linux/pci.h>
 #include <linux/delay.h>
 #include <linux/sched.h>
 #include <linux/netdevice.h>
 #include "ixgbe.h"
 #include "ixgbe_common.h"
 #include "ixgbe_phy.h"
 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
                                         u16 count);
 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
 static void ixgbe_release_eeprom(struct ixgbe_hw *hw);
 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg);
 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
 					     u16 words, u16 *data);
 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
 					     u16 words, u16 *data);
 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
 						 u16 offset);
 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw);
 /**
  *  ixgbe_device_supports_autoneg_fc - Check if phy supports autoneg flow
  *  control
  *  @hw: pointer to hardware structure
  *
  *  There are several phys that do not support autoneg flow control. This
  *  function check the device id to see if the associated phy supports
  *  autoneg flow control.
  **/
 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
 {
 	bool supported = false;
 	ixgbe_link_speed speed;
 	bool link_up;
 	switch (hw->phy.media_type) {
+	case ixgbe_media_type_fiber_fixed:
 	case ixgbe_media_type_fiber:
 		hw->mac.ops.check_link(hw, &speed, &link_up, false);
 		/* if link is down, assume supported */
 		if (link_up)
 			supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
 				true : false;
 		else
 			supported = true;
 		break;
 	case ixgbe_media_type_backplane:
 		supported = true;
 		break;
 	case ixgbe_media_type_copper:
 		/* only some copper devices support flow control autoneg */
 		switch (hw->device_id) {
 		case IXGBE_DEV_ID_82599_T3_LOM:
 		case IXGBE_DEV_ID_X540T:
 		case IXGBE_DEV_ID_X540T1:
 			supported = true;
 			break;
 		default:
 			break;
 		}
 	default:
 		break;
 	}
 	return supported;
 }
 /**
  *  ixgbe_setup_fc - Set up flow control
  *  @hw: pointer to hardware structure
  *
  *  Called at init time to set up flow control.
  **/
 static s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
 {
 	s32 ret_val = 0;
 	u32 reg = 0, reg_bp = 0;
 	u16 reg_cu = 0;
 	bool got_lock = false;
 	/*
 	 * Validate the requested mode.  Strict IEEE mode does not allow
 	 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
 	 */
 	if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
 		hw_dbg(hw, "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
 		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 		goto out;
 	}
 	/*
 	 * 10gig parts do not have a word in the EEPROM to determine the
 	 * default flow control setting, so we explicitly set it to full.
 	 */
 	if (hw->fc.requested_mode == ixgbe_fc_default)
 		hw->fc.requested_mode = ixgbe_fc_full;
 	/*
 	 * Set up the 1G and 10G flow control advertisement registers so the
 	 * HW will be able to do fc autoneg once the cable is plugged in.  If
 	 * we link at 10G, the 1G advertisement is harmless and vice versa.
 	 */
 	switch (hw->phy.media_type) {
+	case ixgbe_media_type_fiber_fixed:
 	case ixgbe_media_type_fiber:
 	case ixgbe_media_type_backplane:
 		reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 		reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 		break;
 	case ixgbe_media_type_copper:
 		hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 					MDIO_MMD_AN, &reg_cu);
 		break;
 	default:
 		break;
 	}
 	/*
 	 * The possible values of fc.requested_mode are:
 	 * 0: Flow control is completely disabled
 	 * 1: Rx flow control is enabled (we can receive pause frames,
 	 *    but not send pause frames).
 	 * 2: Tx flow control is enabled (we can send pause frames but
 	 *    we do not support receiving pause frames).
 	 * 3: Both Rx and Tx flow control (symmetric) are enabled.
 	 * other: Invalid.
 	 */
 	switch (hw->fc.requested_mode) {
 	case ixgbe_fc_none:
 		/* Flow control completely disabled by software override. */
 		reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
 		if (hw->phy.media_type == ixgbe_media_type_backplane)
 			reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
 				    IXGBE_AUTOC_ASM_PAUSE);
 		else if (hw->phy.media_type == ixgbe_media_type_copper)
 			reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
 		break;
 	case ixgbe_fc_tx_pause:
 		/*
 		 * Tx Flow control is enabled, and Rx Flow control is
 		 * disabled by software override.
 		 */
 		reg |= IXGBE_PCS1GANA_ASM_PAUSE;
 		reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
 		if (hw->phy.media_type == ixgbe_media_type_backplane) {
 			reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
 			reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
 		} else if (hw->phy.media_type == ixgbe_media_type_copper) {
 			reg_cu |= IXGBE_TAF_ASM_PAUSE;
 			reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
 		}
 		break;
 	case ixgbe_fc_rx_pause:
 		/*
 		 * Rx Flow control is enabled and Tx Flow control is
 		 * disabled by software override. Since there really
 		 * isn't a way to advertise that we are capable of RX
 		 * Pause ONLY, we will advertise that we support both
 		 * symmetric and asymmetric Rx PAUSE, as such we fall
 		 * through to the fc_full statement.  Later, we will
 		 * disable the adapter's ability to send PAUSE frames.
 		 */
 	case ixgbe_fc_full:
 		/* Flow control (both Rx and Tx) is enabled by SW override. */
 		reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
 		if (hw->phy.media_type == ixgbe_media_type_backplane)
 			reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
 				  IXGBE_AUTOC_ASM_PAUSE;
 		else if (hw->phy.media_type == ixgbe_media_type_copper)
 			reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
 		break;
 	default:
 		hw_dbg(hw, "Flow control param set incorrectly\n");
 		ret_val = IXGBE_ERR_CONFIG;
 		goto out;
 		break;
 	}
 	if (hw->mac.type != ixgbe_mac_X540) {
 		/*
 		 * Enable auto-negotiation between the MAC & PHY;
 		 * the MAC will advertise clause 37 flow control.
 		 */
 		IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
 		reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
 		/* Disable AN timeout */
 		if (hw->fc.strict_ieee)
 			reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
 		IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
 		hw_dbg(hw, "Set up FC; PCS1GLCTL = 0x%08X\n", reg);
 	}
 	/*
 	 * AUTOC restart handles negotiation of 1G and 10G on backplane
 	 * and copper. There is no need to set the PCS1GCTL register.
 	 *
 	 */
 	if (hw->phy.media_type == ixgbe_media_type_backplane) {
 		/* Need the SW/FW semaphore around AUTOC writes if 82599 and
 		 * LESM is on, likewise reset_pipeline requries the lock as
 		 * it also writes AUTOC.
 		 */
 		if ((hw->mac.type == ixgbe_mac_82599EB) &&
 		    ixgbe_verify_lesm_fw_enabled_82599(hw)) {
 			ret_val = hw->mac.ops.acquire_swfw_sync(hw,
 							IXGBE_GSSR_MAC_CSR_SM);
 			if (ret_val)
 				goto out;
 			got_lock = true;
 		}
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
 		if (hw->mac.type == ixgbe_mac_82599EB)
 			ixgbe_reset_pipeline_82599(hw);
 		if (got_lock)
 			hw->mac.ops.release_swfw_sync(hw,
 						      IXGBE_GSSR_MAC_CSR_SM);
 	} else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
 		    ixgbe_device_supports_autoneg_fc(hw)) {
 		hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE,
 				      MDIO_MMD_AN, reg_cu);
 	}
 	hw_dbg(hw, "Set up FC; IXGBE_AUTOC = 0x%08X\n", reg);
 out:
 	return ret_val;
 }
 /**
  *  ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
  *  @hw: pointer to hardware structure
  *
  *  Starts the hardware by filling the bus info structure and media type, clears
  *  all on chip counters, initializes receive address registers, multicast
  *  table, VLAN filter table, calls routine to set up link and flow control
  *  settings, and leaves transmit and receive units disabled and uninitialized
  **/
 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
 {
 	u32 ctrl_ext;
 	/* Set the media type */
 	hw->phy.media_type = hw->mac.ops.get_media_type(hw);
 	/* Identify the PHY */
 	hw->phy.ops.identify(hw);
 	/* Clear the VLAN filter table */
 	hw->mac.ops.clear_vfta(hw);
 	/* Clear statistics registers */
 	hw->mac.ops.clear_hw_cntrs(hw);
 	/* Set No Snoop Disable */
 	ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
 	ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
 	IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
 	IXGBE_WRITE_FLUSH(hw);
 	/* Setup flow control */
 	ixgbe_setup_fc(hw);
 	/* Clear adapter stopped flag */
 	hw->adapter_stopped = false;
 	return 0;
 }
 /**
  *  ixgbe_start_hw_gen2 - Init sequence for common device family
  *  @hw: pointer to hw structure
  *
  * Performs the init sequence common to the second generation
  * of 10 GbE devices.
  * Devices in the second generation:
  *     82599
  *     X540
  **/
 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
 {
 	u32 i;
 	u32 regval;
 	/* Clear the rate limiters */
 	for (i = 0; i < hw->mac.max_tx_queues; i++) {
 		IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
 		IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
 	}
 	IXGBE_WRITE_FLUSH(hw);
 	/* Disable relaxed ordering */
 	for (i = 0; i < hw->mac.max_tx_queues; i++) {
 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
 		regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
 		IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
 	}
 	for (i = 0; i < hw->mac.max_rx_queues; i++) {
 		regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 		regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
 			    IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
 		IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
 	}
 	return 0;
 }
 /**
  *  ixgbe_init_hw_generic - Generic hardware initialization
  *  @hw: pointer to hardware structure
  *
  *  Initialize the hardware by resetting the hardware, filling the bus info
  *  structure and media type, clears all on chip counters, initializes receive
  *  address registers, multicast table, VLAN filter table, calls routine to set
  *  up link and flow control settings, and leaves transmit and receive units
  *  disabled and uninitialized
  **/
 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
 {
 	s32 status;
 	/* Reset the hardware */
 	status = hw->mac.ops.reset_hw(hw);
 	if (status == 0) {
 		/* Start the HW */
 		status = hw->mac.ops.start_hw(hw);
 	}
 	return status;
 }
 /**
  *  ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
  *  @hw: pointer to hardware structure
  *
  *  Clears all hardware statistics counters by reading them from the hardware
  *  Statistics counters are clear on read.
  **/
 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
 {
 	u16 i = 0;
 	IXGBE_READ_REG(hw, IXGBE_CRCERRS);
 	IXGBE_READ_REG(hw, IXGBE_ILLERRC);
 	IXGBE_READ_REG(hw, IXGBE_ERRBC);
 	IXGBE_READ_REG(hw, IXGBE_MSPDC);
 	for (i = 0; i < 8; i++)
 		IXGBE_READ_REG(hw, IXGBE_MPC(i));
 	IXGBE_READ_REG(hw, IXGBE_MLFC);
 	IXGBE_READ_REG(hw, IXGBE_MRFC);
 	IXGBE_READ_REG(hw, IXGBE_RLEC);
 	IXGBE_READ_REG(hw, IXGBE_LXONTXC);
 	IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
 	if (hw->mac.type >= ixgbe_mac_82599EB) {
 		IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
 		IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 	} else {
 		IXGBE_READ_REG(hw, IXGBE_LXONRXC);
 		IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 	}
 	for (i = 0; i < 8; i++) {
 		IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
 		IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
 		if (hw->mac.type >= ixgbe_mac_82599EB) {
 			IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
 			IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 		} else {
 			IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
 			IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 		}
 	}
 	if (hw->mac.type >= ixgbe_mac_82599EB)
 		for (i = 0; i < 8; i++)
 			IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
 	IXGBE_READ_REG(hw, IXGBE_PRC64);
 	IXGBE_READ_REG(hw, IXGBE_PRC127);
 	IXGBE_READ_REG(hw, IXGBE_PRC255);
 	IXGBE_READ_REG(hw, IXGBE_PRC511);
 	IXGBE_READ_REG(hw, IXGBE_PRC1023);
 	IXGBE_READ_REG(hw, IXGBE_PRC1522);
 	IXGBE_READ_REG(hw, IXGBE_GPRC);
 	IXGBE_READ_REG(hw, IXGBE_BPRC);
 	IXGBE_READ_REG(hw, IXGBE_MPRC);
 	IXGBE_READ_REG(hw, IXGBE_GPTC);
 	IXGBE_READ_REG(hw, IXGBE_GORCL);
 	IXGBE_READ_REG(hw, IXGBE_GORCH);
 	IXGBE_READ_REG(hw, IXGBE_GOTCL);
 	IXGBE_READ_REG(hw, IXGBE_GOTCH);
 	if (hw->mac.type == ixgbe_mac_82598EB)
 		for (i = 0; i < 8; i++)
 			IXGBE_READ_REG(hw, IXGBE_RNBC(i));
 	IXGBE_READ_REG(hw, IXGBE_RUC);
 	IXGBE_READ_REG(hw, IXGBE_RFC);
 	IXGBE_READ_REG(hw, IXGBE_ROC);
 	IXGBE_READ_REG(hw, IXGBE_RJC);
 	IXGBE_READ_REG(hw, IXGBE_MNGPRC);
 	IXGBE_READ_REG(hw, IXGBE_MNGPDC);
 	IXGBE_READ_REG(hw, IXGBE_MNGPTC);
 	IXGBE_READ_REG(hw, IXGBE_TORL);
 	IXGBE_READ_REG(hw, IXGBE_TORH);
 	IXGBE_READ_REG(hw, IXGBE_TPR);
 	IXGBE_READ_REG(hw, IXGBE_TPT);
 	IXGBE_READ_REG(hw, IXGBE_PTC64);
 	IXGBE_READ_REG(hw, IXGBE_PTC127);
 	IXGBE_READ_REG(hw, IXGBE_PTC255);
 	IXGBE_READ_REG(hw, IXGBE_PTC511);
 	IXGBE_READ_REG(hw, IXGBE_PTC1023);
 	IXGBE_READ_REG(hw, IXGBE_PTC1522);
 	IXGBE_READ_REG(hw, IXGBE_MPTC);
 	IXGBE_READ_REG(hw, IXGBE_BPTC);
 	for (i = 0; i < 16; i++) {
 		IXGBE_READ_REG(hw, IXGBE_QPRC(i));
 		IXGBE_READ_REG(hw, IXGBE_QPTC(i));
 		if (hw->mac.type >= ixgbe_mac_82599EB) {
 			IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
 			IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
 			IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
 			IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
 			IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
 		} else {
 			IXGBE_READ_REG(hw, IXGBE_QBRC(i));
 			IXGBE_READ_REG(hw, IXGBE_QBTC(i));
 		}
 	}
 	if (hw->mac.type == ixgbe_mac_X540) {
 		if (hw->phy.id == 0)
 			hw->phy.ops.identify(hw);
 		hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL, MDIO_MMD_PCS, &i);
 		hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH, MDIO_MMD_PCS, &i);
 		hw->phy.ops.read_reg(hw, IXGBE_LDPCECL, MDIO_MMD_PCS, &i);
 		hw->phy.ops.read_reg(hw, IXGBE_LDPCECH, MDIO_MMD_PCS, &i);
 	}
 	return 0;
 }
 /**
  *  ixgbe_read_pba_string_generic - Reads part number string from EEPROM
  *  @hw: pointer to hardware structure
  *  @pba_num: stores the part number string from the EEPROM
  *  @pba_num_size: part number string buffer length
  *
  *  Reads the part number string from the EEPROM.
  **/
 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
                                   u32 pba_num_size)
 {
 	s32 ret_val;
 	u16 data;
 	u16 pba_ptr;
 	u16 offset;
 	u16 length;
 	if (pba_num == NULL) {
 		hw_dbg(hw, "PBA string buffer was null\n");
 		return IXGBE_ERR_INVALID_ARGUMENT;
 	}
 	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
 	if (ret_val) {
 		hw_dbg(hw, "NVM Read Error\n");
 		return ret_val;
 	}
 	ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
 	if (ret_val) {
 		hw_dbg(hw, "NVM Read Error\n");
 		return ret_val;
 	}
 	/*
 	 * if data is not ptr guard the PBA must be in legacy format which
 	 * means pba_ptr is actually our second data word for the PBA number
 	 * and we can decode it into an ascii string
 	 */
 	if (data != IXGBE_PBANUM_PTR_GUARD) {
 		hw_dbg(hw, "NVM PBA number is not stored as string\n");
 		/* we will need 11 characters to store the PBA */
 		if (pba_num_size < 11) {
 			hw_dbg(hw, "PBA string buffer too small\n");
 			return IXGBE_ERR_NO_SPACE;
 		}
 		/* extract hex string from data and pba_ptr */
 		pba_num[0] = (data >> 12) & 0xF;
 		pba_num[1] = (data >> 8) & 0xF;
 		pba_num[2] = (data >> 4) & 0xF;
 		pba_num[3] = data & 0xF;
 		pba_num[4] = (pba_ptr >> 12) & 0xF;
 		pba_num[5] = (pba_ptr >> 8) & 0xF;
 		pba_num[6] = '-';
 		pba_num[7] = 0;
 		pba_num[8] = (pba_ptr >> 4) & 0xF;
 		pba_num[9] = pba_ptr & 0xF;
 		/* put a null character on the end of our string */
 		pba_num[10] = '\0';
 		/* switch all the data but the '-' to hex char */
 		for (offset = 0; offset < 10; offset++) {
 			if (pba_num[offset] < 0xA)
 				pba_num[offset] += '0';
 			else if (pba_num[offset] < 0x10)
 				pba_num[offset] += 'A' - 0xA;
 		}
 		return 0;
 	}
 	ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
 	if (ret_val) {
 		hw_dbg(hw, "NVM Read Error\n");
 		return ret_val;
 	}
 	if (length == 0xFFFF || length == 0) {
 		hw_dbg(hw, "NVM PBA number section invalid length\n");
 		return IXGBE_ERR_PBA_SECTION;
 	}
 	/* check if pba_num buffer is big enough */
 	if (pba_num_size  < (((u32)length * 2) - 1)) {
 		hw_dbg(hw, "PBA string buffer too small\n");
 		return IXGBE_ERR_NO_SPACE;
 	}
 	/* trim pba length from start of string */
 	pba_ptr++;
 	length--;
 	for (offset = 0; offset < length; offset++) {
 		ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
 		if (ret_val) {
 			hw_dbg(hw, "NVM Read Error\n");
 			return ret_val;
 		}
 		pba_num[offset * 2] = (u8)(data >> 8);
 		pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
 	}
 	pba_num[offset * 2] = '\0';
 	return 0;
 }
 /**
  *  ixgbe_get_mac_addr_generic - Generic get MAC address
  *  @hw: pointer to hardware structure
  *  @mac_addr: Adapter MAC address
  *
  *  Reads the adapter's MAC address from first Receive Address Register (RAR0)
  *  A reset of the adapter must be performed prior to calling this function
  *  in order for the MAC address to have been loaded from the EEPROM into RAR0
  **/
 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
 {
 	u32 rar_high;
 	u32 rar_low;
 	u16 i;
 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
 	rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
 	for (i = 0; i < 4; i++)
 		mac_addr[i] = (u8)(rar_low >> (i*8));
 	for (i = 0; i < 2; i++)
 		mac_addr[i+4] = (u8)(rar_high >> (i*8));
 	return 0;
 }
 enum ixgbe_bus_width ixgbe_convert_bus_width(u16 link_status)
 {
 	switch (link_status & IXGBE_PCI_LINK_WIDTH) {
 	case IXGBE_PCI_LINK_WIDTH_1:
 		return ixgbe_bus_width_pcie_x1;
 	case IXGBE_PCI_LINK_WIDTH_2:
 		return ixgbe_bus_width_pcie_x2;
 	case IXGBE_PCI_LINK_WIDTH_4:
 		return ixgbe_bus_width_pcie_x4;
 	case IXGBE_PCI_LINK_WIDTH_8:
 		return ixgbe_bus_width_pcie_x8;
 	default:
 		return ixgbe_bus_width_unknown;
 	}
 }
 enum ixgbe_bus_speed ixgbe_convert_bus_speed(u16 link_status)
 {
 	switch (link_status & IXGBE_PCI_LINK_SPEED) {
 	case IXGBE_PCI_LINK_SPEED_2500:
 		return ixgbe_bus_speed_2500;
 	case IXGBE_PCI_LINK_SPEED_5000:
 		return ixgbe_bus_speed_5000;
 	case IXGBE_PCI_LINK_SPEED_8000:
 		return ixgbe_bus_speed_8000;
 	default:
 		return ixgbe_bus_speed_unknown;
 	}
 }
 /**
  *  ixgbe_get_bus_info_generic - Generic set PCI bus info
  *  @hw: pointer to hardware structure
  *
  *  Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
  **/
 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_adapter *adapter = hw->back;
 	struct ixgbe_mac_info *mac = &hw->mac;
 	u16 link_status;
 	hw->bus.type = ixgbe_bus_type_pci_express;
 	/* Get the negotiated link width and speed from PCI config space */
 	pci_read_config_word(adapter->pdev, IXGBE_PCI_LINK_STATUS,
 	                     &link_status);
 	hw->bus.width = ixgbe_convert_bus_width(link_status);
 	hw->bus.speed = ixgbe_convert_bus_speed(link_status);
 	mac->ops.set_lan_id(hw);
 	return 0;
 }
 /**
  *  ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
  *  @hw: pointer to the HW structure
  *
  *  Determines the LAN function id by reading memory-mapped registers
  *  and swaps the port value if requested.
  **/
 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
 {
 	struct ixgbe_bus_info *bus = &hw->bus;
 	u32 reg;
 	reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
 	bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
 	bus->lan_id = bus->func;
 	/* check for a port swap */
 	reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
 	if (reg & IXGBE_FACTPS_LFS)
 		bus->func ^= 0x1;
 }
 /**
  *  ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
  *  @hw: pointer to hardware structure
  *
  *  Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
  *  disables transmit and receive units. The adapter_stopped flag is used by
  *  the shared code and drivers to determine if the adapter is in a stopped
  *  state and should not touch the hardware.
  **/
 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
 {
 	u32 reg_val;
 	u16 i;
 	/*
 	 * Set the adapter_stopped flag so other driver functions stop touching
 	 * the hardware
 	 */
 	hw->adapter_stopped = true;
 	/* Disable the receive unit */
 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
 	/* Clear interrupt mask to stop interrupts from being generated */
 	IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
 	/* Clear any pending interrupts, flush previous writes */
 	IXGBE_READ_REG(hw, IXGBE_EICR);
 	/* Disable the transmit unit.  Each queue must be disabled. */
 	for (i = 0; i < hw->mac.max_tx_queues; i++)
 		IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
 	/* Disable the receive unit by stopping each queue */
 	for (i = 0; i < hw->mac.max_rx_queues; i++) {
 		reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 		reg_val &= ~IXGBE_RXDCTL_ENABLE;
 		reg_val |= IXGBE_RXDCTL_SWFLSH;
 		IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
 	}
 	/* flush all queues disables */
 	IXGBE_WRITE_FLUSH(hw);
 	usleep_range(1000, 2000);
 	/*
 	 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
 	 * access and verify no pending requests
 	 */
 	return ixgbe_disable_pcie_master(hw);
 }
 /**
  *  ixgbe_led_on_generic - Turns on the software controllable LEDs.
  *  @hw: pointer to hardware structure
  *  @index: led number to turn on
  **/
 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
 {
 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 	/* To turn on the LED, set mode to ON. */
 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
 	led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 	IXGBE_WRITE_FLUSH(hw);
 	return 0;
 }
 /**
  *  ixgbe_led_off_generic - Turns off the software controllable LEDs.
  *  @hw: pointer to hardware structure
  *  @index: led number to turn off
  **/
 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
 {
 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 	/* To turn off the LED, set mode to OFF. */
 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
 	led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 	IXGBE_WRITE_FLUSH(hw);
 	return 0;
 }
 /**
  *  ixgbe_init_eeprom_params_generic - Initialize EEPROM params
  *  @hw: pointer to hardware structure
  *
  *  Initializes the EEPROM parameters ixgbe_eeprom_info within the
  *  ixgbe_hw struct in order to set up EEPROM access.
  **/
 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
 	u32 eec;
 	u16 eeprom_size;
 	if (eeprom->type == ixgbe_eeprom_uninitialized) {
 		eeprom->type = ixgbe_eeprom_none;
 		/* Set default semaphore delay to 10ms which is a well
 		 * tested value */
 		eeprom->semaphore_delay = 10;
 		/* Clear EEPROM page size, it will be initialized as needed */
 		eeprom->word_page_size = 0;
 		/*
 		 * Check for EEPROM present first.
 		 * If not present leave as none
 		 */
 		eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 		if (eec & IXGBE_EEC_PRES) {
 			eeprom->type = ixgbe_eeprom_spi;
 			/*
 			 * SPI EEPROM is assumed here.  This code would need to
 			 * change if a future EEPROM is not SPI.
 			 */
 			eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
 					    IXGBE_EEC_SIZE_SHIFT);
 			eeprom->word_size = 1 << (eeprom_size +
 						  IXGBE_EEPROM_WORD_SIZE_SHIFT);
 		}
 		if (eec & IXGBE_EEC_ADDR_SIZE)
 			eeprom->address_bits = 16;
 		else
 			eeprom->address_bits = 8;
 		hw_dbg(hw, "Eeprom params: type = %d, size = %d, address bits: "
 			  "%d\n", eeprom->type, eeprom->word_size,
 			  eeprom->address_bits);
 	}
 	return 0;
 }
 /**
  *  ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
  *  @hw: pointer to hardware structure
  *  @offset: offset within the EEPROM to write
  *  @words: number of words
  *  @data: 16 bit word(s) to write to EEPROM
  *
  *  Reads 16 bit word(s) from EEPROM through bit-bang method
  **/
 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
 					       u16 words, u16 *data)
 {
 	s32 status = 0;
 	u16 i, count;
 	hw->eeprom.ops.init_params(hw);
 	if (words == 0) {
 		status = IXGBE_ERR_INVALID_ARGUMENT;
 		goto out;
 	}
 	if (offset + words > hw->eeprom.word_size) {
 		status = IXGBE_ERR_EEPROM;
 		goto out;
 	}
 	/*
 	 * The EEPROM page size cannot be queried from the chip. We do lazy
 	 * initialization. It is worth to do that when we write large buffer.
 	 */
 	if ((hw->eeprom.word_page_size == 0) &&
 	    (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
 		ixgbe_detect_eeprom_page_size_generic(hw, offset);
 	/*
 	 * We cannot hold synchronization semaphores for too long
 	 * to avoid other entity starvation. However it is more efficient
 	 * to read in bursts than synchronizing access for each word.
 	 */
 	for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
 		count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
 			 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
 		status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
 							    count, &data[i]);
 		if (status != 0)
 			break;
 	}
 out:
 	return status;
 }
 /**
  *  ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
  *  @hw: pointer to hardware structure
  *  @offset: offset within the EEPROM to be written to
  *  @words: number of word(s)
  *  @data: 16 bit word(s) to be written to the EEPROM
  *
  *  If ixgbe_eeprom_update_checksum is not called after this function, the
  *  EEPROM will most likely contain an invalid checksum.
  **/
 static s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
 					      u16 words, u16 *data)
 {
 	s32 status;
 	u16 word;
 	u16 page_size;
 	u16 i;
 	u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
 	/* Prepare the EEPROM for writing  */
 	status = ixgbe_acquire_eeprom(hw);
 	if (status == 0) {
 		if (ixgbe_ready_eeprom(hw) != 0) {
 			ixgbe_release_eeprom(hw);
 			status = IXGBE_ERR_EEPROM;
 		}
 	}
 	if (status == 0) {
 		for (i = 0; i < words; i++) {
 			ixgbe_standby_eeprom(hw);
 			/*  Send the WRITE ENABLE command (8 bit opcode )  */
 			ixgbe_shift_out_eeprom_bits(hw,
 						  IXGBE_EEPROM_WREN_OPCODE_SPI,
 						  IXGBE_EEPROM_OPCODE_BITS);
 			ixgbe_standby_eeprom(hw);
 			/*
 			 * Some SPI eeproms use the 8th address bit embedded
 			 * in the opcode
 			 */
 			if ((hw->eeprom.address_bits == 8) &&
 			    ((offset + i) >= 128))
 				write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
 			/* Send the Write command (8-bit opcode + addr) */
 			ixgbe_shift_out_eeprom_bits(hw, write_opcode,
 						    IXGBE_EEPROM_OPCODE_BITS);
 			ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
 						    hw->eeprom.address_bits);
 			page_size = hw->eeprom.word_page_size;
 			/* Send the data in burst via SPI*/
 			do {
 				word = data[i];
 				word = (word >> 8) | (word << 8);
 				ixgbe_shift_out_eeprom_bits(hw, word, 16);
 				if (page_size == 0)
 					break;
 				/* do not wrap around page */
 				if (((offset + i) & (page_size - 1)) ==
 				    (page_size - 1))
 					break;
 			} while (++i < words);
 			ixgbe_standby_eeprom(hw);
 			usleep_range(10000, 20000);
 		}
 		/* Done with writing - release the EEPROM */
 		ixgbe_release_eeprom(hw);
 	}
 	return status;
 }
 /**
  *  ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
  *  @hw: pointer to hardware structure
  *  @offset: offset within the EEPROM to be written to
  *  @data: 16 bit word to be written to the EEPROM
  *
  *  If ixgbe_eeprom_update_checksum is not called after this function, the
  *  EEPROM will most likely contain an invalid checksum.
  **/
 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
 {
 	s32 status;
 	hw->eeprom.ops.init_params(hw);
 	if (offset >= hw->eeprom.word_size) {
 		status = IXGBE_ERR_EEPROM;
 		goto out;
 	}
 	status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
 out:
 	return status;
 }
 /**
  *  ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
  *  @hw: pointer to hardware structure
  *  @offset: offset within the EEPROM to be read
  *  @words: number of word(s)
  *  @data: read 16 bit words(s) from EEPROM
  *
  *  Reads 16 bit word(s) from EEPROM through bit-bang method
  **/
 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
 					      u16 words, u16 *data)
 {
 	s32 status = 0;
 	u16 i, count;
 	hw->eeprom.ops.init_params(hw);
 	if (words == 0) {
 		status = IXGBE_ERR_INVALID_ARGUMENT;
 		goto out;
 	}
 	if (offset + words > hw->eeprom.word_size) {
 		status = IXGBE_ERR_EEPROM;
 		goto out;
 	}
 	/*
 	 * We cannot hold synchronization semaphores for too long
 	 * to avoid other entity starvation. However it is more efficient
 	 * to read in bursts than synchronizing access for each word.
 	 */
 	for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
 		count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
 			 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
 		status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
 							   count, &data[i]);
 		if (status != 0)
 			break;
 	}
 out:
 	return status;
 }
 /**
  *  ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
  *  @hw: pointer to hardware structure
  *  @offset: offset within the EEPROM to be read
  *  @words: number of word(s)
  *  @data: read 16 bit word(s) from EEPROM
  *
  *  Reads 16 bit word(s) from EEPROM through bit-bang method
  **/
 static s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
 					     u16 words, u16 *data)
 {
 	s32 status;
 	u16 word_in;
 	u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
 	u16 i;
 	/* Prepare the EEPROM for reading  */
 	status = ixgbe_acquire_eeprom(hw);
 	if (status == 0) {
 		if (ixgbe_ready_eeprom(hw) != 0) {
 			ixgbe_release_eeprom(hw);
 			status = IXGBE_ERR_EEPROM;
 		}
 	}
 	if (status == 0) {
 		for (i = 0; i < words; i++) {
 			ixgbe_standby_eeprom(hw);
 			/*
 			 * Some SPI eeproms use the 8th address bit embedded
 			 * in the opcode
 			 */
 			if ((hw->eeprom.address_bits == 8) &&
 			    ((offset + i) >= 128))
 				read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
 			/* Send the READ command (opcode + addr) */
 			ixgbe_shift_out_eeprom_bits(hw, read_opcode,
 						    IXGBE_EEPROM_OPCODE_BITS);
 			ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
 						    hw->eeprom.address_bits);
 			/* Read the data. */
 			word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
 			data[i] = (word_in >> 8) | (word_in << 8);
 		}
 		/* End this read operation */
 		ixgbe_release_eeprom(hw);
 	}
 	return status;
 }
 /**
  *  ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
  *  @hw: pointer to hardware structure
  *  @offset: offset within the EEPROM to be read
  *  @data: read 16 bit value from EEPROM
  *
  *  Reads 16 bit value from EEPROM through bit-bang method
  **/
 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
 				       u16 *data)
 {
 	s32 status;
 	hw->eeprom.ops.init_params(hw);
 	if (offset >= hw->eeprom.word_size) {
 		status = IXGBE_ERR_EEPROM;
 		goto out;
 	}
 	status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
 out:
 	return status;
 }
 /**
  *  ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
  *  @hw: pointer to hardware structure
  *  @offset: offset of word in the EEPROM to read
  *  @words: number of word(s)
  *  @data: 16 bit word(s) from the EEPROM
  *
  *  Reads a 16 bit word(s) from the EEPROM using the EERD register.
  **/
 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
 				   u16 words, u16 *data)
 {
 	u32 eerd;
 	s32 status = 0;
 	u32 i;
 	hw->eeprom.ops.init_params(hw);
 	if (words == 0) {
 		status = IXGBE_ERR_INVALID_ARGUMENT;
 		goto out;
 	}
 	if (offset >= hw->eeprom.word_size) {
 		status = IXGBE_ERR_EEPROM;
 		goto out;
 	}
 	for (i = 0; i < words; i++) {
 		eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
 		       IXGBE_EEPROM_RW_REG_START;
 		IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
 		status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
 		if (status == 0) {
 			data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
 				   IXGBE_EEPROM_RW_REG_DATA);
 		} else {
 			hw_dbg(hw, "Eeprom read timed out\n");
 			goto out;
 		}
 	}
 out:
 	return status;
 }
 /**
  *  ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
  *  @hw: pointer to hardware structure
  *  @offset: offset within the EEPROM to be used as a scratch pad
  *
  *  Discover EEPROM page size by writing marching data at given offset.
  *  This function is called only when we are writing a new large buffer
  *  at given offset so the data would be overwritten anyway.
  **/
 static s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
 						 u16 offset)
 {
 	u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
 	s32 status = 0;
 	u16 i;
 	for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
 		data[i] = i;
 	hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
 	status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
 					     IXGBE_EEPROM_PAGE_SIZE_MAX, data);
 	hw->eeprom.word_page_size = 0;
 	if (status != 0)
 		goto out;
 	status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
 	if (status != 0)
 		goto out;
 	/*
 	 * When writing in burst more than the actual page size
 	 * EEPROM address wraps around current page.
 	 */
 	hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
 	hw_dbg(hw, "Detected EEPROM page size = %d words.",
 	       hw->eeprom.word_page_size);
 out:
 	return status;
 }
 /**
  *  ixgbe_read_eerd_generic - Read EEPROM word using EERD
  *  @hw: pointer to hardware structure
  *  @offset: offset of  word in the EEPROM to read
  *  @data: word read from the EEPROM
  *
  *  Reads a 16 bit word from the EEPROM using the EERD register.
  **/
 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
 {
 	return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
 }
 /**
  *  ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
  *  @hw: pointer to hardware structure
  *  @offset: offset of  word in the EEPROM to write
  *  @words: number of words
  *  @data: word(s) write to the EEPROM
  *
  *  Write a 16 bit word(s) to the EEPROM using the EEWR register.
  **/
 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
 				    u16 words, u16 *data)
 {
 	u32 eewr;
 	s32 status = 0;
 	u16 i;
 	hw->eeprom.ops.init_params(hw);
 	if (words == 0) {
 		status = IXGBE_ERR_INVALID_ARGUMENT;
 		goto out;
 	}
 	if (offset >= hw->eeprom.word_size) {
 		status = IXGBE_ERR_EEPROM;
 		goto out;
 	}
 	for (i = 0; i < words; i++) {
 		eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
 		       (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
 		       IXGBE_EEPROM_RW_REG_START;
 		status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
 		if (status != 0) {
 			hw_dbg(hw, "Eeprom write EEWR timed out\n");
 			goto out;
 		}
 		IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
 		status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
 		if (status != 0) {
 			hw_dbg(hw, "Eeprom write EEWR timed out\n");
 			goto out;
 		}
 	}
 out:
 	return status;
 }
 /**
  *  ixgbe_write_eewr_generic - Write EEPROM word using EEWR
  *  @hw: pointer to hardware structure
  *  @offset: offset of  word in the EEPROM to write
  *  @data: word write to the EEPROM
  *
  *  Write a 16 bit word to the EEPROM using the EEWR register.
  **/
 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
 {
 	return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
 }
 /**
  *  ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
  *  @hw: pointer to hardware structure
  *  @ee_reg: EEPROM flag for polling
  *
  *  Polls the status bit (bit 1) of the EERD or EEWR to determine when the
  *  read or write is done respectively.
  **/
 static s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
 {
 	u32 i;
 	u32 reg;
 	s32 status = IXGBE_ERR_EEPROM;
 	for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
 		if (ee_reg == IXGBE_NVM_POLL_READ)
 			reg = IXGBE_READ_REG(hw, IXGBE_EERD);
 		else
 			reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
 		if (reg & IXGBE_EEPROM_RW_REG_DONE) {
 			status = 0;
 			break;
 		}
 		udelay(5);
 	}
 	return status;
 }
 /**
  *  ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
  *  @hw: pointer to hardware structure
  *
  *  Prepares EEPROM for access using bit-bang method. This function should
  *  be called before issuing a command to the EEPROM.
  **/
 static s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
 {
 	s32 status = 0;
 	u32 eec;
 	u32 i;
 	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) != 0)
 		status = IXGBE_ERR_SWFW_SYNC;
 	if (status == 0) {
 		eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 		/* Request EEPROM Access */
 		eec |= IXGBE_EEC_REQ;
 		IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
 		for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
 			eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 			if (eec & IXGBE_EEC_GNT)
 				break;
 			udelay(5);
 		}
 		/* Release if grant not acquired */
 		if (!(eec & IXGBE_EEC_GNT)) {
 			eec &= ~IXGBE_EEC_REQ;
 			IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
 			hw_dbg(hw, "Could not acquire EEPROM grant\n");
 			hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 			status = IXGBE_ERR_EEPROM;
 		}
 		/* Setup EEPROM for Read/Write */
 		if (status == 0) {
 			/* Clear CS and SK */
 			eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
 			IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
 			IXGBE_WRITE_FLUSH(hw);
 			udelay(1);
 		}
 	}
 	return status;
 }
 /**
  *  ixgbe_get_eeprom_semaphore - Get hardware semaphore
  *  @hw: pointer to hardware structure
  *
  *  Sets the hardware semaphores so EEPROM access can occur for bit-bang method
  **/
 static s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
 {
 	s32 status = IXGBE_ERR_EEPROM;
 	u32 timeout = 2000;
 	u32 i;
 	u32 swsm;
 	/* Get SMBI software semaphore between device drivers first */
 	for (i = 0; i < timeout; i++) {
 		/*
 		 * If the SMBI bit is 0 when we read it, then the bit will be
 		 * set and we have the semaphore
 		 */
 		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 		if (!(swsm & IXGBE_SWSM_SMBI)) {
 			status = 0;
 			break;
 		}
 		udelay(50);
 	}
 	if (i == timeout) {
 		hw_dbg(hw, "Driver can't access the Eeprom - SMBI Semaphore "
 		       "not granted.\n");
 		/*
 		 * this release is particularly important because our attempts
 		 * above to get the semaphore may have succeeded, and if there
 		 * was a timeout, we should unconditionally clear the semaphore
 		 * bits to free the driver to make progress
 		 */
 		ixgbe_release_eeprom_semaphore(hw);
 		udelay(50);
 		/*
 		 * one last try
 		 * If the SMBI bit is 0 when we read it, then the bit will be
 		 * set and we have the semaphore
 		 */
 		swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 		if (!(swsm & IXGBE_SWSM_SMBI))
 			status = 0;
 	}
 	/* Now get the semaphore between SW/FW through the SWESMBI bit */
 	if (status == 0) {
 		for (i = 0; i < timeout; i++) {
 			swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 			/* Set the SW EEPROM semaphore bit to request access */
 			swsm |= IXGBE_SWSM_SWESMBI;
 			IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 			/*
 			 * If we set the bit successfully then we got the
 			 * semaphore.
 			 */
 			swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 			if (swsm & IXGBE_SWSM_SWESMBI)
 				break;
 			udelay(50);
 		}
 		/*
 		 * Release semaphores and return error if SW EEPROM semaphore
 		 * was not granted because we don't have access to the EEPROM
 		 */
 		if (i >= timeout) {
 			hw_dbg(hw, "SWESMBI Software EEPROM semaphore "
 			       "not granted.\n");
 			ixgbe_release_eeprom_semaphore(hw);
 			status = IXGBE_ERR_EEPROM;
 		}
 	} else {
 		hw_dbg(hw, "Software semaphore SMBI between device drivers "
 		       "not granted.\n");
 	}
 	return status;
 }
 /**
  *  ixgbe_release_eeprom_semaphore - Release hardware semaphore
  *  @hw: pointer to hardware structure
  *
  *  This function clears hardware semaphore bits.
  **/
 static void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
 {
 	u32 swsm;
 	swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
 	/* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
 	swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
 	IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
 	IXGBE_WRITE_FLUSH(hw);
 }
 /**
  *  ixgbe_ready_eeprom - Polls for EEPROM ready
  *  @hw: pointer to hardware structure
  **/
 static s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
 {
 	s32 status = 0;
 	u16 i;
 	u8 spi_stat_reg;
 	/*
 	 * Read "Status Register" repeatedly until the LSB is cleared.  The
 	 * EEPROM will signal that the command has been completed by clearing
 	 * bit 0 of the internal status register.  If it's not cleared within
 	 * 5 milliseconds, then error out.
 	 */
 	for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
 		ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
 		                            IXGBE_EEPROM_OPCODE_BITS);
 		spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
 		if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
 			break;
 		udelay(5);
 		ixgbe_standby_eeprom(hw);
 	}
 	/*
 	 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
 	 * devices (and only 0-5mSec on 5V devices)
 	 */
 	if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
 		hw_dbg(hw, "SPI EEPROM Status error\n");
 		status = IXGBE_ERR_EEPROM;
 	}
 	return status;
 }
 /**
  *  ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
  *  @hw: pointer to hardware structure
  **/
 static void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
 {
 	u32 eec;
 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 	/* Toggle CS to flush commands */
 	eec |= IXGBE_EEC_CS;
 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
 	IXGBE_WRITE_FLUSH(hw);
 	udelay(1);
 	eec &= ~IXGBE_EEC_CS;
 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
 	IXGBE_WRITE_FLUSH(hw);
 	udelay(1);
 }
 /**
  *  ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
  *  @hw: pointer to hardware structure
  *  @data: data to send to the EEPROM
  *  @count: number of bits to shift out
  **/
 static void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
                                         u16 count)
 {
 	u32 eec;
 	u32 mask;
 	u32 i;
 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 	/*
 	 * Mask is used to shift "count" bits of "data" out to the EEPROM
 	 * one bit at a time.  Determine the starting bit based on count
 	 */
 	mask = 0x01 << (count - 1);
 	for (i = 0; i < count; i++) {
 		/*
 		 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
 		 * "1", and then raising and then lowering the clock (the SK
 		 * bit controls the clock input to the EEPROM).  A "0" is
 		 * shifted out to the EEPROM by setting "DI" to "0" and then
 		 * raising and then lowering the clock.
 		 */
 		if (data & mask)
 			eec |= IXGBE_EEC_DI;
 		else
 			eec &= ~IXGBE_EEC_DI;
 		IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
 		IXGBE_WRITE_FLUSH(hw);
 		udelay(1);
 		ixgbe_raise_eeprom_clk(hw, &eec);
 		ixgbe_lower_eeprom_clk(hw, &eec);
 		/*
 		 * Shift mask to signify next bit of data to shift in to the
 		 * EEPROM
 		 */
 		mask = mask >> 1;
 	}
 	/* We leave the "DI" bit set to "0" when we leave this routine. */
 	eec &= ~IXGBE_EEC_DI;
 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
 	IXGBE_WRITE_FLUSH(hw);
 }
 /**
  *  ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
  *  @hw: pointer to hardware structure
  **/
 static u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
 {
 	u32 eec;
 	u32 i;
 	u16 data = 0;
 	/*
 	 * In order to read a register from the EEPROM, we need to shift
 	 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
 	 * the clock input to the EEPROM (setting the SK bit), and then reading
 	 * the value of the "DO" bit.  During this "shifting in" process the
 	 * "DI" bit should always be clear.
 	 */
 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 	eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
 	for (i = 0; i < count; i++) {
 		data = data << 1;
 		ixgbe_raise_eeprom_clk(hw, &eec);
 		eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 		eec &= ~(IXGBE_EEC_DI);
 		if (eec & IXGBE_EEC_DO)
 			data |= 1;
 		ixgbe_lower_eeprom_clk(hw, &eec);
 	}
 	return data;
 }
 /**
  *  ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
  *  @hw: pointer to hardware structure
  *  @eec: EEC register's current value
  **/
 static void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
 {
 	/*
 	 * Raise the clock input to the EEPROM
 	 * (setting the SK bit), then delay
 	 */
 	*eec = *eec | IXGBE_EEC_SK;
 	IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
 	IXGBE_WRITE_FLUSH(hw);
 	udelay(1);
 }
 /**
  *  ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
  *  @hw: pointer to hardware structure
  *  @eecd: EECD's current value
  **/
 static void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
 {
 	/*
 	 * Lower the clock input to the EEPROM (clearing the SK bit), then
 	 * delay
 	 */
 	*eec = *eec & ~IXGBE_EEC_SK;
 	IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
 	IXGBE_WRITE_FLUSH(hw);
 	udelay(1);
 }
 /**
  *  ixgbe_release_eeprom - Release EEPROM, release semaphores
  *  @hw: pointer to hardware structure
  **/
 static void ixgbe_release_eeprom(struct ixgbe_hw *hw)
 {
 	u32 eec;
 	eec = IXGBE_READ_REG(hw, IXGBE_EEC);
 	eec |= IXGBE_EEC_CS;  /* Pull CS high */
 	eec &= ~IXGBE_EEC_SK; /* Lower SCK */
 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
 	IXGBE_WRITE_FLUSH(hw);
 	udelay(1);
 	/* Stop requesting EEPROM access */
 	eec &= ~IXGBE_EEC_REQ;
 	IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
 	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
 	/*
 	 * Delay before attempt to obtain semaphore again to allow FW
 	 * access. semaphore_delay is in ms we need us for usleep_range
 	 */
 	usleep_range(hw->eeprom.semaphore_delay * 1000,
 		     hw->eeprom.semaphore_delay * 2000);
 }
 /**
  *  ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
  *  @hw: pointer to hardware structure
  **/
 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
 {
 	u16 i;
 	u16 j;
 	u16 checksum = 0;
 	u16 length = 0;
 	u16 pointer = 0;
 	u16 word = 0;
 	/* Include 0x0-0x3F in the checksum */
 	for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
 		if (hw->eeprom.ops.read(hw, i, &word) != 0) {
 			hw_dbg(hw, "EEPROM read failed\n");
 			break;
 		}
 		checksum += word;
 	}
 	/* Include all data from pointers except for the fw pointer */
 	for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
 		hw->eeprom.ops.read(hw, i, &pointer);
 		/* Make sure the pointer seems valid */
 		if (pointer != 0xFFFF && pointer != 0) {
 			hw->eeprom.ops.read(hw, pointer, &length);
 			if (length != 0xFFFF && length != 0) {
 				for (j = pointer+1; j <= pointer+length; j++) {
 					hw->eeprom.ops.read(hw, j, &word);
 					checksum += word;
 				}
 			}
 		}
 	}
 	checksum = (u16)IXGBE_EEPROM_SUM - checksum;
 	return checksum;
 }
 /**
  *  ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
  *  @hw: pointer to hardware structure
  *  @checksum_val: calculated checksum
  *
  *  Performs checksum calculation and validates the EEPROM checksum.  If the
  *  caller does not need checksum_val, the value can be NULL.
  **/
 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
                                            u16 *checksum_val)
 {
 	s32 status;
 	u16 checksum;
 	u16 read_checksum = 0;
 	/*
 	 * Read the first word from the EEPROM. If this times out or fails, do
 	 * not continue or we could be in for a very long wait while every
 	 * EEPROM read fails
 	 */
 	status = hw->eeprom.ops.read(hw, 0, &checksum);
 	if (status == 0) {
 		checksum = hw->eeprom.ops.calc_checksum(hw);
 		hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
 		/*
 		 * Verify read checksum from EEPROM is the same as
 		 * calculated checksum
 		 */
 		if (read_checksum != checksum)
 			status = IXGBE_ERR_EEPROM_CHECKSUM;
 		/* If the user cares, return the calculated checksum */
 		if (checksum_val)
 			*checksum_val = checksum;
 	} else {
 		hw_dbg(hw, "EEPROM read failed\n");
 	}
 	return status;
 }
 /**
  *  ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
  *  @hw: pointer to hardware structure
  **/
 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
 {
 	s32 status;
 	u16 checksum;
 	/*
 	 * Read the first word from the EEPROM. If this times out or fails, do
 	 * not continue or we could be in for a very long wait while every
 	 * EEPROM read fails
 	 */
 	status = hw->eeprom.ops.read(hw, 0, &checksum);
 	if (status == 0) {
 		checksum = hw->eeprom.ops.calc_checksum(hw);
 		status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
 					      checksum);
 	} else {
 		hw_dbg(hw, "EEPROM read failed\n");
 	}
 	return status;
 }
 /**
  *  ixgbe_set_rar_generic - Set Rx address register
  *  @hw: pointer to hardware structure
  *  @index: Receive address register to write
  *  @addr: Address to put into receive address register
  *  @vmdq: VMDq "set" or "pool" index
  *  @enable_addr: set flag that address is active
  *
  *  Puts an ethernet address into a receive address register.
  **/
 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
                           u32 enable_addr)
 {
 	u32 rar_low, rar_high;
 	u32 rar_entries = hw->mac.num_rar_entries;
 	/* Make sure we are using a valid rar index range */
 	if (index >= rar_entries) {
 		hw_dbg(hw, "RAR index %d is out of range.\n", index);
 		return IXGBE_ERR_INVALID_ARGUMENT;
 	}
 	/* setup VMDq pool selection before this RAR gets enabled */
 	hw->mac.ops.set_vmdq(hw, index, vmdq);
 	/*
 	 * HW expects these in little endian so we reverse the byte
 	 * order from network order (big endian) to little endian
 	 */
 	rar_low = ((u32)addr[0] |
 		   ((u32)addr[1] << 8) |
 		   ((u32)addr[2] << 16) |
 		   ((u32)addr[3] << 24));
 	/*
 	 * Some parts put the VMDq setting in the extra RAH bits,
 	 * so save everything except the lower 16 bits that hold part
 	 * of the address and the address valid bit.
 	 */
 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
 	rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
 	rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
 	if (enable_addr != 0)
 		rar_high |= IXGBE_RAH_AV;
 	IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
 	IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
 	return 0;
 }
 /**
  *  ixgbe_clear_rar_generic - Remove Rx address register
  *  @hw: pointer to hardware structure
  *  @index: Receive address register to write
  *
  *  Clears an ethernet address from a receive address register.
  **/
 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
 {
 	u32 rar_high;
 	u32 rar_entries = hw->mac.num_rar_entries;
 	/* Make sure we are using a valid rar index range */
 	if (index >= rar_entries) {
 		hw_dbg(hw, "RAR index %d is out of range.\n", index);
 		return IXGBE_ERR_INVALID_ARGUMENT;
 	}
 	/*
 	 * Some parts put the VMDq setting in the extra RAH bits,
 	 * so save everything except the lower 16 bits that hold part
 	 * of the address and the address valid bit.
 	 */
 	rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
 	rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
 	IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
 	IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
 	/* clear VMDq pool/queue selection for this RAR */
 	hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
 	return 0;
 }
 /**
  *  ixgbe_init_rx_addrs_generic - Initializes receive address filters.
  *  @hw: pointer to hardware structure
  *
  *  Places the MAC address in receive address register 0 and clears the rest
  *  of the receive address registers. Clears the multicast table. Assumes
  *  the receiver is in reset when the routine is called.
  **/
 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
 {
 	u32 i;
 	u32 rar_entries = hw->mac.num_rar_entries;
 	/*
 	 * If the current mac address is valid, assume it is a software override
 	 * to the permanent address.
 	 * Otherwise, use the permanent address from the eeprom.
 	 */
 	if (!is_valid_ether_addr(hw->mac.addr)) {
 		/* Get the MAC address from the RAR0 for later reference */
 		hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
 		hw_dbg(hw, " Keeping Current RAR0 Addr =%pM\n", hw->mac.addr);
 	} else {
 		/* Setup the receive address. */
 		hw_dbg(hw, "Overriding MAC Address in RAR[0]\n");
 		hw_dbg(hw, " New MAC Addr =%pM\n", hw->mac.addr);
 		hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
 		/*  clear VMDq pool/queue selection for RAR 0 */
 		hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
 	}
 	hw->addr_ctrl.overflow_promisc = 0;
 	hw->addr_ctrl.rar_used_count = 1;
 	/* Zero out the other receive addresses. */
 	hw_dbg(hw, "Clearing RAR[1-%d]\n", rar_entries - 1);
 	for (i = 1; i < rar_entries; i++) {
 		IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
 		IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
 	}
 	/* Clear the MTA */
 	hw->addr_ctrl.mta_in_use = 0;
 	IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
 	hw_dbg(hw, " Clearing MTA\n");
 	for (i = 0; i < hw->mac.mcft_size; i++)
 		IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
 	if (hw->mac.ops.init_uta_tables)
 		hw->mac.ops.init_uta_tables(hw);
 	return 0;
 }
 /**
  *  ixgbe_mta_vector - Determines bit-vector in multicast table to set
  *  @hw: pointer to hardware structure
  *  @mc_addr: the multicast address
  *
  *  Extracts the 12 bits, from a multicast address, to determine which
  *  bit-vector to set in the multicast table. The hardware uses 12 bits, from
  *  incoming rx multicast addresses, to determine the bit-vector to check in
  *  the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
  *  by the MO field of the MCSTCTRL. The MO field is set during initialization
  *  to mc_filter_type.
  **/
 static s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
 {
 	u32 vector = 0;
 	switch (hw->mac.mc_filter_type) {
 	case 0:   /* use bits [47:36] of the address */
 		vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
 		break;
 	case 1:   /* use bits [46:35] of the address */
 		vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
 		break;
 	case 2:   /* use bits [45:34] of the address */
 		vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
 		break;
 	case 3:   /* use bits [43:32] of the address */
 		vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
 		break;
 	default:  /* Invalid mc_filter_type */
 		hw_dbg(hw, "MC filter type param set incorrectly\n");
 		break;
 	}
 	/* vector can only be 12-bits or boundary will be exceeded */
 	vector &= 0xFFF;
 	return vector;
 }
 /**
  *  ixgbe_set_mta - Set bit-vector in multicast table
  *  @hw: pointer to hardware structure
  *  @hash_value: Multicast address hash value
  *
  *  Sets the bit-vector in the multicast table.
  **/
 static void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
 {
 	u32 vector;
 	u32 vector_bit;
 	u32 vector_reg;
 	hw->addr_ctrl.mta_in_use++;
 	vector = ixgbe_mta_vector(hw, mc_addr);
 	hw_dbg(hw, " bit-vector = 0x%03X\n", vector);
 	/*
 	 * The MTA is a register array of 128 32-bit registers. It is treated
 	 * like an array of 4096 bits.  We want to set bit
 	 * BitArray[vector_value]. So we figure out what register the bit is
 	 * in, read it, OR in the new bit, then write back the new value.  The
 	 * register is determined by the upper 7 bits of the vector value and
 	 * the bit within that register are determined by the lower 5 bits of
 	 * the value.
 	 */
 	vector_reg = (vector >> 5) & 0x7F;
 	vector_bit = vector & 0x1F;
 	hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
 }
 /**
  *  ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
  *  @hw: pointer to hardware structure
  *  @netdev: pointer to net device structure
  *
  *  The given list replaces any existing list. Clears the MC addrs from receive
  *  address registers and the multicast table. Uses unused receive address
  *  registers for the first multicast addresses, and hashes the rest into the
  *  multicast table.
  **/
 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw,
 				      struct net_device *netdev)
 {
 	struct netdev_hw_addr *ha;
 	u32 i;
 	/*
 	 * Set the new number of MC addresses that we are being requested to
 	 * use.
 	 */
 	hw->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev);
 	hw->addr_ctrl.mta_in_use = 0;
 	/* Clear mta_shadow */
 	hw_dbg(hw, " Clearing MTA\n");
 	memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
 	/* Update mta shadow */
 	netdev_for_each_mc_addr(ha, netdev) {
 		hw_dbg(hw, " Adding the multicast addresses:\n");
 		ixgbe_set_mta(hw, ha->addr);
 	}
 	/* Enable mta */
 	for (i = 0; i < hw->mac.mcft_size; i++)
 		IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
 				      hw->mac.mta_shadow[i]);
 	if (hw->addr_ctrl.mta_in_use > 0)
 		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
 		                IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
 	hw_dbg(hw, "ixgbe_update_mc_addr_list_generic Complete\n");
 	return 0;
 }
 /**
  *  ixgbe_enable_mc_generic - Enable multicast address in RAR
  *  @hw: pointer to hardware structure
  *
  *  Enables multicast address in RAR and the use of the multicast hash table.
  **/
 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
 	if (a->mta_in_use > 0)
 		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
 		                hw->mac.mc_filter_type);
 	return 0;
 }
 /**
  *  ixgbe_disable_mc_generic - Disable multicast address in RAR
  *  @hw: pointer to hardware structure
  *
  *  Disables multicast address in RAR and the use of the multicast hash table.
  **/
 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
 	if (a->mta_in_use > 0)
 		IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
 	return 0;
 }
 /**
  *  ixgbe_fc_enable_generic - Enable flow control
  *  @hw: pointer to hardware structure
  *
  *  Enable flow control according to the current settings.
  **/
 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
 {
 	s32 ret_val = 0;
 	u32 mflcn_reg, fccfg_reg;
 	u32 reg;
 	u32 fcrtl, fcrth;
 	int i;
 	/*
 	 * Validate the water mark configuration for packet buffer 0.  Zero
 	 * water marks indicate that the packet buffer was not configured
 	 * and the watermarks for packet buffer 0 should always be configured.
 	 */
 	if (!hw->fc.low_water ||
 	    !hw->fc.high_water[0] ||
 	    !hw->fc.pause_time) {
 		hw_dbg(hw, "Invalid water mark configuration\n");
 		ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
 		goto out;
 	}
 	/* Negotiate the fc mode to use */
 	ixgbe_fc_autoneg(hw);
 	/* Disable any previous flow control settings */
 	mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
 	mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
 	fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
 	fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
 	/*
 	 * The possible values of fc.current_mode are:
 	 * 0: Flow control is completely disabled
 	 * 1: Rx flow control is enabled (we can receive pause frames,
 	 *    but not send pause frames).
 	 * 2: Tx flow control is enabled (we can send pause frames but
 	 *    we do not support receiving pause frames).
 	 * 3: Both Rx and Tx flow control (symmetric) are enabled.
 	 * other: Invalid.
 	 */
 	switch (hw->fc.current_mode) {
 	case ixgbe_fc_none:
 		/*
 		 * Flow control is disabled by software override or autoneg.
 		 * The code below will actually disable it in the HW.
 		 */
 		break;
 	case ixgbe_fc_rx_pause:
 		/*
 		 * Rx Flow control is enabled and Tx Flow control is
 		 * disabled by software override. Since there really
 		 * isn't a way to advertise that we are capable of RX
 		 * Pause ONLY, we will advertise that we support both
 		 * symmetric and asymmetric Rx PAUSE.  Later, we will
 		 * disable the adapter's ability to send PAUSE frames.
 		 */
 		mflcn_reg |= IXGBE_MFLCN_RFCE;
 		break;
 	case ixgbe_fc_tx_pause:
 		/*
 		 * Tx Flow control is enabled, and Rx Flow control is
 		 * disabled by software override.
 		 */
 		fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
 		break;
 	case ixgbe_fc_full:
 		/* Flow control (both Rx and Tx) is enabled by SW override. */
 		mflcn_reg |= IXGBE_MFLCN_RFCE;
 		fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
 		break;
 	default:
 		hw_dbg(hw, "Flow control param set incorrectly\n");
 		ret_val = IXGBE_ERR_CONFIG;
 		goto out;
 		break;
 	}
 	/* Set 802.3x based flow control settings. */
 	mflcn_reg |= IXGBE_MFLCN_DPF;
 	IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
 	IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
 	fcrtl = (hw->fc.low_water << 10) | IXGBE_FCRTL_XONE;
 	/* Set up and enable Rx high/low water mark thresholds, enable XON. */
 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
 		if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
 		    hw->fc.high_water[i]) {
 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
 			fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
 		} else {
 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
 			/*
 			 * In order to prevent Tx hangs when the internal Tx
 			 * switch is enabled we must set the high water mark
 			 * to the maximum FCRTH value.  This allows the Tx
 			 * switch to function even under heavy Rx workloads.
 			 */
 			fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
 		}
 		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
 	}
 	/* Configure pause time (2 TCs per register) */
 	reg = hw->fc.pause_time * 0x00010001;
 	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)
 		IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
 out:
 	return ret_val;
 }
 /**
  *  ixgbe_negotiate_fc - Negotiate flow control
  *  @hw: pointer to hardware structure
  *  @adv_reg: flow control advertised settings
  *  @lp_reg: link partner's flow control settings
  *  @adv_sym: symmetric pause bit in advertisement
  *  @adv_asm: asymmetric pause bit in advertisement
  *  @lp_sym: symmetric pause bit in link partner advertisement
  *  @lp_asm: asymmetric pause bit in link partner advertisement
  *
  *  Find the intersection between advertised settings and link partner's
  *  advertised settings
  **/
 static s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
 			      u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
 {
 	if ((!(adv_reg)) ||  (!(lp_reg)))
 		return IXGBE_ERR_FC_NOT_NEGOTIATED;
 	if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
 		/*
 		 * Now we need to check if the user selected Rx ONLY
 		 * of pause frames.  In this case, we had to advertise
 		 * FULL flow control because we could not advertise RX
 		 * ONLY. Hence, we must now check to see if we need to
 		 * turn OFF the TRANSMISSION of PAUSE frames.
 		 */
 		if (hw->fc.requested_mode == ixgbe_fc_full) {
 			hw->fc.current_mode = ixgbe_fc_full;
 			hw_dbg(hw, "Flow Control = FULL.\n");
 		} else {
 			hw->fc.current_mode = ixgbe_fc_rx_pause;
 			hw_dbg(hw, "Flow Control=RX PAUSE frames only\n");
 		}
 	} else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
 		   (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
 		hw->fc.current_mode = ixgbe_fc_tx_pause;
 		hw_dbg(hw, "Flow Control = TX PAUSE frames only.\n");
 	} else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
 		   !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
 		hw->fc.current_mode = ixgbe_fc_rx_pause;
 		hw_dbg(hw, "Flow Control = RX PAUSE frames only.\n");
 	} else {
 		hw->fc.current_mode = ixgbe_fc_none;
 		hw_dbg(hw, "Flow Control = NONE.\n");
 	}
 	return 0;
 }
 /**
  *  ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
  *  @hw: pointer to hardware structure
  *
  *  Enable flow control according on 1 gig fiber.
  **/
 static s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
 {
 	u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
 	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
 	/*
 	 * On multispeed fiber at 1g, bail out if
 	 * - link is up but AN did not complete, or if
 	 * - link is up and AN completed but timed out
 	 */
 	linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
 	if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
 	    (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1))
 		goto out;
 	pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
 	pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
 	ret_val =  ixgbe_negotiate_fc(hw, pcs_anadv_reg,
 			       pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
 			       IXGBE_PCS1GANA_ASM_PAUSE,
 			       IXGBE_PCS1GANA_SYM_PAUSE,
 			       IXGBE_PCS1GANA_ASM_PAUSE);
 out:
 	return ret_val;
 }
 /**
  *  ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
  *  @hw: pointer to hardware structure
  *
  *  Enable flow control according to IEEE clause 37.
  **/
 static s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
 {
 	u32 links2, anlp1_reg, autoc_reg, links;
 	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
 	/*
 	 * On backplane, bail out if
 	 * - backplane autoneg was not completed, or if
 	 * - we are 82599 and link partner is not AN enabled
 	 */
 	links = IXGBE_READ_REG(hw, IXGBE_LINKS);
 	if ((links & IXGBE_LINKS_KX_AN_COMP) == 0)
 		goto out;
 	if (hw->mac.type == ixgbe_mac_82599EB) {
 		links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
 		if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0)
 			goto out;
 	}
 	/*
 	 * Read the 10g AN autoc and LP ability registers and resolve
 	 * local flow control settings accordingly
 	 */
 	autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
 	ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
 		anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
 		IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
 out:
 	return ret_val;
 }
 /**
  *  ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
  *  @hw: pointer to hardware structure
  *
  *  Enable flow control according to IEEE clause 37.
  **/
 static s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
 {
 	u16 technology_ability_reg = 0;
 	u16 lp_technology_ability_reg = 0;
 	hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE,
 			     MDIO_MMD_AN,
 			     &technology_ability_reg);
 	hw->phy.ops.read_reg(hw, MDIO_AN_LPA,
 			     MDIO_MMD_AN,
 			     &lp_technology_ability_reg);
 	return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
 				  (u32)lp_technology_ability_reg,
 				  IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
 				  IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
 }
 /**
  *  ixgbe_fc_autoneg - Configure flow control
  *  @hw: pointer to hardware structure
  *
  *  Compares our advertised flow control capabilities to those advertised by
  *  our link partner, and determines the proper flow control mode to use.
  **/
 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
 {
 	s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
 	ixgbe_link_speed speed;
 	bool link_up;
 	/*
 	 * AN should have completed when the cable was plugged in.
 	 * Look for reasons to bail out.  Bail out if:
 	 * - FC autoneg is disabled, or if
 	 * - link is not up.
 	 *
 	 * Since we're being called from an LSC, link is already known to be up.
 	 * So use link_up_wait_to_complete=false.
 	 */
 	if (hw->fc.disable_fc_autoneg)
 		goto out;
 	hw->mac.ops.check_link(hw, &speed, &link_up, false);
 	if (!link_up)
 		goto out;
 	switch (hw->phy.media_type) {
 	/* Autoneg flow control on fiber adapters */
+	case ixgbe_media_type_fiber_fixed:
 	case ixgbe_media_type_fiber:
 		if (speed == IXGBE_LINK_SPEED_1GB_FULL)
 			ret_val = ixgbe_fc_autoneg_fiber(hw);
 		break;
 	/* Autoneg flow control on backplane adapters */
 	case ixgbe_media_type_backplane:
 		ret_val = ixgbe_fc_autoneg_backplane(hw);
 		break;
 	/* Autoneg flow control on copper adapters */
 	case ixgbe_media_type_copper:
 		if (ixgbe_device_supports_autoneg_fc(hw))
 			ret_val = ixgbe_fc_autoneg_copper(hw);
 		break;
 	default:
 		break;
 	}
 out:
 	if (ret_val == 0) {
 		hw->fc.fc_was_autonegged = true;
 	} else {
 		hw->fc.fc_was_autonegged = false;
 		hw->fc.current_mode = hw->fc.requested_mode;
 	}
 }
 /**
  *  ixgbe_disable_pcie_master - Disable PCI-express master access
  *  @hw: pointer to hardware structure
  *
  *  Disables PCI-Express master access and verifies there are no pending
  *  requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
  *  bit hasn't caused the master requests to be disabled, else 0
  *  is returned signifying master requests disabled.
  **/
 static s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
 {
 	struct ixgbe_adapter *adapter = hw->back;
 	s32 status = 0;
 	u32 i;
 	u16 value;
 	/* Always set this bit to ensure any future transactions are blocked */
 	IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
 	/* Exit if master requests are blocked */
 	if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
 		goto out;
 	/* Poll for master request bit to clear */
 	for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
 		udelay(100);
 		if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
 			goto out;
 	}
 	/*
 	 * Two consecutive resets are required via CTRL.RST per datasheet
 	 * 5.2.5.3.2 Master Disable.  We set a flag to inform the reset routine
 	 * of this need.  The first reset prevents new master requests from
 	 * being issued by our device.  We then must wait 1usec or more for any
 	 * remaining completions from the PCIe bus to trickle in, and then reset
 	 * again to clear out any effects they may have had on our device.
 	 */
 	hw_dbg(hw, "GIO Master Disable bit didn't clear - requesting resets\n");
 	hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
 	/*
 	 * Before proceeding, make sure that the PCIe block does not have
 	 * transactions pending.
 	 */
 	for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
 		udelay(100);
 		pci_read_config_word(adapter->pdev, IXGBE_PCI_DEVICE_STATUS,
 							 &value);
 		if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
 			goto out;
 	}
 	hw_dbg(hw, "PCIe transaction pending bit also did not clear.\n");
 	status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
 out:
 	return status;
 }
 /**
  *  ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
  *  @hw: pointer to hardware structure
  *  @mask: Mask to specify which semaphore to acquire
  *
  *  Acquires the SWFW semaphore through the GSSR register for the specified
  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
  **/
 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
 {
 	u32 gssr;
 	u32 swmask = mask;
 	u32 fwmask = mask << 5;
 	s32 timeout = 200;
 	while (timeout) {
 		/*
 		 * SW EEPROM semaphore bit is used for access to all
 		 * SW_FW_SYNC/GSSR bits (not just EEPROM)
 		 */
 		if (ixgbe_get_eeprom_semaphore(hw))
 			return IXGBE_ERR_SWFW_SYNC;
 		gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
 		if (!(gssr & (fwmask | swmask)))
 			break;
 		/*
 		 * Firmware currently using resource (fwmask) or other software
 		 * thread currently using resource (swmask)
 		 */
 		ixgbe_release_eeprom_semaphore(hw);
 		usleep_range(5000, 10000);
 		timeout--;
 	}
 	if (!timeout) {
 		hw_dbg(hw, "Driver can't access resource, SW_FW_SYNC timeout.\n");
 		return IXGBE_ERR_SWFW_SYNC;
 	}
 	gssr |= swmask;
 	IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
 	ixgbe_release_eeprom_semaphore(hw);
 	return 0;
 }
 /**
  *  ixgbe_release_swfw_sync - Release SWFW semaphore
  *  @hw: pointer to hardware structure
  *  @mask: Mask to specify which semaphore to release
  *
  *  Releases the SWFW semaphore through the GSSR register for the specified
  *  function (CSR, PHY0, PHY1, EEPROM, Flash)
  **/
 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
 {
 	u32 gssr;
 	u32 swmask = mask;
 	ixgbe_get_eeprom_semaphore(hw);
 	gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
 	gssr &= ~swmask;
 	IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
 	ixgbe_release_eeprom_semaphore(hw);
 }
 /**
  *  ixgbe_disable_rx_buff_generic - Stops the receive data path
  *  @hw: pointer to hardware structure
  *
  *  Stops the receive data path and waits for the HW to internally
  *  empty the Rx security block.
  **/
 s32 ixgbe_disable_rx_buff_generic(struct ixgbe_hw *hw)
 {
 #define IXGBE_MAX_SECRX_POLL 40
 	int i;
 	int secrxreg;
 	secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
 	secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
 	IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
 	for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
 		secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
 		if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
 			break;
 		else
 			/* Use interrupt-safe sleep just in case */
 			udelay(1000);
 	}
 	/* For informational purposes only */
 	if (i >= IXGBE_MAX_SECRX_POLL)
 		hw_dbg(hw, "Rx unit being enabled before security "
 		       "path fully disabled.  Continuing with init.\n");
 	return 0;
 }
 /**
  *  ixgbe_enable_rx_buff - Enables the receive data path
  *  @hw: pointer to hardware structure
  *
  *  Enables the receive data path
  **/
 s32 ixgbe_enable_rx_buff_generic(struct ixgbe_hw *hw)
 {
 	int secrxreg;
 	secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
 	secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
 	IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
 	IXGBE_WRITE_FLUSH(hw);
 	return 0;
 }
 /**
  *  ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
  *  @hw: pointer to hardware structure
  *  @regval: register value to write to RXCTRL
  *
  *  Enables the Rx DMA unit
  **/
 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
 {
 	IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
 	return 0;
 }
 /**
  *  ixgbe_blink_led_start_generic - Blink LED based on index.
  *  @hw: pointer to hardware structure
  *  @index: led number to blink
  **/
 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
 {
 	ixgbe_link_speed speed = 0;
 	bool link_up = false;
 	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 	s32 ret_val = 0;
 	/*
 	 * Link must be up to auto-blink the LEDs;
 	 * Force it if link is down.
 	 */
 	hw->mac.ops.check_link(hw, &speed, &link_up, false);
 	if (!link_up) {
 		/* Need the SW/FW semaphore around AUTOC writes if 82599 and
 		 * LESM is on.
 		 */
 		bool got_lock = false;
 		if ((hw->mac.type == ixgbe_mac_82599EB) &&
 		    ixgbe_verify_lesm_fw_enabled_82599(hw)) {
 			ret_val = hw->mac.ops.acquire_swfw_sync(hw,
 							IXGBE_GSSR_MAC_CSR_SM);
 			if (ret_val)
 				goto out;
 			got_lock = true;
 		}
 		autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 		autoc_reg |= IXGBE_AUTOC_FLU;
 		IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 		IXGBE_WRITE_FLUSH(hw);
 		if (got_lock)
 			hw->mac.ops.release_swfw_sync(hw,
 						      IXGBE_GSSR_MAC_CSR_SM);
 		usleep_range(10000, 20000);
 	}
 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
 	led_reg |= IXGBE_LED_BLINK(index);
 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 	IXGBE_WRITE_FLUSH(hw);
 out:
 	return ret_val;
 }
 /**
  *  ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
  *  @hw: pointer to hardware structure
  *  @index: led number to stop blinking
  **/
 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
 {
 	u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
 	u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
 	s32 ret_val = 0;
 	bool got_lock = false;
 	/* Need the SW/FW semaphore around AUTOC writes if 82599 and
 	 * LESM is on.
 	 */
 	if ((hw->mac.type == ixgbe_mac_82599EB) &&
 	    ixgbe_verify_lesm_fw_enabled_82599(hw)) {
 		ret_val = hw->mac.ops.acquire_swfw_sync(hw,
 						IXGBE_GSSR_MAC_CSR_SM);
 		if (ret_val)
 			goto out;
 		got_lock = true;
 	}
 	autoc_reg &= ~IXGBE_AUTOC_FLU;
 	autoc_reg |= IXGBE_AUTOC_AN_RESTART;
 	IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
 	if (hw->mac.type == ixgbe_mac_82599EB)
 		ixgbe_reset_pipeline_82599(hw);
 	if (got_lock)
 		hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
 	led_reg &= ~IXGBE_LED_MODE_MASK(index);
 	led_reg &= ~IXGBE_LED_BLINK(index);
 	led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
 	IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
 	IXGBE_WRITE_FLUSH(hw);
 out:
 	return ret_val;
 }
 /**
  *  ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
  *  @hw: pointer to hardware structure
  *  @san_mac_offset: SAN MAC address offset
  *
  *  This function will read the EEPROM location for the SAN MAC address
  *  pointer, and returns the value at that location.  This is used in both
  *  get and set mac_addr routines.
  **/
 static s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
                                         u16 *san_mac_offset)
 {
 	/*
 	 * First read the EEPROM pointer to see if the MAC addresses are
 	 * available.
 	 */
 	hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR, san_mac_offset);
 	return 0;
 }
 /**
  *  ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
  *  @hw: pointer to hardware structure
  *  @san_mac_addr: SAN MAC address
  *
  *  Reads the SAN MAC address from the EEPROM, if it's available.  This is
  *  per-port, so set_lan_id() must be called before reading the addresses.
  *  set_lan_id() is called by identify_sfp(), but this cannot be relied
  *  upon for non-SFP connections, so we must call it here.
  **/
 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
 {
 	u16 san_mac_data, san_mac_offset;
 	u8 i;
 	/*
 	 * First read the EEPROM pointer to see if the MAC addresses are
 	 * available.  If they're not, no point in calling set_lan_id() here.
 	 */
 	ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
 	if ((san_mac_offset == 0) || (san_mac_offset == 0xFFFF)) {
 		/*
 		 * No addresses available in this EEPROM.  It's not an
 		 * error though, so just wipe the local address and return.
 		 */
 		for (i = 0; i < 6; i++)
 			san_mac_addr[i] = 0xFF;
 		goto san_mac_addr_out;
 	}
 	/* make sure we know which port we need to program */
 	hw->mac.ops.set_lan_id(hw);
 	/* apply the port offset to the address offset */
 	(hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
 	                 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
 	for (i = 0; i < 3; i++) {
 		hw->eeprom.ops.read(hw, san_mac_offset, &san_mac_data);
 		san_mac_addr[i * 2] = (u8)(san_mac_data);
 		san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
 		san_mac_offset++;
 	}
 san_mac_addr_out:
 	return 0;
 }
 /**
  *  ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
  *  @hw: pointer to hardware structure
  *
  *  Read PCIe configuration space, and get the MSI-X vector count from
  *  the capabilities table.
  **/
 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
 {
 	struct ixgbe_adapter *adapter = hw->back;
 	u16 msix_count = 1;
 	u16 max_msix_count;
 	u16 pcie_offset;
 	switch (hw->mac.type) {
 	case ixgbe_mac_82598EB:
 		pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
 		max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
 		break;
 	case ixgbe_mac_82599EB:
 	case ixgbe_mac_X540:
 		pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
 		max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
 		break;
 	default:
 		return msix_count;
 	}
 	pci_read_config_word(adapter->pdev, pcie_offset, &msix_count);
 	msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
 	/* MSI-X count is zero-based in HW */
 	msix_count++;
 	if (msix_count > max_msix_count)
 		msix_count = max_msix_count;
 	return msix_count;
 }
 /**
  *  ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
  *  @hw: pointer to hardware struct
  *  @rar: receive address register index to disassociate
  *  @vmdq: VMDq pool index to remove from the rar
  **/
 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 {
 	u32 mpsar_lo, mpsar_hi;
 	u32 rar_entries = hw->mac.num_rar_entries;
 	/* Make sure we are using a valid rar index range */
 	if (rar >= rar_entries) {
 		hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 		return IXGBE_ERR_INVALID_ARGUMENT;
 	}
 	mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
 	mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 	if (!mpsar_lo && !mpsar_hi)
 		goto done;
 	if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
 		if (mpsar_lo) {
 			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
 			mpsar_lo = 0;
 		}
 		if (mpsar_hi) {
 			IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
 			mpsar_hi = 0;
 		}
 	} else if (vmdq < 32) {
 		mpsar_lo &= ~(1 << vmdq);
 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
 	} else {
 		mpsar_hi &= ~(1 << (vmdq - 32));
 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
 	}
 	/* was that the last pool using this rar? */
 	if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
 		hw->mac.ops.clear_rar(hw, rar);
 done:
 	return 0;
 }
 /**
  *  ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
  *  @hw: pointer to hardware struct
  *  @rar: receive address register index to associate with a VMDq index
  *  @vmdq: VMDq pool index
  **/
 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
 {
 	u32 mpsar;
 	u32 rar_entries = hw->mac.num_rar_entries;
 	/* Make sure we are using a valid rar index range */
 	if (rar >= rar_entries) {
 		hw_dbg(hw, "RAR index %d is out of range.\n", rar);
 		return IXGBE_ERR_INVALID_ARGUMENT;
 	}
 	if (vmdq < 32) {
 		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
 		mpsar |= 1 << vmdq;
 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
 	} else {
 		mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
 		mpsar |= 1 << (vmdq - 32);
 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
 	}
 	return 0;
 }
 /**
  *  This function should only be involved in the IOV mode.
  *  In IOV mode, Default pool is next pool after the number of
  *  VFs advertized and not 0.
  *  MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
  *
  *  ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
  *  @hw: pointer to hardware struct
  *  @vmdq: VMDq pool index
  **/
 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
 {
 	u32 rar = hw->mac.san_mac_rar_index;
 	if (vmdq < 32) {
 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
 	} else {
 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
 		IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
 	}
 	return 0;
 }
 /**
  *  ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
  *  @hw: pointer to hardware structure
  **/
 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
 {
 	int i;
 	for (i = 0; i < 128; i++)
 		IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
 	return 0;
 }
 /**
  *  ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
  *  @hw: pointer to hardware structure
  *  @vlan: VLAN id to write to VLAN filter
  *
  *  return the VLVF index where this VLAN id should be placed
  *
  **/
 static s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
 {
 	u32 bits = 0;
 	u32 first_empty_slot = 0;
 	s32 regindex;
 	/* short cut the special case */
 	if (vlan == 0)
 		return 0;
 	/*
 	  * Search for the vlan id in the VLVF entries. Save off the first empty
 	  * slot found along the way
 	  */
 	for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
 		bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
 		if (!bits && !(first_empty_slot))
 			first_empty_slot = regindex;
 		else if ((bits & 0x0FFF) == vlan)
 			break;
 	}
 	/*
 	  * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
 	  * in the VLVF. Else use the first empty VLVF register for this
 	  * vlan id.
 	  */
 	if (regindex >= IXGBE_VLVF_ENTRIES) {
 		if (first_empty_slot)
 			regindex = first_empty_slot;
 		else {
 			hw_dbg(hw, "No space in VLVF.\n");
 			regindex = IXGBE_ERR_NO_SPACE;
 		}
 	}
 	return regindex;
 }
 /**
  *  ixgbe_set_vfta_generic - Set VLAN filter table
  *  @hw: pointer to hardware structure
  *  @vlan: VLAN id to write to VLAN filter
  *  @vind: VMDq output index that maps queue to VLAN id in VFVFB
  *  @vlan_on: boolean flag to turn on/off VLAN in VFVF
  *
  *  Turn on/off specified VLAN in the VLAN filter table.
  **/
 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
                            bool vlan_on)
 {
 	s32 regindex;
 	u32 bitindex;
 	u32 vfta;
 	u32 bits;
 	u32 vt;
 	u32 targetbit;
 	bool vfta_changed = false;
 	if (vlan > 4095)
 		return IXGBE_ERR_PARAM;
 	/*
 	 * this is a 2 part operation - first the VFTA, then the
 	 * VLVF and VLVFB if VT Mode is set
 	 * We don't write the VFTA until we know the VLVF part succeeded.
 	 */
 	/* Part 1
 	 * The VFTA is a bitstring made up of 128 32-bit registers
 	 * that enable the particular VLAN id, much like the MTA:
 	 *    bits[11-5]: which register
 	 *    bits[4-0]:  which bit in the register
 	 */
 	regindex = (vlan >> 5) & 0x7F;
 	bitindex = vlan & 0x1F;
 	targetbit = (1 << bitindex);
 	vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
 	if (vlan_on) {
 		if (!(vfta & targetbit)) {
 			vfta |= targetbit;
 			vfta_changed = true;
 		}
 	} else {
 		if ((vfta & targetbit)) {
 			vfta &= ~targetbit;
 			vfta_changed = true;
 		}
 	}
 	/* Part 2
 	 * If VT Mode is set
 	 *   Either vlan_on
 	 *     make sure the vlan is in VLVF
 	 *     set the vind bit in the matching VLVFB
 	 *   Or !vlan_on
 	 *     clear the pool bit and possibly the vind
 	 */
 	vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 	if (vt & IXGBE_VT_CTL_VT_ENABLE) {
 		s32 vlvf_index;
 		vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
 		if (vlvf_index < 0)
 			return vlvf_index;
 		if (vlan_on) {
 			/* set the pool bit */
 			if (vind < 32) {
 				bits = IXGBE_READ_REG(hw,
 						IXGBE_VLVFB(vlvf_index*2));
 				bits |= (1 << vind);
 				IXGBE_WRITE_REG(hw,
 						IXGBE_VLVFB(vlvf_index*2),
 						bits);
 			} else {
 				bits = IXGBE_READ_REG(hw,
 						IXGBE_VLVFB((vlvf_index*2)+1));
 				bits |= (1 << (vind-32));
 				IXGBE_WRITE_REG(hw,
 						IXGBE_VLVFB((vlvf_index*2)+1),
 						bits);
 			}
 		} else {
 			/* clear the pool bit */
 			if (vind < 32) {
 				bits = IXGBE_READ_REG(hw,
 						IXGBE_VLVFB(vlvf_index*2));
 				bits &= ~(1 << vind);
 				IXGBE_WRITE_REG(hw,
 						IXGBE_VLVFB(vlvf_index*2),
 						bits);
 				bits |= IXGBE_READ_REG(hw,
 						IXGBE_VLVFB((vlvf_index*2)+1));
 			} else {
 				bits = IXGBE_READ_REG(hw,
 						IXGBE_VLVFB((vlvf_index*2)+1));
 				bits &= ~(1 << (vind-32));
 				IXGBE_WRITE_REG(hw,
 						IXGBE_VLVFB((vlvf_index*2)+1),
 						bits);
 				bits |= IXGBE_READ_REG(hw,
 						IXGBE_VLVFB(vlvf_index*2));
 			}
 		}
 		/*
 		 * If there are still bits set in the VLVFB registers
 		 * for the VLAN ID indicated we need to see if the
 		 * caller is requesting that we clear the VFTA entry bit.
 		 * If the caller has requested that we clear the VFTA
 		 * entry bit but there are still pools/VFs using this VLAN
 		 * ID entry then ignore the request.  We're not worried
 		 * about the case where we're turning the VFTA VLAN ID
 		 * entry bit on, only when requested to turn it off as
 		 * there may be multiple pools and/or VFs using the
 		 * VLAN ID entry.  In that case we cannot clear the
 		 * VFTA bit until all pools/VFs using that VLAN ID have also
 		 * been cleared.  This will be indicated by "bits" being
 		 * zero.
 		 */
 		if (bits) {
 			IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
 					(IXGBE_VLVF_VIEN | vlan));
 			if (!vlan_on) {
 				/* someone wants to clear the vfta entry
 				 * but some pools/VFs are still using it.
 				 * Ignore it. */
 				vfta_changed = false;
 			}
 		}
 		else
 			IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
 	}
 	if (vfta_changed)
 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
 	return 0;
 }
 /**
  *  ixgbe_clear_vfta_generic - Clear VLAN filter table
  *  @hw: pointer to hardware structure
  *
  *  Clears the VLAN filer table, and the VMDq index associated with the filter
  **/
 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
 {
 	u32 offset;
 	for (offset = 0; offset < hw->mac.vft_size; offset++)
 		IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
 	for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
 		IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
 		IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset*2), 0);
 		IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset*2)+1), 0);
 	}
 	return 0;
 }
 /**
  *  ixgbe_check_mac_link_generic - Determine link and speed status
  *  @hw: pointer to hardware structure
  *  @speed: pointer to link speed
  *  @link_up: true when link is up
  *  @link_up_wait_to_complete: bool used to wait for link up or not
  *
  *  Reads the links register to determine if link is up and the current speed
  **/
 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 				 bool *link_up, bool link_up_wait_to_complete)
 {
 	u32 links_reg, links_orig;
 	u32 i;
 	/* clear the old state */
 	links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
 	links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 	if (links_orig != links_reg) {
 		hw_dbg(hw, "LINKS changed from %08X to %08X\n",
 		       links_orig, links_reg);
 	}
 	if (link_up_wait_to_complete) {
 		for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
 			if (links_reg & IXGBE_LINKS_UP) {
 				*link_up = true;
 				break;
 			} else {
 				*link_up = false;
 			}
 			msleep(100);
 			links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
 		}
 	} else {
 		if (links_reg & IXGBE_LINKS_UP)
 			*link_up = true;
 		else
 			*link_up = false;
 	}
 	if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 	    IXGBE_LINKS_SPEED_10G_82599)
 		*speed = IXGBE_LINK_SPEED_10GB_FULL;
 	else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 		 IXGBE_LINKS_SPEED_1G_82599)
 		*speed = IXGBE_LINK_SPEED_1GB_FULL;
 	else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
 		 IXGBE_LINKS_SPEED_100_82599)
 		*speed = IXGBE_LINK_SPEED_100_FULL;
 	else
 		*speed = IXGBE_LINK_SPEED_UNKNOWN;
 	return 0;
 }
 /**
  *  ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
  *  the EEPROM
  *  @hw: pointer to hardware structure
  *  @wwnn_prefix: the alternative WWNN prefix
  *  @wwpn_prefix: the alternative WWPN prefix
  *
  *  This function will read the EEPROM from the alternative SAN MAC address
  *  block to check the support for the alternative WWNN/WWPN prefix support.
  **/
 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
                                         u16 *wwpn_prefix)
 {
 	u16 offset, caps;
 	u16 alt_san_mac_blk_offset;
 	/* clear output first */
 	*wwnn_prefix = 0xFFFF;
 	*wwpn_prefix = 0xFFFF;
 	/* check if alternative SAN MAC is supported */
 	hw->eeprom.ops.read(hw, IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR,
 	                    &alt_san_mac_blk_offset);
 	if ((alt_san_mac_blk_offset == 0) ||
 	    (alt_san_mac_blk_offset == 0xFFFF))
 		goto wwn_prefix_out;
 	/* check capability in alternative san mac address block */
 	offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
 	hw->eeprom.ops.read(hw, offset, &caps);
 	if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
 		goto wwn_prefix_out;
 	/* get the corresponding prefix for WWNN/WWPN */
 	offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
 	hw->eeprom.ops.read(hw, offset, wwnn_prefix);
 	offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
 	hw->eeprom.ops.read(hw, offset, wwpn_prefix);
 wwn_prefix_out:
 	return 0;
 }
 /**
  *  ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
  *  @hw: pointer to hardware structure
  *  @enable: enable or disable switch for anti-spoofing
  *  @pf: Physical Function pool - do not enable anti-spoofing for the PF
  *
  **/
 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
 {
 	int j;
 	int pf_target_reg = pf >> 3;
 	int pf_target_shift = pf % 8;
 	u32 pfvfspoof = 0;
 	if (hw->mac.type == ixgbe_mac_82598EB)
 		return;
 	if (enable)
 		pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
 	/*
 	 * PFVFSPOOF register array is size 8 with 8 bits assigned to
 	 * MAC anti-spoof enables in each register array element.
 	 */
 	for (j = 0; j < pf_target_reg; j++)
 		IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
 	/*
 	 * The PF should be allowed to spoof so that it can support
 	 * emulation mode NICs.  Do not set the bits assigned to the PF
 	 */
 	pfvfspoof &= (1 << pf_target_shift) - 1;
 	IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
 	/*
 	 * Remaining pools belong to the PF so they do not need to have
 	 * anti-spoofing enabled.
 	 */
 	for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
 		IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
 }
 /**
  *  ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
  *  @hw: pointer to hardware structure
  *  @enable: enable or disable switch for VLAN anti-spoofing
  *  @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
  *
  **/
 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
 {
 	int vf_target_reg = vf >> 3;
 	int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
 	u32 pfvfspoof;
 	if (hw->mac.type == ixgbe_mac_82598EB)
 		return;
 	pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
 	if (enable)
 		pfvfspoof |= (1 << vf_target_shift);
 	else
 		pfvfspoof &= ~(1 << vf_target_shift);
 	IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
 }
 /**
  *  ixgbe_get_device_caps_generic - Get additional device capabilities
  *  @hw: pointer to hardware structure
  *  @device_caps: the EEPROM word with the extra device capabilities
  *
  *  This function will read the EEPROM location for the device capabilities,
  *  and return the word through device_caps.
  **/
 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
 {
 	hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
 	return 0;
 }
 /**
  * ixgbe_set_rxpba_generic - Initialize RX packet buffer
  * @hw: pointer to hardware structure
  * @num_pb: number of packet buffers to allocate
  * @headroom: reserve n KB of headroom
  * @strategy: packet buffer allocation strategy
  **/
 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw,
 			     int num_pb,
 			     u32 headroom,
 			     int strategy)
 {
 	u32 pbsize = hw->mac.rx_pb_size;
 	int i = 0;
 	u32 rxpktsize, txpktsize, txpbthresh;
 	/* Reserve headroom */
 	pbsize -= headroom;
 	if (!num_pb)
 		num_pb = 1;
 	/* Divide remaining packet buffer space amongst the number
 	 * of packet buffers requested using supplied strategy.
 	 */
 	switch (strategy) {
 	case (PBA_STRATEGY_WEIGHTED):
 		/* pba_80_48 strategy weight first half of packet buffer with
 		 * 5/8 of the packet buffer space.
 		 */
 		rxpktsize = ((pbsize * 5 * 2) / (num_pb * 8));
 		pbsize -= rxpktsize * (num_pb / 2);
 		rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
 		for (; i < (num_pb / 2); i++)
 			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
 		/* Fall through to configure remaining packet buffers */
 	case (PBA_STRATEGY_EQUAL):
 		/* Divide the remaining Rx packet buffer evenly among the TCs */
 		rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
 		for (; i < num_pb; i++)
 			IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
 		break;
 	default:
 		break;
 	}
 	/*
 	 * Setup Tx packet buffer and threshold equally for all TCs
 	 * TXPBTHRESH register is set in K so divide by 1024 and subtract
 	 * 10 since the largest packet we support is just over 9K.
 	 */
 	txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
 	txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
 	for (i = 0; i < num_pb; i++) {
 		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
 		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
 	}
 	/* Clear unused TCs, if any, to zero buffer size*/
 	for (; i < IXGBE_MAX_PB; i++) {
 		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
 		IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
 		IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
 	}
 }
 /**
  *  ixgbe_calculate_checksum - Calculate checksum for buffer
  *  @buffer: pointer to EEPROM
  *  @length: size of EEPROM to calculate a checksum for
  *
  *  Calculates the checksum for some buffer on a specified length.  The
  *  checksum calculated is returned.
  **/
 static u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
 {
 	u32 i;
 	u8 sum = 0;
 	if (!buffer)
 		return 0;
 	for (i = 0; i < length; i++)
 		sum += buffer[i];
 	return (u8) (0 - sum);
 }
 /**
  *  ixgbe_host_interface_command - Issue command to manageability block
  *  @hw: pointer to the HW structure
  *  @buffer: contains the command to write and where the return status will
  *           be placed
  *  @length: length of buffer, must be multiple of 4 bytes
  *
  *  Communicates with the manageability block.  On success return 0
  *  else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
  **/
 static s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
 					u32 length)
 {
 	u32 hicr, i, bi;
 	u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
 	u8 buf_len, dword_len;
 	s32 ret_val = 0;
 	if (length == 0 || length & 0x3 ||
 	    length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
 		hw_dbg(hw, "Buffer length failure.\n");
 		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
 		goto out;
 	}
 	/* Check that the host interface is enabled. */
 	hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
 	if ((hicr & IXGBE_HICR_EN) == 0) {
 		hw_dbg(hw, "IXGBE_HOST_EN bit disabled.\n");
 		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
 		goto out;
 	}
 	/* Calculate length in DWORDs */
 	dword_len = length >> 2;
 	/*
 	 * The device driver writes the relevant command block
 	 * into the ram area.
 	 */
 	for (i = 0; i < dword_len; i++)
 		IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 				      i, cpu_to_le32(buffer[i]));
 	/* Setting this bit tells the ARC that a new command is pending. */
 	IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
 	for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
 		hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
 		if (!(hicr & IXGBE_HICR_C))
 			break;
 		usleep_range(1000, 2000);
 	}
 	/* Check command successful completion. */
 	if (i == IXGBE_HI_COMMAND_TIMEOUT ||
 	    (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
 		hw_dbg(hw, "Command has failed with no status valid.\n");
 		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
 		goto out;
 	}
 	/* Calculate length in DWORDs */
 	dword_len = hdr_size >> 2;
 	/* first pull in the header so we know the buffer length */
 	for (bi = 0; bi < dword_len; bi++) {
 		buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
 		le32_to_cpus(&buffer[bi]);
 	}
 	/* If there is any thing in data position pull it in */
 	buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
 	if (buf_len == 0)
 		goto out;
 	if (length < (buf_len + hdr_size)) {
 		hw_dbg(hw, "Buffer not large enough for reply message.\n");
 		ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
 		goto out;
 	}
 	/* Calculate length in DWORDs, add 3 for odd lengths */
 	dword_len = (buf_len + 3) >> 2;
 	/* Pull in the rest of the buffer (bi is where we left off)*/
 	for (; bi <= dword_len; bi++) {
 		buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
 		le32_to_cpus(&buffer[bi]);
 	}
 out:
 	return ret_val;
 }
 /**
  *  ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
  *  @hw: pointer to the HW structure
  *  @maj: driver version major number
  *  @min: driver version minor number
  *  @build: driver version build number
  *  @sub: driver version sub build number
  *
  *  Sends driver version number to firmware through the manageability
  *  block.  On success return 0
  *  else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
  *  semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
  **/
 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
 				 u8 build, u8 sub)
 {
 	struct ixgbe_hic_drv_info fw_cmd;
 	int i;
 	s32 ret_val = 0;
 	if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM) != 0) {
 		ret_val = IXGBE_ERR_SWFW_SYNC;
 		goto out;
 	}
 	fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
 	fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
 	fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
 	fw_cmd.port_num = (u8)hw->bus.func;
 	fw_cmd.ver_maj = maj;
 	fw_cmd.ver_min = min;
 	fw_cmd.ver_build = build;
 	fw_cmd.ver_sub = sub;
 	fw_cmd.hdr.checksum = 0;
 	fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
 				(FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
 	fw_cmd.pad = 0;
 	fw_cmd.pad2 = 0;
 	for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
 		ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
 						       sizeof(fw_cmd));
 		if (ret_val != 0)
 			continue;
 		if (fw_cmd.hdr.cmd_or_resp.ret_status ==
 		    FW_CEM_RESP_STATUS_SUCCESS)
 			ret_val = 0;
 		else
 			ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
 		break;
 	}
 	hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
 out:
 	return ret_val;
 }
 /**
  * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
  * @hw: pointer to the hardware structure
  *
  * The 82599 and x540 MACs can experience issues if TX work is still pending
  * when a reset occurs.  This function prevents this by flushing the PCIe
  * buffers on the system.
  **/
 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
 {
 	u32 gcr_ext, hlreg0;
 	/*
 	 * If double reset is not requested then all transactions should
 	 * already be clear and as such there is no work to do
 	 */
 	if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
 		return;
 	/*
 	 * Set loopback enable to prevent any transmits from being sent
 	 * should the link come up.  This assumes that the RXCTRL.RXEN bit
 	 * has already been cleared.
 	 */
 	hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
 	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
 	/* initiate cleaning flow for buffers in the PCIe transaction layer */
 	gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
 			gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
 	/* Flush all writes and allow 20usec for all transactions to clear */
 	IXGBE_WRITE_FLUSH(hw);
 	udelay(20);
 	/* restore previous register values */
 	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
 	IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
 }
 static const u8 ixgbe_emc_temp_data[4] = {
 	IXGBE_EMC_INTERNAL_DATA,
 	IXGBE_EMC_DIODE1_DATA,
 	IXGBE_EMC_DIODE2_DATA,
 	IXGBE_EMC_DIODE3_DATA
 };
 static const u8 ixgbe_emc_therm_limit[4] = {
 	IXGBE_EMC_INTERNAL_THERM_LIMIT,
 	IXGBE_EMC_DIODE1_THERM_LIMIT,
 	IXGBE_EMC_DIODE2_THERM_LIMIT,
 	IXGBE_EMC_DIODE3_THERM_LIMIT
 };
 /**
  *  ixgbe_get_ets_data - Extracts the ETS bit data
  *  @hw: pointer to hardware structure
  *  @ets_cfg: extected ETS data
  *  @ets_offset: offset of ETS data
  *
  *  Returns error code.
  **/
 static s32 ixgbe_get_ets_data(struct ixgbe_hw *hw, u16 *ets_cfg,
 			      u16 *ets_offset)
 {
 	s32 status = 0;
 	status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, ets_offset);
 	if (status)
 		goto out;
 	if ((*ets_offset == 0x0000) || (*ets_offset == 0xFFFF)) {
 		status = IXGBE_NOT_IMPLEMENTED;
 		goto out;
 	}
 	status = hw->eeprom.ops.read(hw, *ets_offset, ets_cfg);
 	if (status)
 		goto out;
 	if ((*ets_cfg & IXGBE_ETS_TYPE_MASK) != IXGBE_ETS_TYPE_EMC_SHIFTED) {
 		status = IXGBE_NOT_IMPLEMENTED;
 		goto out;
 	}
 out:
 	return status;
 }
 /**
  *  ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
  *  @hw: pointer to hardware structure
  *
  *  Returns the thermal sensor data structure
  **/
 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
 {
 	s32 status = 0;
 	u16 ets_offset;
 	u16 ets_cfg;
 	u16 ets_sensor;
 	u8  num_sensors;
 	u8  i;
 	struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
 	/* Only support thermal sensors attached to physical port 0 */
 	if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
 		status = IXGBE_NOT_IMPLEMENTED;
 		goto out;
 	}
 	status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
 	if (status)
 		goto out;
 	num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
 	if (num_sensors > IXGBE_MAX_SENSORS)
 		num_sensors = IXGBE_MAX_SENSORS;
 	for (i = 0; i < num_sensors; i++) {
 		u8  sensor_index;
 		u8  sensor_location;
 		status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
 					     &ets_sensor);
 		if (status)
 			goto out;
 		sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
 				IXGBE_ETS_DATA_INDEX_SHIFT);
 		sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
 				   IXGBE_ETS_DATA_LOC_SHIFT);
 		if (sensor_location != 0) {
 			status = hw->phy.ops.read_i2c_byte(hw,
 					ixgbe_emc_temp_data[sensor_index],
 					IXGBE_I2C_THERMAL_SENSOR_ADDR,
 					&data->sensor[i].temp);
 			if (status)
 				goto out;
 		}
 	}
 out:
 	return status;
 }
 /**
  * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
  * @hw: pointer to hardware structure
  *
  * Inits the thermal sensor thresholds according to the NVM map
  * and save off the threshold and location values into mac.thermal_sensor_data
  **/
 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
 {
 	s32 status = 0;
 	u16 ets_offset;
 	u16 ets_cfg;
 	u16 ets_sensor;
 	u8  low_thresh_delta;
 	u8  num_sensors;
 	u8  therm_limit;
 	u8  i;
 	struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
 	memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
 	/* Only support thermal sensors attached to physical port 0 */
 	if ((IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
 		status = IXGBE_NOT_IMPLEMENTED;
 		goto out;
 	}
 	status = ixgbe_get_ets_data(hw, &ets_cfg, &ets_offset);
 	if (status)
 		goto out;
 	low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
 			     IXGBE_ETS_LTHRES_DELTA_SHIFT);
 	num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
 	if (num_sensors > IXGBE_MAX_SENSORS)
 		num_sensors = IXGBE_MAX_SENSORS;
 	for (i = 0; i < num_sensors; i++) {
 		u8  sensor_index;
 		u8  sensor_location;
 		hw->eeprom.ops.read(hw, (ets_offset + 1 + i), &ets_sensor);
 		sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
 				IXGBE_ETS_DATA_INDEX_SHIFT);
 		sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
 				   IXGBE_ETS_DATA_LOC_SHIFT);
 		therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
 		hw->phy.ops.write_i2c_byte(hw,
 			ixgbe_emc_therm_limit[sensor_index],
 			IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
 		if (sensor_location == 0)
 			continue;
 		data->sensor[i].location = sensor_location;
 		data->sensor[i].caution_thresh = therm_limit;
 		data->sensor[i].max_op_thresh = therm_limit - low_thresh_delta;
 	}
 out:
 	return status;
 }

drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h

Diff comments View file @ 4e8e1bc

 /*******************************************************************************
   Intel 10 Gigabit PCI Express Linux driver
   Copyright(c) 1999 - 2013 Intel Corporation.
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
   version 2, as published by the Free Software Foundation.
   This program is distributed in the hope it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
   You should have received a copy of the GNU General Public License along with
   this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   The full GNU General Public License is included in this distribution in
   the file called "COPYING".
   Contact Information:
   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *******************************************************************************/
 #ifndef _IXGBE_PHY_H_
 #define _IXGBE_PHY_H_
 #include "ixgbe_type.h"
 #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
 #define IXGBE_I2C_EEPROM_DEV_ADDR2   0xA2
 /* EEPROM byte offsets */
 #define IXGBE_SFF_IDENTIFIER         0x0
 #define IXGBE_SFF_IDENTIFIER_SFP     0x3
 #define IXGBE_SFF_VENDOR_OUI_BYTE0   0x25
 #define IXGBE_SFF_VENDOR_OUI_BYTE1   0x26
 #define IXGBE_SFF_VENDOR_OUI_BYTE2   0x27
 #define IXGBE_SFF_1GBE_COMP_CODES    0x6
 #define IXGBE_SFF_10GBE_COMP_CODES   0x3
 #define IXGBE_SFF_CABLE_TECHNOLOGY   0x8
 #define IXGBE_SFF_CABLE_SPEC_COMP    0x3C
 #define IXGBE_SFF_SFF_8472_SWAP      0x5C
 #define IXGBE_SFF_SFF_8472_COMP      0x5E
+#define IXGBE_SFF_SFF_8472_OSCB	0x6E
+#define IXGBE_SFF_SFF_8472_ESCB	0x76
 /* Bitmasks */
 #define IXGBE_SFF_DA_PASSIVE_CABLE           0x4
 #define IXGBE_SFF_DA_ACTIVE_CABLE            0x8
 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING    0x4
 #define IXGBE_SFF_1GBASESX_CAPABLE           0x1
 #define IXGBE_SFF_1GBASELX_CAPABLE           0x2
 #define IXGBE_SFF_1GBASET_CAPABLE            0x8
 #define IXGBE_SFF_10GBASESR_CAPABLE          0x10
 #define IXGBE_SFF_10GBASELR_CAPABLE          0x20
+#define IXGBE_SFF_SOFT_RS_SELECT_MASK	0x8
+#define IXGBE_SFF_SOFT_RS_SELECT_10G	0x8
+#define IXGBE_SFF_SOFT_RS_SELECT_1G	0x0
 #define IXGBE_SFF_ADDRESSING_MODE	     0x4
 #define IXGBE_I2C_EEPROM_READ_MASK           0x100
 #define IXGBE_I2C_EEPROM_STATUS_MASK         0x3
 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
 #define IXGBE_I2C_EEPROM_STATUS_PASS         0x1
 #define IXGBE_I2C_EEPROM_STATUS_FAIL         0x2
 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS  0x3
 /* Flow control defines */
 #define IXGBE_TAF_SYM_PAUSE                  0x400
 #define IXGBE_TAF_ASM_PAUSE                  0x800
 /* Bit-shift macros */
 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT    24
 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT    16
 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT    8
 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
 #define IXGBE_SFF_VENDOR_OUI_TYCO     0x00407600
 #define IXGBE_SFF_VENDOR_OUI_FTL      0x00906500
 #define IXGBE_SFF_VENDOR_OUI_AVAGO    0x00176A00
 #define IXGBE_SFF_VENDOR_OUI_INTEL    0x001B2100
 /* I2C SDA and SCL timing parameters for standard mode */
 #define IXGBE_I2C_T_HD_STA  4
 #define IXGBE_I2C_T_LOW     5
 #define IXGBE_I2C_T_HIGH    4
 #define IXGBE_I2C_T_SU_STA  5
 #define IXGBE_I2C_T_HD_DATA 5
 #define IXGBE_I2C_T_SU_DATA 1
 #define IXGBE_I2C_T_RISE    1
 #define IXGBE_I2C_T_FALL    1
 #define IXGBE_I2C_T_SU_STO  4
 #define IXGBE_I2C_T_BUF     5
 #define IXGBE_TN_LASI_STATUS_REG        0x9005
 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
 /* SFP+ SFF-8472 Compliance code */
 #define IXGBE_SFF_SFF_8472_UNSUP      0x00
 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                                u32 device_type, u16 *phy_data);
 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
                                 u32 device_type, u16 phy_data);
 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
                                        ixgbe_link_speed speed,
                                        bool autoneg_wait_to_complete);
 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
                                                ixgbe_link_speed *speed,
                                                bool *autoneg);
 /* PHY specific */
 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
                              ixgbe_link_speed *speed,
                              bool *link_up);
 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
                                        u16 *firmware_version);
 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
                                            u16 *firmware_version);
 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
                                         u16 *list_offset,
                                         u16 *data_offset);
 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
                                 u8 dev_addr, u8 *data);
 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
                                  u8 dev_addr, u8 data);
 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
                                   u8 *eeprom_data);
 s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
 				   u8 *sff8472_data);
 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
                                    u8 eeprom_data);
 #endif /* _IXGBE_PHY_H_ */

drivers/net/ethernet/intel/ixgbe/ixgbe_type.h

Diff comments View file @ 4e8e1bc

 /*******************************************************************************
   Intel 10 Gigabit PCI Express Linux driver
   Copyright(c) 1999 - 2013 Intel Corporation.
   This program is free software; you can redistribute it and/or modify it
   under the terms and conditions of the GNU General Public License,
   version 2, as published by the Free Software Foundation.
   This program is distributed in the hope it will be useful, but WITHOUT
   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
   more details.
   You should have received a copy of the GNU General Public License along with
   this program; if not, write to the Free Software Foundation, Inc.,
   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
   The full GNU General Public License is included in this distribution in
   the file called "COPYING".
   Contact Information:
   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
 *******************************************************************************/
 #ifndef _IXGBE_TYPE_H_
 #define _IXGBE_TYPE_H_
 #include <linux/types.h>
 #include <linux/mdio.h>
 #include <linux/netdevice.h>
 /* Device IDs */
 #define IXGBE_DEV_ID_82598               0x10B6
 #define IXGBE_DEV_ID_82598_BX            0x1508
 #define IXGBE_DEV_ID_82598AF_DUAL_PORT   0x10C6
 #define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7
 #define IXGBE_DEV_ID_82598EB_SFP_LOM     0x10DB
 #define IXGBE_DEV_ID_82598AT             0x10C8
 #define IXGBE_DEV_ID_82598AT2            0x150B
 #define IXGBE_DEV_ID_82598EB_CX4         0x10DD
 #define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC
 #define IXGBE_DEV_ID_82598_DA_DUAL_PORT  0x10F1
 #define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM      0x10E1
 #define IXGBE_DEV_ID_82598EB_XF_LR       0x10F4
 #define IXGBE_DEV_ID_82599_KX4           0x10F7
 #define IXGBE_DEV_ID_82599_KX4_MEZZ      0x1514
 #define IXGBE_DEV_ID_82599_KR            0x1517
 #define IXGBE_DEV_ID_82599_T3_LOM        0x151C
 #define IXGBE_DEV_ID_82599_CX4           0x10F9
 #define IXGBE_DEV_ID_82599_SFP           0x10FB
 #define IXGBE_DEV_ID_82599_BACKPLANE_FCOE       0x152a
 #define IXGBE_DEV_ID_82599_SFP_FCOE      0x1529
 #define IXGBE_SUBDEV_ID_82599_SFP        0x11A9
 #define IXGBE_SUBDEV_ID_82599_RNDC       0x1F72
 #define IXGBE_SUBDEV_ID_82599_560FLR     0x17D0
 #define IXGBE_SUBDEV_ID_82599_SP_560FLR  0x211B
 #define IXGBE_SUBDEV_ID_82599_ECNA_DP    0x0470
 #define IXGBE_SUBDEV_ID_82599_LOM_SFP    0x8976
 #define IXGBE_DEV_ID_82599_SFP_EM        0x1507
 #define IXGBE_DEV_ID_82599_SFP_SF2       0x154D
 #define IXGBE_DEV_ID_82599EN_SFP         0x1557
 #define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001
 #define IXGBE_DEV_ID_82599_XAUI_LOM      0x10FC
 #define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8
 #define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ  0x000C
 #define IXGBE_DEV_ID_82599_LS            0x154F
 #define IXGBE_DEV_ID_X540T               0x1528
 #define IXGBE_DEV_ID_82599_SFP_SF_QP     0x154A
 #define IXGBE_DEV_ID_X540T1              0x1560
 /* VF Device IDs */
 #define IXGBE_DEV_ID_82599_VF           0x10ED
 #define IXGBE_DEV_ID_X540_VF            0x1515
 /* General Registers */
 #define IXGBE_CTRL      0x00000
 #define IXGBE_STATUS    0x00008
 #define IXGBE_CTRL_EXT  0x00018
 #define IXGBE_ESDP      0x00020
 #define IXGBE_EODSDP    0x00028
 #define IXGBE_I2CCTL    0x00028
 #define IXGBE_LEDCTL    0x00200
 #define IXGBE_FRTIMER   0x00048
 #define IXGBE_TCPTIMER  0x0004C
 #define IXGBE_CORESPARE 0x00600
 #define IXGBE_EXVET     0x05078
 /* NVM Registers */
 #define IXGBE_EEC       0x10010
 #define IXGBE_EERD      0x10014
 #define IXGBE_EEWR      0x10018
 #define IXGBE_FLA       0x1001C
 #define IXGBE_EEMNGCTL  0x10110
 #define IXGBE_EEMNGDATA 0x10114
 #define IXGBE_FLMNGCTL  0x10118
 #define IXGBE_FLMNGDATA 0x1011C
 #define IXGBE_FLMNGCNT  0x10120
 #define IXGBE_FLOP      0x1013C
 #define IXGBE_GRC       0x10200
 /* General Receive Control */
 #define IXGBE_GRC_MNG  0x00000001 /* Manageability Enable */
 #define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */
 #define IXGBE_VPDDIAG0  0x10204
 #define IXGBE_VPDDIAG1  0x10208
 /* I2CCTL Bit Masks */
 #define IXGBE_I2C_CLK_IN    0x00000001
 #define IXGBE_I2C_CLK_OUT   0x00000002
 #define IXGBE_I2C_DATA_IN   0x00000004
 #define IXGBE_I2C_DATA_OUT  0x00000008
 #define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT	500
 #define IXGBE_I2C_THERMAL_SENSOR_ADDR	0xF8
 #define IXGBE_EMC_INTERNAL_DATA		0x00
 #define IXGBE_EMC_INTERNAL_THERM_LIMIT	0x20
 #define IXGBE_EMC_DIODE1_DATA		0x01
 #define IXGBE_EMC_DIODE1_THERM_LIMIT	0x19
 #define IXGBE_EMC_DIODE2_DATA		0x23
 #define IXGBE_EMC_DIODE2_THERM_LIMIT	0x1A
 #define IXGBE_MAX_SENSORS		3
 struct ixgbe_thermal_diode_data {
 	u8 location;
 	u8 temp;
 	u8 caution_thresh;
 	u8 max_op_thresh;
 };
 struct ixgbe_thermal_sensor_data {
 	struct ixgbe_thermal_diode_data sensor[IXGBE_MAX_SENSORS];
 };
 /* Interrupt Registers */
 #define IXGBE_EICR      0x00800
 #define IXGBE_EICS      0x00808
 #define IXGBE_EIMS      0x00880
 #define IXGBE_EIMC      0x00888
 #define IXGBE_EIAC      0x00810
 #define IXGBE_EIAM      0x00890
 #define IXGBE_EICS_EX(_i)   (0x00A90 + (_i) * 4)
 #define IXGBE_EIMS_EX(_i)   (0x00AA0 + (_i) * 4)
 #define IXGBE_EIMC_EX(_i)   (0x00AB0 + (_i) * 4)
 #define IXGBE_EIAM_EX(_i)   (0x00AD0 + (_i) * 4)
 /*
  * 82598 EITR is 16 bits but set the limits based on the max
  * supported by all ixgbe hardware.  82599 EITR is only 12 bits,
  * with the lower 3 always zero.
  */
 #define IXGBE_MAX_INT_RATE 488281
 #define IXGBE_MIN_INT_RATE 956
 #define IXGBE_MAX_EITR     0x00000FF8
 #define IXGBE_MIN_EITR     8
 #define IXGBE_EITR(_i)  (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \
                          (0x012300 + (((_i) - 24) * 4)))
 #define IXGBE_EITR_ITR_INT_MASK 0x00000FF8
 #define IXGBE_EITR_LLI_MOD      0x00008000
 #define IXGBE_EITR_CNT_WDIS     0x80000000
 #define IXGBE_IVAR(_i)  (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */
 #define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */
 #define IXGBE_EITRSEL   0x00894
 #define IXGBE_MSIXT     0x00000 /* MSI-X Table. 0x0000 - 0x01C */
 #define IXGBE_MSIXPBA   0x02000 /* MSI-X Pending bit array */
 #define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4)))
 #define IXGBE_GPIE      0x00898
 /* Flow Control Registers */
 #define IXGBE_FCADBUL   0x03210
 #define IXGBE_FCADBUH   0x03214
 #define IXGBE_FCAMACL   0x04328
 #define IXGBE_FCAMACH   0x0432C
 #define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_PFCTOP    0x03008
 #define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */
 #define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */
 #define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */
 #define IXGBE_FCRTV     0x032A0
 #define IXGBE_FCCFG     0x03D00
 #define IXGBE_TFCS      0x0CE00
 /* Receive DMA Registers */
 #define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \
 			 (0x0D000 + (((_i) - 64) * 0x40)))
 #define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \
 			 (0x0D004 + (((_i) - 64) * 0x40)))
 #define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \
 			 (0x0D008 + (((_i) - 64) * 0x40)))
 #define IXGBE_RDH(_i)   (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \
 			 (0x0D010 + (((_i) - 64) * 0x40)))
 #define IXGBE_RDT(_i)   (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \
 			 (0x0D018 + (((_i) - 64) * 0x40)))
 #define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \
 			 (0x0D028 + (((_i) - 64) * 0x40)))
 #define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \
 			 (0x0D02C + (((_i) - 64) * 0x40)))
 #define IXGBE_RSCDBU     0x03028
 #define IXGBE_RDDCC      0x02F20
 #define IXGBE_RXMEMWRAP  0x03190
 #define IXGBE_STARCTRL   0x03024
 /*
  * Split and Replication Receive Control Registers
  * 00-15 : 0x02100 + n*4
  * 16-64 : 0x01014 + n*0x40
  * 64-127: 0x0D014 + (n-64)*0x40
  */
 #define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \
                           (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \
 			  (0x0D014 + (((_i) - 64) * 0x40))))
 /*
  * Rx DCA Control Register:
  * 00-15 : 0x02200 + n*4
  * 16-64 : 0x0100C + n*0x40
  * 64-127: 0x0D00C + (n-64)*0x40
  */
 #define IXGBE_DCA_RXCTRL(_i)    (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \
                                  (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \
 				 (0x0D00C + (((_i) - 64) * 0x40))))
 #define IXGBE_RDRXCTL           0x02F00
 #define IXGBE_RXPBSIZE(_i)      (0x03C00 + ((_i) * 4))
                                              /* 8 of these 0x03C00 - 0x03C1C */
 #define IXGBE_RXCTRL    0x03000
 #define IXGBE_DROPEN    0x03D04
 #define IXGBE_RXPBSIZE_SHIFT 10
 /* Receive Registers */
 #define IXGBE_RXCSUM    0x05000
 #define IXGBE_RFCTL     0x05008
 #define IXGBE_DRECCCTL  0x02F08
 #define IXGBE_DRECCCTL_DISABLE 0
 /* Multicast Table Array - 128 entries */
 #define IXGBE_MTA(_i)   (0x05200 + ((_i) * 4))
 #define IXGBE_RAL(_i)   (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \
                          (0x0A200 + ((_i) * 8)))
 #define IXGBE_RAH(_i)   (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \
                          (0x0A204 + ((_i) * 8)))
 #define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8))
 #define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8))
 /* Packet split receive type */
 #define IXGBE_PSRTYPE(_i)    (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \
                               (0x0EA00 + ((_i) * 4)))
 /* array of 4096 1-bit vlan filters */
 #define IXGBE_VFTA(_i)  (0x0A000 + ((_i) * 4))
 /*array of 4096 4-bit vlan vmdq indices */
 #define IXGBE_VFTAVIND(_j, _i)  (0x0A200 + ((_j) * 0x200) + ((_i) * 4))
 #define IXGBE_FCTRL     0x05080
 #define IXGBE_VLNCTRL   0x05088
 #define IXGBE_MCSTCTRL  0x05090
 #define IXGBE_MRQC      0x05818
 #define IXGBE_SAQF(_i)  (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */
 #define IXGBE_DAQF(_i)  (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */
 #define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */
 #define IXGBE_FTQF(_i)  (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */
 #define IXGBE_ETQF(_i)  (0x05128 + ((_i) * 4)) /* EType Queue Filter */
 #define IXGBE_ETQS(_i)  (0x0EC00 + ((_i) * 4)) /* EType Queue Select */
 #define IXGBE_SYNQF     0x0EC30 /* SYN Packet Queue Filter */
 #define IXGBE_RQTC      0x0EC70
 #define IXGBE_MTQC      0x08120
 #define IXGBE_VLVF(_i)  (0x0F100 + ((_i) * 4))  /* 64 of these (0-63) */
 #define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4))  /* 128 of these (0-127) */
 #define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4))  /* 64 of these (0-63) */
 #define IXGBE_VT_CTL         0x051B0
 #define IXGBE_PFMAILBOX(_i)  (0x04B00 + (4 * (_i))) /* 64 total */
 #define IXGBE_PFMBMEM(_i)    (0x13000 + (64 * (_i))) /* 64 Mailboxes, 16 DW each */
 #define IXGBE_PFMBICR(_i)    (0x00710 + (4 * (_i))) /* 4 total */
 #define IXGBE_PFMBIMR(_i)    (0x00720 + (4 * (_i))) /* 4 total */
 #define IXGBE_VFRE(_i)       (0x051E0 + ((_i) * 4))
 #define IXGBE_VFTE(_i)       (0x08110 + ((_i) * 4))
 #define IXGBE_VMECM(_i)      (0x08790 + ((_i) * 4))
 #define IXGBE_QDE            0x2F04
 #define IXGBE_VMTXSW(_i)     (0x05180 + ((_i) * 4)) /* 2 total */
 #define IXGBE_VMOLR(_i)      (0x0F000 + ((_i) * 4)) /* 64 total */
 #define IXGBE_UTA(_i)        (0x0F400 + ((_i) * 4))
 #define IXGBE_MRCTL(_i)      (0x0F600 + ((_i) * 4))
 #define IXGBE_VMRVLAN(_i)    (0x0F610 + ((_i) * 4))
 #define IXGBE_VMRVM(_i)      (0x0F630 + ((_i) * 4))
 #define IXGBE_L34T_IMIR(_i)  (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/
 #define IXGBE_RXFECCERR0         0x051B8
 #define IXGBE_LLITHRESH 0x0EC90
 #define IXGBE_IMIR(_i)  (0x05A80 + ((_i) * 4))  /* 8 of these (0-7) */
 #define IXGBE_IMIREXT(_i)       (0x05AA0 + ((_i) * 4))  /* 8 of these (0-7) */
 #define IXGBE_IMIRVP    0x05AC0
 #define IXGBE_VMD_CTL   0x0581C
 #define IXGBE_RETA(_i)  (0x05C00 + ((_i) * 4))  /* 32 of these (0-31) */
 #define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4))  /* 10 of these (0-9) */
 /* Flow Director registers */
 #define IXGBE_FDIRCTRL  0x0EE00
 #define IXGBE_FDIRHKEY  0x0EE68
 #define IXGBE_FDIRSKEY  0x0EE6C
 #define IXGBE_FDIRDIP4M 0x0EE3C
 #define IXGBE_FDIRSIP4M 0x0EE40
 #define IXGBE_FDIRTCPM  0x0EE44
 #define IXGBE_FDIRUDPM  0x0EE48
 #define IXGBE_FDIRIP6M  0x0EE74
 #define IXGBE_FDIRM     0x0EE70
 /* Flow Director Stats registers */
 #define IXGBE_FDIRFREE  0x0EE38
 #define IXGBE_FDIRLEN   0x0EE4C
 #define IXGBE_FDIRUSTAT 0x0EE50
 #define IXGBE_FDIRFSTAT 0x0EE54
 #define IXGBE_FDIRMATCH 0x0EE58
 #define IXGBE_FDIRMISS  0x0EE5C
 /* Flow Director Programming registers */
 #define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */
 #define IXGBE_FDIRIPSA      0x0EE18
 #define IXGBE_FDIRIPDA      0x0EE1C
 #define IXGBE_FDIRPORT      0x0EE20
 #define IXGBE_FDIRVLAN      0x0EE24
 #define IXGBE_FDIRHASH      0x0EE28
 #define IXGBE_FDIRCMD       0x0EE2C
 /* Transmit DMA registers */
 #define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of these (0-31)*/
 #define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40))
 #define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40))
 #define IXGBE_TDH(_i)   (0x06010 + ((_i) * 0x40))
 #define IXGBE_TDT(_i)   (0x06018 + ((_i) * 0x40))
 #define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40))
 #define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40))
 #define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40))
 #define IXGBE_DTXCTL    0x07E00
 #define IXGBE_DMATXCTL      0x04A80
 #define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */
 #define IXGBE_PFDTXGSWC     0x08220
 #define IXGBE_DTXMXSZRQ     0x08100
 #define IXGBE_DTXTCPFLGL    0x04A88
 #define IXGBE_DTXTCPFLGH    0x04A8C
 #define IXGBE_LBDRPEN       0x0CA00
 #define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */
 #define IXGBE_DMATXCTL_TE       0x1 /* Transmit Enable */
 #define IXGBE_DMATXCTL_NS       0x2 /* No Snoop LSO hdr buffer */
 #define IXGBE_DMATXCTL_GDV      0x8 /* Global Double VLAN */
 #define IXGBE_DMATXCTL_VT_SHIFT 16  /* VLAN EtherType */
 #define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */
 /* Anti-spoofing defines */
 #define IXGBE_SPOOF_MACAS_MASK          0xFF
 #define IXGBE_SPOOF_VLANAS_MASK         0xFF00
 #define IXGBE_SPOOF_VLANAS_SHIFT        8
 #define IXGBE_PFVFSPOOF_REG_COUNT       8
 #define IXGBE_DCA_TXCTRL(_i)    (0x07200 + ((_i) * 4)) /* 16 of these (0-15) */
 /* Tx DCA Control register : 128 of these (0-127) */
 #define IXGBE_DCA_TXCTRL_82599(_i)  (0x0600C + ((_i) * 0x40))
 #define IXGBE_TIPG      0x0CB00
 #define IXGBE_TXPBSIZE(_i)      (0x0CC00 + ((_i) * 4)) /* 8 of these */
 #define IXGBE_MNGTXMAP  0x0CD10
 #define IXGBE_TIPG_FIBER_DEFAULT 3
 #define IXGBE_TXPBSIZE_SHIFT    10
 /* Wake up registers */
 #define IXGBE_WUC       0x05800
 #define IXGBE_WUFC      0x05808
 #define IXGBE_WUS       0x05810
 #define IXGBE_IPAV      0x05838
 #define IXGBE_IP4AT     0x05840 /* IPv4 table 0x5840-0x5858 */
 #define IXGBE_IP6AT     0x05880 /* IPv6 table 0x5880-0x588F */
 #define IXGBE_WUPL      0x05900
 #define IXGBE_WUPM      0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */
 #define IXGBE_FHFT(_n)	(0x09000 + ((_n) * 0x100)) /* Flex host filter table */
 #define IXGBE_FHFT_EXT(_n)	(0x09800 + ((_n) * 0x100)) /* Ext Flexible Host
 							    * Filter Table */
 #define IXGBE_FLEXIBLE_FILTER_COUNT_MAX         4
 #define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX     2
 /* Each Flexible Filter is at most 128 (0x80) bytes in length */
 #define IXGBE_FLEXIBLE_FILTER_SIZE_MAX  128
 #define IXGBE_FHFT_LENGTH_OFFSET        0xFC  /* Length byte in FHFT */
 #define IXGBE_FHFT_LENGTH_MASK          0x0FF /* Length in lower byte */
 /* Definitions for power management and wakeup registers */
 /* Wake Up Control */
 #define IXGBE_WUC_PME_EN     0x00000002 /* PME Enable */
 #define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */
 #define IXGBE_WUC_WKEN       0x00000010 /* Enable PE_WAKE_N pin assertion  */
 /* Wake Up Filter Control */
 #define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
 #define IXGBE_WUFC_MAG  0x00000002 /* Magic Packet Wakeup Enable */
 #define IXGBE_WUFC_EX   0x00000004 /* Directed Exact Wakeup Enable */
 #define IXGBE_WUFC_MC   0x00000008 /* Directed Multicast Wakeup Enable */
 #define IXGBE_WUFC_BC   0x00000010 /* Broadcast Wakeup Enable */
 #define IXGBE_WUFC_ARP  0x00000020 /* ARP Request Packet Wakeup Enable */
 #define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
 #define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
 #define IXGBE_WUFC_MNG  0x00000100 /* Directed Mgmt Packet Wakeup Enable */
 #define IXGBE_WUFC_IGNORE_TCO   0x00008000 /* Ignore WakeOn TCO packets */
 #define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
 #define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
 #define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
 #define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
 #define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */
 #define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */
 #define IXGBE_WUFC_FLX_FILTERS     0x000F0000 /* Mask for 4 flex filters */
 #define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 /* Mask for Ext. flex filters */
 #define IXGBE_WUFC_ALL_FILTERS     0x003F00FF /* Mask for all wakeup filters */
 #define IXGBE_WUFC_FLX_OFFSET      16 /* Offset to the Flexible Filters bits */
 /* Wake Up Status */
 #define IXGBE_WUS_LNKC  IXGBE_WUFC_LNKC
 #define IXGBE_WUS_MAG   IXGBE_WUFC_MAG
 #define IXGBE_WUS_EX    IXGBE_WUFC_EX
 #define IXGBE_WUS_MC    IXGBE_WUFC_MC
 #define IXGBE_WUS_BC    IXGBE_WUFC_BC
 #define IXGBE_WUS_ARP   IXGBE_WUFC_ARP
 #define IXGBE_WUS_IPV4  IXGBE_WUFC_IPV4
 #define IXGBE_WUS_IPV6  IXGBE_WUFC_IPV6
 #define IXGBE_WUS_MNG   IXGBE_WUFC_MNG
 #define IXGBE_WUS_FLX0  IXGBE_WUFC_FLX0
 #define IXGBE_WUS_FLX1  IXGBE_WUFC_FLX1
 #define IXGBE_WUS_FLX2  IXGBE_WUFC_FLX2
 #define IXGBE_WUS_FLX3  IXGBE_WUFC_FLX3
 #define IXGBE_WUS_FLX4  IXGBE_WUFC_FLX4
 #define IXGBE_WUS_FLX5  IXGBE_WUFC_FLX5
 #define IXGBE_WUS_FLX_FILTERS  IXGBE_WUFC_FLX_FILTERS
 /* Wake Up Packet Length */
 #define IXGBE_WUPL_LENGTH_MASK 0xFFFF
 /* DCB registers */
 #define MAX_TRAFFIC_CLASS        8
 #define X540_TRAFFIC_CLASS       4
 #define IXGBE_RMCS      0x03D00
 #define IXGBE_DPMCS     0x07F40
 #define IXGBE_PDPMCS    0x0CD00
 #define IXGBE_RUPPBMR   0x050A0
 #define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_TDTQ2TCCR(_i)     (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */
 #define IXGBE_TDTQ2TCSR(_i)     (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */
 #define IXGBE_TDPT2TCCR(_i)     (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_TDPT2TCSR(_i)     (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 /* Security Control Registers */
 #define IXGBE_SECTXCTRL         0x08800
 #define IXGBE_SECTXSTAT         0x08804
 #define IXGBE_SECTXBUFFAF       0x08808
 #define IXGBE_SECTXMINIFG       0x08810
 #define IXGBE_SECRXCTRL         0x08D00
 #define IXGBE_SECRXSTAT         0x08D04
 /* Security Bit Fields and Masks */
 #define IXGBE_SECTXCTRL_SECTX_DIS       0x00000001
 #define IXGBE_SECTXCTRL_TX_DIS          0x00000002
 #define IXGBE_SECTXCTRL_STORE_FORWARD   0x00000004
 #define IXGBE_SECTXSTAT_SECTX_RDY       0x00000001
 #define IXGBE_SECTXSTAT_ECC_TXERR       0x00000002
 #define IXGBE_SECRXCTRL_SECRX_DIS       0x00000001
 #define IXGBE_SECRXCTRL_RX_DIS          0x00000002
 #define IXGBE_SECRXSTAT_SECRX_RDY       0x00000001
 #define IXGBE_SECRXSTAT_ECC_RXERR       0x00000002
 /* LinkSec (MacSec) Registers */
 #define IXGBE_LSECTXCAP         0x08A00
 #define IXGBE_LSECRXCAP         0x08F00
 #define IXGBE_LSECTXCTRL        0x08A04
 #define IXGBE_LSECTXSCL         0x08A08 /* SCI Low */
 #define IXGBE_LSECTXSCH         0x08A0C /* SCI High */
 #define IXGBE_LSECTXSA          0x08A10
 #define IXGBE_LSECTXPN0         0x08A14
 #define IXGBE_LSECTXPN1         0x08A18
 #define IXGBE_LSECTXKEY0(_n)    (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */
 #define IXGBE_LSECTXKEY1(_n)    (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */
 #define IXGBE_LSECRXCTRL        0x08F04
 #define IXGBE_LSECRXSCL         0x08F08
 #define IXGBE_LSECRXSCH         0x08F0C
 #define IXGBE_LSECRXSA(_i)      (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */
 #define IXGBE_LSECRXPN(_i)      (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */
 #define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m))))
 #define IXGBE_LSECTXUT          0x08A3C /* OutPktsUntagged */
 #define IXGBE_LSECTXPKTE        0x08A40 /* OutPktsEncrypted */
 #define IXGBE_LSECTXPKTP        0x08A44 /* OutPktsProtected */
 #define IXGBE_LSECTXOCTE        0x08A48 /* OutOctetsEncrypted */
 #define IXGBE_LSECTXOCTP        0x08A4C /* OutOctetsProtected */
 #define IXGBE_LSECRXUT          0x08F40 /* InPktsUntagged/InPktsNoTag */
 #define IXGBE_LSECRXOCTD        0x08F44 /* InOctetsDecrypted */
 #define IXGBE_LSECRXOCTV        0x08F48 /* InOctetsValidated */
 #define IXGBE_LSECRXBAD         0x08F4C /* InPktsBadTag */
 #define IXGBE_LSECRXNOSCI       0x08F50 /* InPktsNoSci */
 #define IXGBE_LSECRXUNSCI       0x08F54 /* InPktsUnknownSci */
 #define IXGBE_LSECRXUNCH        0x08F58 /* InPktsUnchecked */
 #define IXGBE_LSECRXDELAY       0x08F5C /* InPktsDelayed */
 #define IXGBE_LSECRXLATE        0x08F60 /* InPktsLate */
 #define IXGBE_LSECRXOK(_n)      (0x08F64 + (0x04 * (_n))) /* InPktsOk */
 #define IXGBE_LSECRXINV(_n)     (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */
 #define IXGBE_LSECRXNV(_n)      (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */
 #define IXGBE_LSECRXUNSA        0x08F7C /* InPktsUnusedSa */
 #define IXGBE_LSECRXNUSA        0x08F80 /* InPktsNotUsingSa */
 /* LinkSec (MacSec) Bit Fields and Masks */
 #define IXGBE_LSECTXCAP_SUM_MASK        0x00FF0000
 #define IXGBE_LSECTXCAP_SUM_SHIFT       16
 #define IXGBE_LSECRXCAP_SUM_MASK        0x00FF0000
 #define IXGBE_LSECRXCAP_SUM_SHIFT       16
 #define IXGBE_LSECTXCTRL_EN_MASK        0x00000003
 #define IXGBE_LSECTXCTRL_DISABLE        0x0
 #define IXGBE_LSECTXCTRL_AUTH           0x1
 #define IXGBE_LSECTXCTRL_AUTH_ENCRYPT   0x2
 #define IXGBE_LSECTXCTRL_AISCI          0x00000020
 #define IXGBE_LSECTXCTRL_PNTHRSH_MASK   0xFFFFFF00
 #define IXGBE_LSECTXCTRL_RSV_MASK       0x000000D8
 #define IXGBE_LSECRXCTRL_EN_MASK        0x0000000C
 #define IXGBE_LSECRXCTRL_EN_SHIFT       2
 #define IXGBE_LSECRXCTRL_DISABLE        0x0
 #define IXGBE_LSECRXCTRL_CHECK          0x1
 #define IXGBE_LSECRXCTRL_STRICT         0x2
 #define IXGBE_LSECRXCTRL_DROP           0x3
 #define IXGBE_LSECRXCTRL_PLSH           0x00000040
 #define IXGBE_LSECRXCTRL_RP             0x00000080
 #define IXGBE_LSECRXCTRL_RSV_MASK       0xFFFFFF33
 /* IpSec Registers */
 #define IXGBE_IPSTXIDX          0x08900
 #define IXGBE_IPSTXSALT         0x08904
 #define IXGBE_IPSTXKEY(_i)      (0x08908 + (4 * (_i))) /* 4 of these (0-3) */
 #define IXGBE_IPSRXIDX          0x08E00
 #define IXGBE_IPSRXIPADDR(_i)   (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */
 #define IXGBE_IPSRXSPI          0x08E14
 #define IXGBE_IPSRXIPIDX        0x08E18
 #define IXGBE_IPSRXKEY(_i)      (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */
 #define IXGBE_IPSRXSALT         0x08E2C
 #define IXGBE_IPSRXMOD          0x08E30
 #define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE    0x4
 /* DCB registers */
 #define IXGBE_RTRPCS      0x02430
 #define IXGBE_RTTDCS      0x04900
 #define IXGBE_RTTDCS_ARBDIS     0x00000040 /* DCB arbiter disable */
 #define IXGBE_RTTPCS      0x0CD00
 #define IXGBE_RTRUP2TC    0x03020
 #define IXGBE_RTTUP2TC    0x0C800
 #define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_TXLLQ(_i)   (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */
 #define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_RTTDQSEL    0x04904
 #define IXGBE_RTTDT1C     0x04908
 #define IXGBE_RTTDT1S     0x0490C
 #define IXGBE_RTTDTECC    0x04990
 #define IXGBE_RTTDTECC_NO_BCN   0x00000100
 #define IXGBE_RTTBCNRC    0x04984
 #define IXGBE_RTTBCNRC_RS_ENA	0x80000000
 #define IXGBE_RTTBCNRC_RF_DEC_MASK	0x00003FFF
 #define IXGBE_RTTBCNRC_RF_INT_SHIFT	14
 #define IXGBE_RTTBCNRC_RF_INT_MASK	\
 	(IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT)
 #define IXGBE_RTTBCNRM    0x04980
 /* FCoE DMA Context Registers */
 #define IXGBE_FCPTRL    0x02410 /* FC User Desc. PTR Low */
 #define IXGBE_FCPTRH    0x02414 /* FC USer Desc. PTR High */
 #define IXGBE_FCBUFF    0x02418 /* FC Buffer Control */
 #define IXGBE_FCDMARW   0x02420 /* FC Receive DMA RW */
 #define IXGBE_FCINVST0  0x03FC0 /* FC Invalid DMA Context Status Reg 0 */
 #define IXGBE_FCINVST(_i)       (IXGBE_FCINVST0 + ((_i) * 4))
 #define IXGBE_FCBUFF_VALID      (1 << 0)   /* DMA Context Valid */
 #define IXGBE_FCBUFF_BUFFSIZE   (3 << 3)   /* User Buffer Size */
 #define IXGBE_FCBUFF_WRCONTX    (1 << 7)   /* 0: Initiator, 1: Target */
 #define IXGBE_FCBUFF_BUFFCNT    0x0000ff00 /* Number of User Buffers */
 #define IXGBE_FCBUFF_OFFSET     0xffff0000 /* User Buffer Offset */
 #define IXGBE_FCBUFF_BUFFSIZE_SHIFT  3
 #define IXGBE_FCBUFF_BUFFCNT_SHIFT   8
 #define IXGBE_FCBUFF_OFFSET_SHIFT    16
 #define IXGBE_FCDMARW_WE        (1 << 14)   /* Write enable */
 #define IXGBE_FCDMARW_RE        (1 << 15)   /* Read enable */
 #define IXGBE_FCDMARW_FCOESEL   0x000001ff  /* FC X_ID: 11 bits */
 #define IXGBE_FCDMARW_LASTSIZE  0xffff0000  /* Last User Buffer Size */
 #define IXGBE_FCDMARW_LASTSIZE_SHIFT 16
 /* FCoE SOF/EOF */
 #define IXGBE_TEOFF     0x04A94 /* Tx FC EOF */
 #define IXGBE_TSOFF     0x04A98 /* Tx FC SOF */
 #define IXGBE_REOFF     0x05158 /* Rx FC EOF */
 #define IXGBE_RSOFF     0x051F8 /* Rx FC SOF */
 /* FCoE Filter Context Registers */
 #define IXGBE_FCFLT     0x05108 /* FC FLT Context */
 #define IXGBE_FCFLTRW   0x05110 /* FC Filter RW Control */
 #define IXGBE_FCPARAM   0x051d8 /* FC Offset Parameter */
 #define IXGBE_FCFLT_VALID       (1 << 0)   /* Filter Context Valid */
 #define IXGBE_FCFLT_FIRST       (1 << 1)   /* Filter First */
 #define IXGBE_FCFLT_SEQID       0x00ff0000 /* Sequence ID */
 #define IXGBE_FCFLT_SEQCNT      0xff000000 /* Sequence Count */
 #define IXGBE_FCFLTRW_RVALDT    (1 << 13)  /* Fast Re-Validation */
 #define IXGBE_FCFLTRW_WE        (1 << 14)  /* Write Enable */
 #define IXGBE_FCFLTRW_RE        (1 << 15)  /* Read Enable */
 /* FCoE Receive Control */
 #define IXGBE_FCRXCTRL  0x05100 /* FC Receive Control */
 #define IXGBE_FCRXCTRL_FCOELLI  (1 << 0)   /* Low latency interrupt */
 #define IXGBE_FCRXCTRL_SAVBAD   (1 << 1)   /* Save Bad Frames */
 #define IXGBE_FCRXCTRL_FRSTRDH  (1 << 2)   /* EN 1st Read Header */
 #define IXGBE_FCRXCTRL_LASTSEQH (1 << 3)   /* EN Last Header in Seq */
 #define IXGBE_FCRXCTRL_ALLH     (1 << 4)   /* EN All Headers */
 #define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5)   /* EN 1st Seq. Header */
 #define IXGBE_FCRXCTRL_ICRC     (1 << 6)   /* Ignore Bad FC CRC */
 #define IXGBE_FCRXCTRL_FCCRCBO  (1 << 7)   /* FC CRC Byte Ordering */
 #define IXGBE_FCRXCTRL_FCOEVER  0x00000f00 /* FCoE Version: 4 bits */
 #define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8
 /* FCoE Redirection */
 #define IXGBE_FCRECTL   0x0ED00 /* FC Redirection Control */
 #define IXGBE_FCRETA0   0x0ED10 /* FC Redirection Table 0 */
 #define IXGBE_FCRETA(_i)        (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */
 #define IXGBE_FCRECTL_ENA       0x1        /* FCoE Redir Table Enable */
 #define IXGBE_FCRETA_SIZE       8          /* Max entries in FCRETA */
 #define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */
 /* Stats registers */
 #define IXGBE_CRCERRS   0x04000
 #define IXGBE_ILLERRC   0x04004
 #define IXGBE_ERRBC     0x04008
 #define IXGBE_MSPDC     0x04010
 #define IXGBE_MPC(_i)   (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/
 #define IXGBE_MLFC      0x04034
 #define IXGBE_MRFC      0x04038
 #define IXGBE_RLEC      0x04040
 #define IXGBE_LXONTXC   0x03F60
 #define IXGBE_LXONRXC   0x0CF60
 #define IXGBE_LXOFFTXC  0x03F68
 #define IXGBE_LXOFFRXC  0x0CF68
 #define IXGBE_LXONRXCNT 0x041A4
 #define IXGBE_LXOFFRXCNT 0x041A8
 #define IXGBE_PXONRXCNT(_i)     (0x04140 + ((_i) * 4)) /* 8 of these */
 #define IXGBE_PXOFFRXCNT(_i)    (0x04160 + ((_i) * 4)) /* 8 of these */
 #define IXGBE_PXON2OFFCNT(_i)   (0x03240 + ((_i) * 4)) /* 8 of these */
 #define IXGBE_PXONTXC(_i)       (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/
 #define IXGBE_PXONRXC(_i)       (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/
 #define IXGBE_PXOFFTXC(_i)      (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/
 #define IXGBE_PXOFFRXC(_i)      (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/
 #define IXGBE_PRC64     0x0405C
 #define IXGBE_PRC127    0x04060
 #define IXGBE_PRC255    0x04064
 #define IXGBE_PRC511    0x04068
 #define IXGBE_PRC1023   0x0406C
 #define IXGBE_PRC1522   0x04070
 #define IXGBE_GPRC      0x04074
 #define IXGBE_BPRC      0x04078
 #define IXGBE_MPRC      0x0407C
 #define IXGBE_GPTC      0x04080
 #define IXGBE_GORCL     0x04088
 #define IXGBE_GORCH     0x0408C
 #define IXGBE_GOTCL     0x04090
 #define IXGBE_GOTCH     0x04094
 #define IXGBE_RNBC(_i)  (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/
 #define IXGBE_RUC       0x040A4
 #define IXGBE_RFC       0x040A8
 #define IXGBE_ROC       0x040AC
 #define IXGBE_RJC       0x040B0
 #define IXGBE_MNGPRC    0x040B4
 #define IXGBE_MNGPDC    0x040B8
 #define IXGBE_MNGPTC    0x0CF90
 #define IXGBE_TORL      0x040C0
 #define IXGBE_TORH      0x040C4
 #define IXGBE_TPR       0x040D0
 #define IXGBE_TPT       0x040D4
 #define IXGBE_PTC64     0x040D8
 #define IXGBE_PTC127    0x040DC
 #define IXGBE_PTC255    0x040E0
 #define IXGBE_PTC511    0x040E4
 #define IXGBE_PTC1023   0x040E8
 #define IXGBE_PTC1522   0x040EC
 #define IXGBE_MPTC      0x040F0
 #define IXGBE_BPTC      0x040F4
 #define IXGBE_XEC       0x04120
 #define IXGBE_SSVPC     0x08780
 #define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4))
 #define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \
                          (0x08600 + ((_i) * 4)))
 #define IXGBE_TQSM(_i)  (0x08600 + ((_i) * 4))
 #define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */
 #define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */
 #define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
 #define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */
 #define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */
 #define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */
 #define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */
 #define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */
 #define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */
 #define IXGBE_FCCRC     0x05118 /* Count of Good Eth CRC w/ Bad FC CRC */
 #define IXGBE_FCOERPDC  0x0241C /* FCoE Rx Packets Dropped Count */
 #define IXGBE_FCLAST    0x02424 /* FCoE Last Error Count */
 #define IXGBE_FCOEPRC   0x02428 /* Number of FCoE Packets Received */
 #define IXGBE_FCOEDWRC  0x0242C /* Number of FCoE DWords Received */
 #define IXGBE_FCOEPTC   0x08784 /* Number of FCoE Packets Transmitted */
 #define IXGBE_FCOEDWTC  0x08788 /* Number of FCoE DWords Transmitted */
 #define IXGBE_O2BGPTC   0x041C4
 #define IXGBE_O2BSPC    0x087B0
 #define IXGBE_B2OSPC    0x041C0
 #define IXGBE_B2OGPRC   0x02F90
 #define IXGBE_PCRC8ECL  0x0E810
 #define IXGBE_PCRC8ECH  0x0E811
 #define IXGBE_PCRC8ECH_MASK     0x1F
 #define IXGBE_LDPCECL   0x0E820
 #define IXGBE_LDPCECH   0x0E821
 /* Management */
 #define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_MANC      0x05820
 #define IXGBE_MFVAL     0x05824
 #define IXGBE_MANC2H    0x05860
 #define IXGBE_MDEF(_i)  (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_MIPAF     0x058B0
 #define IXGBE_MMAL(_i)  (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */
 #define IXGBE_MMAH(_i)  (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */
 #define IXGBE_FTFT      0x09400 /* 0x9400-0x97FC */
 #define IXGBE_METF(_i)  (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */
 #define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */
 #define IXGBE_LSWFW     0x15014
 /* Management Bit Fields and Masks */
 #define IXGBE_MANC_RCV_TCO_EN	0x00020000 /* Rcv TCO packet enable */
 /* Firmware Semaphore Register */
 #define IXGBE_FWSM_MODE_MASK	0xE
 #define IXGBE_FWSM_FW_MODE_PT	0x4
 /* ARC Subsystem registers */
 #define IXGBE_HICR      0x15F00
 #define IXGBE_FWSTS     0x15F0C
 #define IXGBE_HSMC0R    0x15F04
 #define IXGBE_HSMC1R    0x15F08
 #define IXGBE_SWSR      0x15F10
 #define IXGBE_HFDR      0x15FE8
 #define IXGBE_FLEX_MNG  0x15800 /* 0x15800 - 0x15EFC */
 #define IXGBE_HICR_EN              0x01  /* Enable bit - RO */
 /* Driver sets this bit when done to put command in RAM */
 #define IXGBE_HICR_C               0x02
 #define IXGBE_HICR_SV              0x04  /* Status Validity */
 #define IXGBE_HICR_FW_RESET_ENABLE 0x40
 #define IXGBE_HICR_FW_RESET        0x80
 /* PCI-E registers */
 #define IXGBE_GCR       0x11000
 #define IXGBE_GTV       0x11004
 #define IXGBE_FUNCTAG   0x11008
 #define IXGBE_GLT       0x1100C
 #define IXGBE_GSCL_1    0x11010
 #define IXGBE_GSCL_2    0x11014
 #define IXGBE_GSCL_3    0x11018
 #define IXGBE_GSCL_4    0x1101C
 #define IXGBE_GSCN_0    0x11020
 #define IXGBE_GSCN_1    0x11024
 #define IXGBE_GSCN_2    0x11028
 #define IXGBE_GSCN_3    0x1102C
 #define IXGBE_FACTPS    0x10150
 #define IXGBE_PCIEANACTL  0x11040
 #define IXGBE_SWSM      0x10140
 #define IXGBE_FWSM      0x10148
 #define IXGBE_GSSR      0x10160
 #define IXGBE_MREVID    0x11064
 #define IXGBE_DCA_ID    0x11070
 #define IXGBE_DCA_CTRL  0x11074
 #define IXGBE_SWFW_SYNC IXGBE_GSSR
 /* PCIe registers 82599-specific */
 #define IXGBE_GCR_EXT           0x11050
 #define IXGBE_GSCL_5_82599      0x11030
 #define IXGBE_GSCL_6_82599      0x11034
 #define IXGBE_GSCL_7_82599      0x11038
 #define IXGBE_GSCL_8_82599      0x1103C
 #define IXGBE_PHYADR_82599      0x11040
 #define IXGBE_PHYDAT_82599      0x11044
 #define IXGBE_PHYCTL_82599      0x11048
 #define IXGBE_PBACLR_82599      0x11068
 #define IXGBE_CIAA_82599        0x11088
 #define IXGBE_CIAD_82599        0x1108C
 #define IXGBE_PICAUSE           0x110B0
 #define IXGBE_PIENA             0x110B8
 #define IXGBE_CDQ_MBR_82599     0x110B4
 #define IXGBE_PCIESPARE         0x110BC
 #define IXGBE_MISC_REG_82599    0x110F0
 #define IXGBE_ECC_CTRL_0_82599  0x11100
 #define IXGBE_ECC_CTRL_1_82599  0x11104
 #define IXGBE_ECC_STATUS_82599  0x110E0
 #define IXGBE_BAR_CTRL_82599    0x110F4
 /* PCI Express Control */
 #define IXGBE_GCR_CMPL_TMOUT_MASK       0x0000F000
 #define IXGBE_GCR_CMPL_TMOUT_10ms       0x00001000
 #define IXGBE_GCR_CMPL_TMOUT_RESEND     0x00010000
 #define IXGBE_GCR_CAP_VER2              0x00040000
 #define IXGBE_GCR_EXT_MSIX_EN           0x80000000
 #define IXGBE_GCR_EXT_BUFFERS_CLEAR     0x40000000
 #define IXGBE_GCR_EXT_VT_MODE_16        0x00000001
 #define IXGBE_GCR_EXT_VT_MODE_32        0x00000002
 #define IXGBE_GCR_EXT_VT_MODE_64        0x00000003
 #define IXGBE_GCR_EXT_SRIOV             (IXGBE_GCR_EXT_MSIX_EN | \
                                          IXGBE_GCR_EXT_VT_MODE_64)
 /* Time Sync Registers */
 #define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */
 #define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */
 #define IXGBE_RXSTMPL    0x051E8 /* Rx timestamp Low - RO */
 #define IXGBE_RXSTMPH    0x051A4 /* Rx timestamp High - RO */
 #define IXGBE_RXSATRL    0x051A0 /* Rx timestamp attribute low - RO */
 #define IXGBE_RXSATRH    0x051A8 /* Rx timestamp attribute high - RO */
 #define IXGBE_RXMTRL     0x05120 /* RX message type register low - RW */
 #define IXGBE_TXSTMPL    0x08C04 /* Tx timestamp value Low - RO */
 #define IXGBE_TXSTMPH    0x08C08 /* Tx timestamp value High - RO */
 #define IXGBE_SYSTIML    0x08C0C /* System time register Low - RO */
 #define IXGBE_SYSTIMH    0x08C10 /* System time register High - RO */
 #define IXGBE_TIMINCA    0x08C14 /* Increment attributes register - RW */
 #define IXGBE_TIMADJL    0x08C18 /* Time Adjustment Offset register Low - RW */
 #define IXGBE_TIMADJH    0x08C1C /* Time Adjustment Offset register High - RW */
 #define IXGBE_TSAUXC     0x08C20 /* TimeSync Auxiliary Control register - RW */
 #define IXGBE_TRGTTIML0  0x08C24 /* Target Time Register 0 Low - RW */
 #define IXGBE_TRGTTIMH0  0x08C28 /* Target Time Register 0 High - RW */
 #define IXGBE_TRGTTIML1  0x08C2C /* Target Time Register 1 Low - RW */
 #define IXGBE_TRGTTIMH1  0x08C30 /* Target Time Register 1 High - RW */
 #define IXGBE_CLKTIML    0x08C34 /* Clock Out Time Register Low - RW */
 #define IXGBE_CLKTIMH    0x08C38 /* Clock Out Time Register High - RW */
 #define IXGBE_FREQOUT0   0x08C34 /* Frequency Out 0 Control register - RW */
 #define IXGBE_FREQOUT1   0x08C38 /* Frequency Out 1 Control register - RW */
 #define IXGBE_AUXSTMPL0  0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */
 #define IXGBE_AUXSTMPH0  0x08C40 /* Auxiliary Time Stamp 0 register High - RO */
 #define IXGBE_AUXSTMPL1  0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */
 #define IXGBE_AUXSTMPH1  0x08C48 /* Auxiliary Time Stamp 1 register High - RO */
 /* Diagnostic Registers */
 #define IXGBE_RDSTATCTL   0x02C20
 #define IXGBE_RDSTAT(_i)  (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */
 #define IXGBE_RDHMPN      0x02F08
 #define IXGBE_RIC_DW(_i)  (0x02F10 + ((_i) * 4))
 #define IXGBE_RDPROBE     0x02F20
 #define IXGBE_RDMAM       0x02F30
 #define IXGBE_RDMAD       0x02F34
 #define IXGBE_TDSTATCTL   0x07C20
 #define IXGBE_TDSTAT(_i)  (0x07C00 + ((_i) * 4)) /* 0x07C00 - 0x07C1C */
 #define IXGBE_TDHMPN      0x07F08
 #define IXGBE_TDHMPN2     0x082FC
 #define IXGBE_TXDESCIC    0x082CC
 #define IXGBE_TIC_DW(_i)  (0x07F10 + ((_i) * 4))
 #define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4))
 #define IXGBE_TDPROBE     0x07F20
 #define IXGBE_TXBUFCTRL   0x0C600
 #define IXGBE_TXBUFDATA0  0x0C610
 #define IXGBE_TXBUFDATA1  0x0C614
 #define IXGBE_TXBUFDATA2  0x0C618
 #define IXGBE_TXBUFDATA3  0x0C61C
 #define IXGBE_RXBUFCTRL   0x03600
 #define IXGBE_RXBUFDATA0  0x03610
 #define IXGBE_RXBUFDATA1  0x03614
 #define IXGBE_RXBUFDATA2  0x03618
 #define IXGBE_RXBUFDATA3  0x0361C
 #define IXGBE_PCIE_DIAG(_i)     (0x11090 + ((_i) * 4)) /* 8 of these */
 #define IXGBE_RFVAL     0x050A4
 #define IXGBE_MDFTC1    0x042B8
 #define IXGBE_MDFTC2    0x042C0
 #define IXGBE_MDFTFIFO1 0x042C4
 #define IXGBE_MDFTFIFO2 0x042C8
 #define IXGBE_MDFTS     0x042CC
 #define IXGBE_RXDATAWRPTR(_i)   (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/
 #define IXGBE_RXDESCWRPTR(_i)   (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/
 #define IXGBE_RXDATARDPTR(_i)   (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/
 #define IXGBE_RXDESCRDPTR(_i)   (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/
 #define IXGBE_TXDATAWRPTR(_i)   (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/
 #define IXGBE_TXDESCWRPTR(_i)   (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/
 #define IXGBE_TXDATARDPTR(_i)   (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/
 #define IXGBE_TXDESCRDPTR(_i)   (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/
 #define IXGBE_PCIEECCCTL 0x1106C
 #define IXGBE_RXWRPTR(_i)       (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/
 #define IXGBE_RXUSED(_i)        (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/
 #define IXGBE_RXRDPTR(_i)       (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/
 #define IXGBE_RXRDWRPTR(_i)     (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/
 #define IXGBE_TXWRPTR(_i)       (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/
 #define IXGBE_TXUSED(_i)        (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/
 #define IXGBE_TXRDPTR(_i)       (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/
 #define IXGBE_TXRDWRPTR(_i)     (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/
 #define IXGBE_PCIEECCCTL0 0x11100
 #define IXGBE_PCIEECCCTL1 0x11104
 #define IXGBE_RXDBUECC  0x03F70
 #define IXGBE_TXDBUECC  0x0CF70
 #define IXGBE_RXDBUEST 0x03F74
 #define IXGBE_TXDBUEST 0x0CF74
 #define IXGBE_PBTXECC   0x0C300
 #define IXGBE_PBRXECC   0x03300
 #define IXGBE_GHECCR    0x110B0
 /* MAC Registers */
 #define IXGBE_PCS1GCFIG 0x04200
 #define IXGBE_PCS1GLCTL 0x04208
 #define IXGBE_PCS1GLSTA 0x0420C
 #define IXGBE_PCS1GDBG0 0x04210
 #define IXGBE_PCS1GDBG1 0x04214
 #define IXGBE_PCS1GANA  0x04218
 #define IXGBE_PCS1GANLP 0x0421C
 #define IXGBE_PCS1GANNP 0x04220
 #define IXGBE_PCS1GANLPNP 0x04224
 #define IXGBE_HLREG0    0x04240
 #define IXGBE_HLREG1    0x04244
 #define IXGBE_PAP       0x04248
 #define IXGBE_MACA      0x0424C
 #define IXGBE_APAE      0x04250
 #define IXGBE_ARD       0x04254
 #define IXGBE_AIS       0x04258
 #define IXGBE_MSCA      0x0425C
 #define IXGBE_MSRWD     0x04260
 #define IXGBE_MLADD     0x04264
 #define IXGBE_MHADD     0x04268
 #define IXGBE_MAXFRS    0x04268
 #define IXGBE_TREG      0x0426C
 #define IXGBE_PCSS1     0x04288
 #define IXGBE_PCSS2     0x0428C
 #define IXGBE_XPCSS     0x04290
 #define IXGBE_MFLCN     0x04294
 #define IXGBE_SERDESC   0x04298
 #define IXGBE_MACS      0x0429C
 #define IXGBE_AUTOC     0x042A0
 #define IXGBE_LINKS     0x042A4
 #define IXGBE_LINKS2    0x04324
 #define IXGBE_AUTOC2    0x042A8
 #define IXGBE_AUTOC3    0x042AC
 #define IXGBE_ANLP1     0x042B0
 #define IXGBE_ANLP2     0x042B4
 #define IXGBE_MACC      0x04330
 #define IXGBE_ATLASCTL  0x04800
 #define IXGBE_MMNGC     0x042D0
 #define IXGBE_ANLPNP1   0x042D4
 #define IXGBE_ANLPNP2   0x042D8
 #define IXGBE_KRPCSFC   0x042E0
 #define IXGBE_KRPCSS    0x042E4
 #define IXGBE_FECS1     0x042E8
 #define IXGBE_FECS2     0x042EC
 #define IXGBE_SMADARCTL 0x14F10
 #define IXGBE_MPVC      0x04318
 #define IXGBE_SGMIIC    0x04314
 /* Statistics Registers */
 #define IXGBE_RXNFGPC      0x041B0
 #define IXGBE_RXNFGBCL     0x041B4
 #define IXGBE_RXNFGBCH     0x041B8
 #define IXGBE_RXDGPC       0x02F50
 #define IXGBE_RXDGBCL      0x02F54
 #define IXGBE_RXDGBCH      0x02F58
 #define IXGBE_RXDDGPC      0x02F5C
 #define IXGBE_RXDDGBCL     0x02F60
 #define IXGBE_RXDDGBCH     0x02F64
 #define IXGBE_RXLPBKGPC    0x02F68
 #define IXGBE_RXLPBKGBCL   0x02F6C
 #define IXGBE_RXLPBKGBCH   0x02F70
 #define IXGBE_RXDLPBKGPC   0x02F74
 #define IXGBE_RXDLPBKGBCL  0x02F78
 #define IXGBE_RXDLPBKGBCH  0x02F7C
 #define IXGBE_TXDGPC       0x087A0
 #define IXGBE_TXDGBCL      0x087A4
 #define IXGBE_TXDGBCH      0x087A8
 #define IXGBE_RXDSTATCTRL 0x02F40
 /* Copper Pond 2 link timeout */
 #define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50
 /* Omer CORECTL */
 #define IXGBE_CORECTL           0x014F00
 /* BARCTRL */
 #define IXGBE_BARCTRL               0x110F4
 #define IXGBE_BARCTRL_FLSIZE        0x0700
 #define IXGBE_BARCTRL_FLSIZE_SHIFT  8
 #define IXGBE_BARCTRL_CSRSIZE       0x2000
 /* RSCCTL Bit Masks */
 #define IXGBE_RSCCTL_RSCEN          0x01
 #define IXGBE_RSCCTL_MAXDESC_1      0x00
 #define IXGBE_RSCCTL_MAXDESC_4      0x04
 #define IXGBE_RSCCTL_MAXDESC_8      0x08
 #define IXGBE_RSCCTL_MAXDESC_16     0x0C
 /* RSCDBU Bit Masks */
 #define IXGBE_RSCDBU_RSCSMALDIS_MASK    0x0000007F
 #define IXGBE_RSCDBU_RSCACKDIS          0x00000080
 /* RDRXCTL Bit Masks */
 #define IXGBE_RDRXCTL_RDMTS_1_2     0x00000000 /* Rx Desc Min Threshold Size */
 #define IXGBE_RDRXCTL_CRCSTRIP      0x00000002 /* CRC Strip */
 #define IXGBE_RDRXCTL_MVMEN         0x00000020
 #define IXGBE_RDRXCTL_DMAIDONE      0x00000008 /* DMA init cycle done */
 #define IXGBE_RDRXCTL_AGGDIS        0x00010000 /* Aggregation disable */
 #define IXGBE_RDRXCTL_RSCFRSTSIZE   0x003E0000 /* RSC First packet size */
 #define IXGBE_RDRXCTL_RSCLLIDIS     0x00800000 /* Disable RSC compl on LLI */
 #define IXGBE_RDRXCTL_RSCACKC       0x02000000 /* must set 1 when RSC enabled */
 #define IXGBE_RDRXCTL_FCOE_WRFIX    0x04000000 /* must set 1 when RSC enabled */
 /* RQTC Bit Masks and Shifts */
 #define IXGBE_RQTC_SHIFT_TC(_i)     ((_i) * 4)
 #define IXGBE_RQTC_TC0_MASK         (0x7 << 0)
 #define IXGBE_RQTC_TC1_MASK         (0x7 << 4)
 #define IXGBE_RQTC_TC2_MASK         (0x7 << 8)
 #define IXGBE_RQTC_TC3_MASK         (0x7 << 12)
 #define IXGBE_RQTC_TC4_MASK         (0x7 << 16)
 #define IXGBE_RQTC_TC5_MASK         (0x7 << 20)
 #define IXGBE_RQTC_TC6_MASK         (0x7 << 24)
 #define IXGBE_RQTC_TC7_MASK         (0x7 << 28)
 /* PSRTYPE.RQPL Bit masks and shift */
 #define IXGBE_PSRTYPE_RQPL_MASK     0x7
 #define IXGBE_PSRTYPE_RQPL_SHIFT    29
 /* CTRL Bit Masks */
 #define IXGBE_CTRL_GIO_DIS      0x00000004 /* Global IO Master Disable bit */
 #define IXGBE_CTRL_LNK_RST      0x00000008 /* Link Reset. Resets everything. */
 #define IXGBE_CTRL_RST          0x04000000 /* Reset (SW) */
 #define IXGBE_CTRL_RST_MASK     (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
 /* FACTPS */
 #define IXGBE_FACTPS_MNGCG      0x20000000 /* Manageblility Clock Gated */
 #define IXGBE_FACTPS_LFS        0x40000000 /* LAN Function Select */
 /* MHADD Bit Masks */
 #define IXGBE_MHADD_MFS_MASK    0xFFFF0000
 #define IXGBE_MHADD_MFS_SHIFT   16
 /* Extended Device Control */
 #define IXGBE_CTRL_EXT_PFRSTD   0x00004000 /* Physical Function Reset Done */
 #define IXGBE_CTRL_EXT_NS_DIS   0x00010000 /* No Snoop disable */
 #define IXGBE_CTRL_EXT_RO_DIS   0x00020000 /* Relaxed Ordering disable */
 #define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */
 /* Direct Cache Access (DCA) definitions */
 #define IXGBE_DCA_CTRL_DCA_ENABLE  0x00000000 /* DCA Enable */
 #define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */
 #define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */
 #define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */
 #define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */
 #define IXGBE_DCA_RXCTRL_CPUID_MASK_82599  0xFF000000 /* Rx CPUID Mask */
 #define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */
 #define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* DCA Rx Desc enable */
 #define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* DCA Rx Desc header enable */
 #define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* DCA Rx Desc payload enable */
 #define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* DCA Rx rd Desc Relax Order */
 #define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */
 #define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */
 #define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */
 #define IXGBE_DCA_TXCTRL_CPUID_MASK_82599  0xFF000000 /* Tx CPUID Mask */
 #define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */
 #define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */
 #define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */
 #define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */
 #define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */
 #define IXGBE_DCA_MAX_QUEUES_82598   16 /* DCA regs only on 16 queues */
 /* MSCA Bit Masks */
 #define IXGBE_MSCA_NP_ADDR_MASK      0x0000FFFF /* MDI Address (new protocol) */
 #define IXGBE_MSCA_NP_ADDR_SHIFT     0
 #define IXGBE_MSCA_DEV_TYPE_MASK     0x001F0000 /* Device Type (new protocol) */
 #define IXGBE_MSCA_DEV_TYPE_SHIFT    16 /* Register Address (old protocol */
 #define IXGBE_MSCA_PHY_ADDR_MASK     0x03E00000 /* PHY Address mask */
 #define IXGBE_MSCA_PHY_ADDR_SHIFT    21 /* PHY Address shift*/
 #define IXGBE_MSCA_OP_CODE_MASK      0x0C000000 /* OP CODE mask */
 #define IXGBE_MSCA_OP_CODE_SHIFT     26 /* OP CODE shift */
 #define IXGBE_MSCA_ADDR_CYCLE        0x00000000 /* OP CODE 00 (addr cycle) */
 #define IXGBE_MSCA_WRITE             0x04000000 /* OP CODE 01 (write) */
 #define IXGBE_MSCA_READ              0x0C000000 /* OP CODE 11 (read) */
 #define IXGBE_MSCA_READ_AUTOINC      0x08000000 /* OP CODE 10 (read, auto inc)*/
 #define IXGBE_MSCA_ST_CODE_MASK      0x30000000 /* ST Code mask */
 #define IXGBE_MSCA_ST_CODE_SHIFT     28 /* ST Code shift */
 #define IXGBE_MSCA_NEW_PROTOCOL      0x00000000 /* ST CODE 00 (new protocol) */
 #define IXGBE_MSCA_OLD_PROTOCOL      0x10000000 /* ST CODE 01 (old protocol) */
 #define IXGBE_MSCA_MDI_COMMAND       0x40000000 /* Initiate MDI command */
 #define IXGBE_MSCA_MDI_IN_PROG_EN    0x80000000 /* MDI in progress enable */
 /* MSRWD bit masks */
 #define IXGBE_MSRWD_WRITE_DATA_MASK     0x0000FFFF
 #define IXGBE_MSRWD_WRITE_DATA_SHIFT    0
 #define IXGBE_MSRWD_READ_DATA_MASK      0xFFFF0000
 #define IXGBE_MSRWD_READ_DATA_SHIFT     16
 /* Atlas registers */
 #define IXGBE_ATLAS_PDN_LPBK    0x24
 #define IXGBE_ATLAS_PDN_10G     0xB
 #define IXGBE_ATLAS_PDN_1G      0xC
 #define IXGBE_ATLAS_PDN_AN      0xD
 /* Atlas bit masks */
 #define IXGBE_ATLASCTL_WRITE_CMD        0x00010000
 #define IXGBE_ATLAS_PDN_TX_REG_EN       0x10
 #define IXGBE_ATLAS_PDN_TX_10G_QL_ALL   0xF0
 #define IXGBE_ATLAS_PDN_TX_1G_QL_ALL    0xF0
 #define IXGBE_ATLAS_PDN_TX_AN_QL_ALL    0xF0
 /* Omer bit masks */
 #define IXGBE_CORECTL_WRITE_CMD         0x00010000
 /* MDIO definitions */
 #define IXGBE_MDIO_COMMAND_TIMEOUT     100 /* PHY Timeout for 1 GB mode */
 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL      0x0    /* VS1 Control Reg */
 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS       0x1    /* VS1 Status Reg */
 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS  0x0008 /* 1 = Link Up */
 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0 - 10G, 1 - 1G */
 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED    0x0018
 #define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED     0x0010
 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR     0xC30A /* PHY_XS SDA/SCL Addr Reg */
 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA     0xC30B /* PHY_XS SDA/SCL Data Reg */
 #define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT     0xC30C /* PHY_XS SDA/SCL Status Reg */
 /* MII clause 22/28 definitions */
 #define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */
 #define IXGBE_MII_AUTONEG_XNP_TX_REG             0x17   /* 1G XNP Transmit */
 #define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX      0x4000 /* full duplex, bit:14*/
 #define IXGBE_MII_1GBASE_T_ADVERTISE             0x8000 /* full duplex, bit:15*/
 #define IXGBE_MII_AUTONEG_REG                    0x0
 #define IXGBE_PHY_REVISION_MASK        0xFFFFFFF0
 #define IXGBE_MAX_PHY_ADDR             32
 /* PHY IDs*/
 #define TN1010_PHY_ID    0x00A19410
 #define TNX_FW_REV       0xB
 #define X540_PHY_ID      0x01540200
 #define QT2022_PHY_ID    0x0043A400
 #define ATH_PHY_ID       0x03429050
 #define AQ_FW_REV        0x20
 /* PHY Types */
 #define IXGBE_M88E1145_E_PHY_ID  0x01410CD0
 /* Special PHY Init Routine */
 #define IXGBE_PHY_INIT_OFFSET_NL 0x002B
 #define IXGBE_PHY_INIT_END_NL    0xFFFF
 #define IXGBE_CONTROL_MASK_NL    0xF000
 #define IXGBE_DATA_MASK_NL       0x0FFF
 #define IXGBE_CONTROL_SHIFT_NL   12
 #define IXGBE_DELAY_NL           0
 #define IXGBE_DATA_NL            1
 #define IXGBE_CONTROL_NL         0x000F
 #define IXGBE_CONTROL_EOL_NL     0x0FFF
 #define IXGBE_CONTROL_SOL_NL     0x0000
 /* General purpose Interrupt Enable */
 #define IXGBE_SDP0_GPIEN         0x00000001 /* SDP0 */
 #define IXGBE_SDP1_GPIEN         0x00000002 /* SDP1 */
 #define IXGBE_SDP2_GPIEN         0x00000004 /* SDP2 */
 #define IXGBE_GPIE_MSIX_MODE     0x00000010 /* MSI-X mode */
 #define IXGBE_GPIE_OCD           0x00000020 /* Other Clear Disable */
 #define IXGBE_GPIE_EIMEN         0x00000040 /* Immediate Interrupt Enable */
 #define IXGBE_GPIE_EIAME         0x40000000
 #define IXGBE_GPIE_PBA_SUPPORT   0x80000000
 #define IXGBE_GPIE_RSC_DELAY_SHIFT 11
 #define IXGBE_GPIE_VTMODE_MASK   0x0000C000 /* VT Mode Mask */
 #define IXGBE_GPIE_VTMODE_16     0x00004000 /* 16 VFs 8 queues per VF */
 #define IXGBE_GPIE_VTMODE_32     0x00008000 /* 32 VFs 4 queues per VF */
 #define IXGBE_GPIE_VTMODE_64     0x0000C000 /* 64 VFs 2 queues per VF */
 /* Packet Buffer Initialization */
 #define IXGBE_TXPBSIZE_20KB     0x00005000 /* 20KB Packet Buffer */
 #define IXGBE_TXPBSIZE_40KB     0x0000A000 /* 40KB Packet Buffer */
 #define IXGBE_RXPBSIZE_48KB     0x0000C000 /* 48KB Packet Buffer */
 #define IXGBE_RXPBSIZE_64KB     0x00010000 /* 64KB Packet Buffer */
 #define IXGBE_RXPBSIZE_80KB     0x00014000 /* 80KB Packet Buffer */
 #define IXGBE_RXPBSIZE_128KB    0x00020000 /* 128KB Packet Buffer */
 #define IXGBE_RXPBSIZE_MAX      0x00080000 /* 512KB Packet Buffer*/
 #define IXGBE_TXPBSIZE_MAX      0x00028000 /* 160KB Packet Buffer*/
 #define IXGBE_TXPKT_SIZE_MAX    0xA        /* Max Tx Packet size  */
 #define IXGBE_MAX_PB		8
 /* Packet buffer allocation strategies */
 enum {
 	PBA_STRATEGY_EQUAL	= 0,	/* Distribute PB space equally */
 #define PBA_STRATEGY_EQUAL	PBA_STRATEGY_EQUAL
 	PBA_STRATEGY_WEIGHTED	= 1,	/* Weight front half of TCs */
 #define PBA_STRATEGY_WEIGHTED	PBA_STRATEGY_WEIGHTED
 };
 /* Transmit Flow Control status */
 #define IXGBE_TFCS_TXOFF         0x00000001
 #define IXGBE_TFCS_TXOFF0        0x00000100
 #define IXGBE_TFCS_TXOFF1        0x00000200
 #define IXGBE_TFCS_TXOFF2        0x00000400
 #define IXGBE_TFCS_TXOFF3        0x00000800
 #define IXGBE_TFCS_TXOFF4        0x00001000
 #define IXGBE_TFCS_TXOFF5        0x00002000
 #define IXGBE_TFCS_TXOFF6        0x00004000
 #define IXGBE_TFCS_TXOFF7        0x00008000
 /* TCP Timer */
 #define IXGBE_TCPTIMER_KS            0x00000100
 #define IXGBE_TCPTIMER_COUNT_ENABLE  0x00000200
 #define IXGBE_TCPTIMER_COUNT_FINISH  0x00000400
 #define IXGBE_TCPTIMER_LOOP          0x00000800
 #define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF
 /* HLREG0 Bit Masks */
 #define IXGBE_HLREG0_TXCRCEN      0x00000001   /* bit  0 */
 #define IXGBE_HLREG0_RXCRCSTRP    0x00000002   /* bit  1 */
 #define IXGBE_HLREG0_JUMBOEN      0x00000004   /* bit  2 */
 #define IXGBE_HLREG0_TXPADEN      0x00000400   /* bit 10 */
 #define IXGBE_HLREG0_TXPAUSEEN    0x00001000   /* bit 12 */
 #define IXGBE_HLREG0_RXPAUSEEN    0x00004000   /* bit 14 */
 #define IXGBE_HLREG0_LPBK         0x00008000   /* bit 15 */
 #define IXGBE_HLREG0_MDCSPD       0x00010000   /* bit 16 */
 #define IXGBE_HLREG0_CONTMDC      0x00020000   /* bit 17 */
 #define IXGBE_HLREG0_CTRLFLTR     0x00040000   /* bit 18 */
 #define IXGBE_HLREG0_PREPEND      0x00F00000   /* bits 20-23 */
 #define IXGBE_HLREG0_PRIPAUSEEN   0x01000000   /* bit 24 */
 #define IXGBE_HLREG0_RXPAUSERECDA 0x06000000   /* bits 25-26 */
 #define IXGBE_HLREG0_RXLNGTHERREN 0x08000000   /* bit 27 */
 #define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000   /* bit 28 */
 /* VMD_CTL bitmasks */
 #define IXGBE_VMD_CTL_VMDQ_EN     0x00000001
 #define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002
 /* VT_CTL bitmasks */
 #define IXGBE_VT_CTL_DIS_DEFPL  0x20000000 /* disable default pool */
 #define IXGBE_VT_CTL_REPLEN     0x40000000 /* replication enabled */
 #define IXGBE_VT_CTL_VT_ENABLE  0x00000001  /* Enable VT Mode */
 #define IXGBE_VT_CTL_POOL_SHIFT 7
 #define IXGBE_VT_CTL_POOL_MASK  (0x3F << IXGBE_VT_CTL_POOL_SHIFT)
 /* VMOLR bitmasks */
 #define IXGBE_VMOLR_AUPE        0x01000000 /* accept untagged packets */
 #define IXGBE_VMOLR_ROMPE       0x02000000 /* accept packets in MTA tbl */
 #define IXGBE_VMOLR_ROPE        0x04000000 /* accept packets in UC tbl */
 #define IXGBE_VMOLR_BAM         0x08000000 /* accept broadcast packets */
 #define IXGBE_VMOLR_MPE         0x10000000 /* multicast promiscuous */
 /* VFRE bitmask */
 #define IXGBE_VFRE_ENABLE_ALL   0xFFFFFFFF
 #define IXGBE_VF_INIT_TIMEOUT   200 /* Number of retries to clear RSTI */
 /* RDHMPN and TDHMPN bitmasks */
 #define IXGBE_RDHMPN_RDICADDR       0x007FF800
 #define IXGBE_RDHMPN_RDICRDREQ      0x00800000
 #define IXGBE_RDHMPN_RDICADDR_SHIFT 11
 #define IXGBE_TDHMPN_TDICADDR       0x003FF800
 #define IXGBE_TDHMPN_TDICRDREQ      0x00800000
 #define IXGBE_TDHMPN_TDICADDR_SHIFT 11
 #define IXGBE_RDMAM_MEM_SEL_SHIFT   13
 #define IXGBE_RDMAM_DWORD_SHIFT     9
 #define IXGBE_RDMAM_DESC_COMP_FIFO  1
 #define IXGBE_RDMAM_DFC_CMD_FIFO    2
 #define IXGBE_RDMAM_TCN_STATUS_RAM  4
 #define IXGBE_RDMAM_WB_COLL_FIFO    5
 #define IXGBE_RDMAM_QSC_CNT_RAM     6
 #define IXGBE_RDMAM_QSC_QUEUE_CNT   8
 #define IXGBE_RDMAM_QSC_QUEUE_RAM   0xA
 #define IXGBE_RDMAM_DESC_COM_FIFO_RANGE     135
 #define IXGBE_RDMAM_DESC_COM_FIFO_COUNT     4
 #define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE      48
 #define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT      7
 #define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE    256
 #define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT    9
 #define IXGBE_RDMAM_WB_COLL_FIFO_RANGE      8
 #define IXGBE_RDMAM_WB_COLL_FIFO_COUNT      4
 #define IXGBE_RDMAM_QSC_CNT_RAM_RANGE       64
 #define IXGBE_RDMAM_QSC_CNT_RAM_COUNT       4
 #define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE     32
 #define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT     4
 #define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE     128
 #define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT     8
 #define IXGBE_TXDESCIC_READY        0x80000000
 /* Receive Checksum Control */
 #define IXGBE_RXCSUM_IPPCSE     0x00001000   /* IP payload checksum enable */
 #define IXGBE_RXCSUM_PCSD       0x00002000   /* packet checksum disabled */
 /* FCRTL Bit Masks */
 #define IXGBE_FCRTL_XONE        0x80000000  /* XON enable */
 #define IXGBE_FCRTH_FCEN        0x80000000  /* Packet buffer fc enable */
 /* PAP bit masks*/
 #define IXGBE_PAP_TXPAUSECNT_MASK   0x0000FFFF /* Pause counter mask */
 /* RMCS Bit Masks */
 #define IXGBE_RMCS_RRM          0x00000002 /* Receive Recycle Mode enable */
 /* Receive Arbitration Control: 0 Round Robin, 1 DFP */
 #define IXGBE_RMCS_RAC          0x00000004
 #define IXGBE_RMCS_DFP          IXGBE_RMCS_RAC /* Deficit Fixed Priority ena */
 #define IXGBE_RMCS_TFCE_802_3X         0x00000008 /* Tx Priority FC ena */
 #define IXGBE_RMCS_TFCE_PRIORITY       0x00000010 /* Tx Priority FC ena */
 #define IXGBE_RMCS_ARBDIS       0x00000040 /* Arbitration disable bit */
 /* FCCFG Bit Masks */
 #define IXGBE_FCCFG_TFCE_802_3X         0x00000008 /* Tx link FC enable */
 #define IXGBE_FCCFG_TFCE_PRIORITY       0x00000010 /* Tx priority FC enable */
 /* Interrupt register bitmasks */
 /* Extended Interrupt Cause Read */
 #define IXGBE_EICR_RTX_QUEUE    0x0000FFFF /* RTx Queue Interrupt */
 #define IXGBE_EICR_FLOW_DIR     0x00010000 /* FDir Exception */
 #define IXGBE_EICR_RX_MISS      0x00020000 /* Packet Buffer Overrun */
 #define IXGBE_EICR_PCI          0x00040000 /* PCI Exception */
 #define IXGBE_EICR_MAILBOX      0x00080000 /* VF to PF Mailbox Interrupt */
 #define IXGBE_EICR_LSC          0x00100000 /* Link Status Change */
 #define IXGBE_EICR_LINKSEC      0x00200000 /* PN Threshold */
 #define IXGBE_EICR_MNG          0x00400000 /* Manageability Event Interrupt */
 #define IXGBE_EICR_TS           0x00800000 /* Thermal Sensor Event */
 #define IXGBE_EICR_TIMESYNC     0x01000000 /* Timesync Event */
 #define IXGBE_EICR_GPI_SDP0     0x01000000 /* Gen Purpose Interrupt on SDP0 */
 #define IXGBE_EICR_GPI_SDP1     0x02000000 /* Gen Purpose Interrupt on SDP1 */
 #define IXGBE_EICR_GPI_SDP2     0x04000000 /* Gen Purpose Interrupt on SDP2 */
 #define IXGBE_EICR_ECC          0x10000000 /* ECC Error */
 #define IXGBE_EICR_PBUR         0x10000000 /* Packet Buffer Handler Error */
 #define IXGBE_EICR_DHER         0x20000000 /* Descriptor Handler Error */
 #define IXGBE_EICR_TCP_TIMER    0x40000000 /* TCP Timer */
 #define IXGBE_EICR_OTHER        0x80000000 /* Interrupt Cause Active */
 /* Extended Interrupt Cause Set */
 #define IXGBE_EICS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
 #define IXGBE_EICS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
 #define IXGBE_EICS_RX_MISS      IXGBE_EICR_RX_MISS   /* Pkt Buffer Overrun */
 #define IXGBE_EICS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
 #define IXGBE_EICS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
 #define IXGBE_EICS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
 #define IXGBE_EICS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
 #define IXGBE_EICS_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
 #define IXGBE_EICS_GPI_SDP0     IXGBE_EICR_GPI_SDP0  /* SDP0 Gen Purpose Int */
 #define IXGBE_EICS_GPI_SDP1     IXGBE_EICR_GPI_SDP1  /* SDP1 Gen Purpose Int */
 #define IXGBE_EICS_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
 #define IXGBE_EICS_ECC          IXGBE_EICR_ECC       /* ECC Error */
 #define IXGBE_EICS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
 #define IXGBE_EICS_DHER         IXGBE_EICR_DHER      /* Desc Handler Error */
 #define IXGBE_EICS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
 #define IXGBE_EICS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
 /* Extended Interrupt Mask Set */
 #define IXGBE_EIMS_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
 #define IXGBE_EIMS_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
 #define IXGBE_EIMS_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
 #define IXGBE_EIMS_PCI          IXGBE_EICR_PCI       /* PCI Exception */
 #define IXGBE_EIMS_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
 #define IXGBE_EIMS_LSC          IXGBE_EICR_LSC       /* Link Status Change */
 #define IXGBE_EIMS_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
 #define IXGBE_EIMS_TS           IXGBE_EICR_TS        /* Thermel Sensor Event */
 #define IXGBE_EIMS_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
 #define IXGBE_EIMS_GPI_SDP0     IXGBE_EICR_GPI_SDP0  /* SDP0 Gen Purpose Int */
 #define IXGBE_EIMS_GPI_SDP1     IXGBE_EICR_GPI_SDP1  /* SDP1 Gen Purpose Int */
 #define IXGBE_EIMS_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
 #define IXGBE_EIMS_ECC          IXGBE_EICR_ECC       /* ECC Error */
 #define IXGBE_EIMS_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
 #define IXGBE_EIMS_DHER         IXGBE_EICR_DHER      /* Descr Handler Error */
 #define IXGBE_EIMS_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
 #define IXGBE_EIMS_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
 /* Extended Interrupt Mask Clear */
 #define IXGBE_EIMC_RTX_QUEUE    IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */
 #define IXGBE_EIMC_FLOW_DIR     IXGBE_EICR_FLOW_DIR  /* FDir Exception */
 #define IXGBE_EIMC_RX_MISS      IXGBE_EICR_RX_MISS   /* Packet Buffer Overrun */
 #define IXGBE_EIMC_PCI          IXGBE_EICR_PCI       /* PCI Exception */
 #define IXGBE_EIMC_MAILBOX      IXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */
 #define IXGBE_EIMC_LSC          IXGBE_EICR_LSC       /* Link Status Change */
 #define IXGBE_EIMC_MNG          IXGBE_EICR_MNG       /* MNG Event Interrupt */
 #define IXGBE_EIMC_TIMESYNC     IXGBE_EICR_TIMESYNC  /* Timesync Event */
 #define IXGBE_EIMC_GPI_SDP0     IXGBE_EICR_GPI_SDP0  /* SDP0 Gen Purpose Int */
 #define IXGBE_EIMC_GPI_SDP1     IXGBE_EICR_GPI_SDP1  /* SDP1 Gen Purpose Int */
 #define IXGBE_EIMC_GPI_SDP2     IXGBE_EICR_GPI_SDP2  /* SDP2 Gen Purpose Int */
 #define IXGBE_EIMC_ECC          IXGBE_EICR_ECC       /* ECC Error */
 #define IXGBE_EIMC_PBUR         IXGBE_EICR_PBUR      /* Pkt Buf Handler Err */
 #define IXGBE_EIMC_DHER         IXGBE_EICR_DHER      /* Desc Handler Err */
 #define IXGBE_EIMC_TCP_TIMER    IXGBE_EICR_TCP_TIMER /* TCP Timer */
 #define IXGBE_EIMC_OTHER        IXGBE_EICR_OTHER     /* INT Cause Active */
 #define IXGBE_EIMS_ENABLE_MASK ( \
                                 IXGBE_EIMS_RTX_QUEUE       | \
                                 IXGBE_EIMS_LSC             | \
                                 IXGBE_EIMS_TCP_TIMER       | \
                                 IXGBE_EIMS_OTHER)
 /* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */
 #define IXGBE_IMIR_PORT_IM_EN     0x00010000  /* TCP port enable */
 #define IXGBE_IMIR_PORT_BP        0x00020000  /* TCP port check bypass */
 #define IXGBE_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
 #define IXGBE_IMIREXT_CTRL_URG    0x00002000  /* Check URG bit in header */
 #define IXGBE_IMIREXT_CTRL_ACK    0x00004000  /* Check ACK bit in header */
 #define IXGBE_IMIREXT_CTRL_PSH    0x00008000  /* Check PSH bit in header */
 #define IXGBE_IMIREXT_CTRL_RST    0x00010000  /* Check RST bit in header */
 #define IXGBE_IMIREXT_CTRL_SYN    0x00020000  /* Check SYN bit in header */
 #define IXGBE_IMIREXT_CTRL_FIN    0x00040000  /* Check FIN bit in header */
 #define IXGBE_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of control bits */
 #define IXGBE_IMIR_SIZE_BP_82599  0x00001000 /* Packet size bypass */
 #define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */
 #define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */
 #define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */
 #define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */
 #define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */
 #define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */
 #define IXGBE_IMIR_CTRL_BP_82599  0x00080000 /* Bypass check of control bits */
 #define IXGBE_IMIR_LLI_EN_82599   0x00100000 /* Enables low latency Int */
 #define IXGBE_IMIR_RX_QUEUE_MASK_82599  0x0000007F /* Rx Queue Mask */
 #define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */
 #define IXGBE_IMIRVP_PRIORITY_MASK      0x00000007 /* VLAN priority mask */
 #define IXGBE_IMIRVP_PRIORITY_EN        0x00000008 /* VLAN priority enable */
 #define IXGBE_MAX_FTQF_FILTERS          128
 #define IXGBE_FTQF_PROTOCOL_MASK        0x00000003
 #define IXGBE_FTQF_PROTOCOL_TCP         0x00000000
 #define IXGBE_FTQF_PROTOCOL_UDP         0x00000001
 #define IXGBE_FTQF_PROTOCOL_SCTP        2
 #define IXGBE_FTQF_PRIORITY_MASK        0x00000007
 #define IXGBE_FTQF_PRIORITY_SHIFT       2
 #define IXGBE_FTQF_POOL_MASK            0x0000003F
 #define IXGBE_FTQF_POOL_SHIFT           8
 #define IXGBE_FTQF_5TUPLE_MASK_MASK     0x0000001F
 #define IXGBE_FTQF_5TUPLE_MASK_SHIFT    25
 #define IXGBE_FTQF_SOURCE_ADDR_MASK     0x1E
 #define IXGBE_FTQF_DEST_ADDR_MASK       0x1D
 #define IXGBE_FTQF_SOURCE_PORT_MASK     0x1B
 #define IXGBE_FTQF_DEST_PORT_MASK       0x17
 #define IXGBE_FTQF_PROTOCOL_COMP_MASK   0x0F
 #define IXGBE_FTQF_POOL_MASK_EN         0x40000000
 #define IXGBE_FTQF_QUEUE_ENABLE         0x80000000
 /* Interrupt clear mask */
 #define IXGBE_IRQ_CLEAR_MASK    0xFFFFFFFF
 /* Interrupt Vector Allocation Registers */
 #define IXGBE_IVAR_REG_NUM      25
 #define IXGBE_IVAR_REG_NUM_82599       64
 #define IXGBE_IVAR_TXRX_ENTRY   96
 #define IXGBE_IVAR_RX_ENTRY     64
 #define IXGBE_IVAR_RX_QUEUE(_i)    (0 + (_i))
 #define IXGBE_IVAR_TX_QUEUE(_i)    (64 + (_i))
 #define IXGBE_IVAR_TX_ENTRY     32
 #define IXGBE_IVAR_TCP_TIMER_INDEX       96 /* 0 based index */
 #define IXGBE_IVAR_OTHER_CAUSES_INDEX    97 /* 0 based index */
 #define IXGBE_MSIX_VECTOR(_i)   (0 + (_i))
 #define IXGBE_IVAR_ALLOC_VAL    0x80 /* Interrupt Allocation valid */
 /* ETYPE Queue Filter/Select Bit Masks */
 #define IXGBE_MAX_ETQF_FILTERS  8
 #define IXGBE_ETQF_FCOE         0x08000000 /* bit 27 */
 #define IXGBE_ETQF_BCN          0x10000000 /* bit 28 */
 #define IXGBE_ETQF_1588         0x40000000 /* bit 30 */
 #define IXGBE_ETQF_FILTER_EN    0x80000000 /* bit 31 */
 #define IXGBE_ETQF_POOL_ENABLE   (1 << 26) /* bit 26 */
 #define IXGBE_ETQF_POOL_SHIFT		20
 #define IXGBE_ETQS_RX_QUEUE     0x007F0000 /* bits 22:16 */
 #define IXGBE_ETQS_RX_QUEUE_SHIFT       16
 #define IXGBE_ETQS_LLI          0x20000000 /* bit 29 */
 #define IXGBE_ETQS_QUEUE_EN     0x80000000 /* bit 31 */
 /*
  * ETQF filter list: one static filter per filter consumer. This is
  *                   to avoid filter collisions later. Add new filters
  *                   here!!
  *
  * Current filters:
  *    EAPOL 802.1x (0x888e): Filter 0
  *    FCoE (0x8906):         Filter 2
  *    1588 (0x88f7):         Filter 3
  *    FIP  (0x8914):         Filter 4
  */
 #define IXGBE_ETQF_FILTER_EAPOL          0
 #define IXGBE_ETQF_FILTER_FCOE           2
 #define IXGBE_ETQF_FILTER_1588           3
 #define IXGBE_ETQF_FILTER_FIP            4
 /* VLAN Control Bit Masks */
 #define IXGBE_VLNCTRL_VET       0x0000FFFF  /* bits 0-15 */
 #define IXGBE_VLNCTRL_CFI       0x10000000  /* bit 28 */
 #define IXGBE_VLNCTRL_CFIEN     0x20000000  /* bit 29 */
 #define IXGBE_VLNCTRL_VFE       0x40000000  /* bit 30 */
 #define IXGBE_VLNCTRL_VME       0x80000000  /* bit 31 */
 /* VLAN pool filtering masks */
 #define IXGBE_VLVF_VIEN         0x80000000  /* filter is valid */
 #define IXGBE_VLVF_ENTRIES      64
 #define IXGBE_VLVF_VLANID_MASK  0x00000FFF
 /* Per VF Port VLAN insertion rules */
 #define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */
 #define IXGBE_VMVIR_VLANA_NEVER   0x80000000 /* Never insert VLAN tag */
 #define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100  /* 802.1q protocol */
 /* STATUS Bit Masks */
 #define IXGBE_STATUS_LAN_ID         0x0000000C /* LAN ID */
 #define IXGBE_STATUS_LAN_ID_SHIFT   2          /* LAN ID Shift*/
 #define IXGBE_STATUS_GIO            0x00080000 /* GIO Master Enable Status */
 #define IXGBE_STATUS_LAN_ID_0   0x00000000 /* LAN ID 0 */
 #define IXGBE_STATUS_LAN_ID_1   0x00000004 /* LAN ID 1 */
 /* ESDP Bit Masks */
 #define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */
 #define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */
 #define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */
 #define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */
 #define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */
 #define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */
 #define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */
 #define IXGBE_ESDP_SDP0_DIR     0x00000100 /* SDP0 IO direction */
 #define IXGBE_ESDP_SDP4_DIR     0x00000004 /* SDP4 IO direction */
 #define IXGBE_ESDP_SDP5_DIR     0x00002000 /* SDP5 IO direction */
 #define IXGBE_ESDP_SDP0_NATIVE  0x00010000 /* SDP0 Native Function */
 /* LEDCTL Bit Masks */
 #define IXGBE_LED_IVRT_BASE      0x00000040
 #define IXGBE_LED_BLINK_BASE     0x00000080
 #define IXGBE_LED_MODE_MASK_BASE 0x0000000F
 #define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i)))
 #define IXGBE_LED_MODE_SHIFT(_i) (8 * (_i))
 #define IXGBE_LED_IVRT(_i)       IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i)
 #define IXGBE_LED_BLINK(_i)      IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i)
 #define IXGBE_LED_MODE_MASK(_i)  IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i)
 /* LED modes */
 #define IXGBE_LED_LINK_UP       0x0
 #define IXGBE_LED_LINK_10G      0x1
 #define IXGBE_LED_MAC           0x2
 #define IXGBE_LED_FILTER        0x3
 #define IXGBE_LED_LINK_ACTIVE   0x4
 #define IXGBE_LED_LINK_1G       0x5
 #define IXGBE_LED_ON            0xE
 #define IXGBE_LED_OFF           0xF
 /* AUTOC Bit Masks */
 #define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000
 #define IXGBE_AUTOC_KX4_SUPP    0x80000000
 #define IXGBE_AUTOC_KX_SUPP     0x40000000
 #define IXGBE_AUTOC_PAUSE       0x30000000
 #define IXGBE_AUTOC_ASM_PAUSE   0x20000000
 #define IXGBE_AUTOC_SYM_PAUSE   0x10000000
 #define IXGBE_AUTOC_RF          0x08000000
 #define IXGBE_AUTOC_PD_TMR      0x06000000
 #define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000
 #define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000
 #define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000
 #define IXGBE_AUTOC_FECA        0x00040000
 #define IXGBE_AUTOC_FECR        0x00020000
 #define IXGBE_AUTOC_KR_SUPP     0x00010000
 #define IXGBE_AUTOC_AN_RESTART  0x00001000
 #define IXGBE_AUTOC_FLU         0x00000001
 #define IXGBE_AUTOC_LMS_SHIFT   13
 #define IXGBE_AUTOC_LMS_10G_SERIAL      (0x3 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_KX4_KX_KR       (0x4 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_SGMII_1G_100M   (0x5 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_MASK            (0x7 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_1G_LINK_NO_AN   (0x0 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_10G_LINK_NO_AN  (0x1 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_1G_AN           (0x2 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_KX4_AN          (0x4 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_KX4_AN_1G_AN    (0x6 << IXGBE_AUTOC_LMS_SHIFT)
 #define IXGBE_AUTOC_LMS_ATTACH_TYPE     (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC_1G_PMA_PMD_MASK    0x00000200
 #define IXGBE_AUTOC_1G_PMA_PMD_SHIFT   9
 #define IXGBE_AUTOC_10G_PMA_PMD_MASK   0x00000180
 #define IXGBE_AUTOC_10G_PMA_PMD_SHIFT  7
 #define IXGBE_AUTOC_10G_XAUI   (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC_10G_KX4    (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC_10G_CX4    (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC_1G_BX      (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC_1G_KX      (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC_1G_SFI     (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC_1G_KX_BX   (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC2_UPPER_MASK  0xFFFF0000
 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK  0x00030000
 #define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16
 #define IXGBE_AUTOC2_10G_KR  (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT)
 #define IXGBE_AUTOC2_LINK_DISABLE_MASK        0x70000000
 #define IXGBE_MACC_FLU       0x00000001
 #define IXGBE_MACC_FSV_10G   0x00030000
 #define IXGBE_MACC_FS        0x00040000
 #define IXGBE_MAC_RX2TX_LPBK 0x00000002
 /* LINKS Bit Masks */
 #define IXGBE_LINKS_KX_AN_COMP  0x80000000
 #define IXGBE_LINKS_UP          0x40000000
 #define IXGBE_LINKS_SPEED       0x20000000
 #define IXGBE_LINKS_MODE        0x18000000
 #define IXGBE_LINKS_RX_MODE     0x06000000
 #define IXGBE_LINKS_TX_MODE     0x01800000
 #define IXGBE_LINKS_XGXS_EN     0x00400000
 #define IXGBE_LINKS_SGMII_EN    0x02000000
 #define IXGBE_LINKS_PCS_1G_EN   0x00200000
 #define IXGBE_LINKS_1G_AN_EN    0x00100000
 #define IXGBE_LINKS_KX_AN_IDLE  0x00080000
 #define IXGBE_LINKS_1G_SYNC     0x00040000
 #define IXGBE_LINKS_10G_ALIGN   0x00020000
 #define IXGBE_LINKS_10G_LANE_SYNC 0x00017000
 #define IXGBE_LINKS_TL_FAULT    0x00001000
 #define IXGBE_LINKS_SIGNAL      0x00000F00
 #define IXGBE_LINKS_SPEED_82599     0x30000000
 #define IXGBE_LINKS_SPEED_10G_82599 0x30000000
 #define IXGBE_LINKS_SPEED_1G_82599  0x20000000
 #define IXGBE_LINKS_SPEED_100_82599 0x10000000
 #define IXGBE_LINK_UP_TIME      90 /* 9.0 Seconds */
 #define IXGBE_AUTO_NEG_TIME     45 /* 4.5 Seconds */
 #define IXGBE_LINKS2_AN_SUPPORTED   0x00000040
 /* PCS1GLSTA Bit Masks */
 #define IXGBE_PCS1GLSTA_LINK_OK         1
 #define IXGBE_PCS1GLSTA_SYNK_OK         0x10
 #define IXGBE_PCS1GLSTA_AN_COMPLETE     0x10000
 #define IXGBE_PCS1GLSTA_AN_PAGE_RX      0x20000
 #define IXGBE_PCS1GLSTA_AN_TIMED_OUT    0x40000
 #define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000
 #define IXGBE_PCS1GLSTA_AN_ERROR_RWS    0x100000
 #define IXGBE_PCS1GANA_SYM_PAUSE        0x80
 #define IXGBE_PCS1GANA_ASM_PAUSE        0x100
 /* PCS1GLCTL Bit Masks */
 #define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN  0x00040000 /* PCS 1G autoneg to en */
 #define IXGBE_PCS1GLCTL_FLV_LINK_UP     1
 #define IXGBE_PCS1GLCTL_FORCE_LINK      0x20
 #define IXGBE_PCS1GLCTL_LOW_LINK_LATCH  0x40
 #define IXGBE_PCS1GLCTL_AN_ENABLE       0x10000
 #define IXGBE_PCS1GLCTL_AN_RESTART      0x20000
 /* ANLP1 Bit Masks */
 #define IXGBE_ANLP1_PAUSE               0x0C00
 #define IXGBE_ANLP1_SYM_PAUSE           0x0400
 #define IXGBE_ANLP1_ASM_PAUSE           0x0800
 #define IXGBE_ANLP1_AN_STATE_MASK       0x000f0000
 /* SW Semaphore Register bitmasks */
 #define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */
 #define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */
 #define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */
 #define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */
 /* SW_FW_SYNC/GSSR definitions */
 #define IXGBE_GSSR_EEP_SM     0x0001
 #define IXGBE_GSSR_PHY0_SM    0x0002
 #define IXGBE_GSSR_PHY1_SM    0x0004
 #define IXGBE_GSSR_MAC_CSR_SM 0x0008
 #define IXGBE_GSSR_FLASH_SM   0x0010
 #define IXGBE_GSSR_SW_MNG_SM  0x0400
 /* FW Status register bitmask */
 #define IXGBE_FWSTS_FWRI    0x00000200 /* Firmware Reset Indication */
 /* EEC Register */
 #define IXGBE_EEC_SK        0x00000001 /* EEPROM Clock */
 #define IXGBE_EEC_CS        0x00000002 /* EEPROM Chip Select */
 #define IXGBE_EEC_DI        0x00000004 /* EEPROM Data In */
 #define IXGBE_EEC_DO        0x00000008 /* EEPROM Data Out */
 #define IXGBE_EEC_FWE_MASK  0x00000030 /* FLASH Write Enable */
 #define IXGBE_EEC_FWE_DIS   0x00000010 /* Disable FLASH writes */
 #define IXGBE_EEC_FWE_EN    0x00000020 /* Enable FLASH writes */
 #define IXGBE_EEC_FWE_SHIFT 4
 #define IXGBE_EEC_REQ       0x00000040 /* EEPROM Access Request */
 #define IXGBE_EEC_GNT       0x00000080 /* EEPROM Access Grant */
 #define IXGBE_EEC_PRES      0x00000100 /* EEPROM Present */
 #define IXGBE_EEC_ARD       0x00000200 /* EEPROM Auto Read Done */
 #define IXGBE_EEC_FLUP      0x00800000 /* Flash update command */
 #define IXGBE_EEC_SEC1VAL   0x02000000 /* Sector 1 Valid */
 #define IXGBE_EEC_FLUDONE   0x04000000 /* Flash update done */
 /* EEPROM Addressing bits based on type (0-small, 1-large) */
 #define IXGBE_EEC_ADDR_SIZE 0x00000400
 #define IXGBE_EEC_SIZE      0x00007800 /* EEPROM Size */
 #define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */
 #define IXGBE_EEC_SIZE_SHIFT          11
 #define IXGBE_EEPROM_WORD_SIZE_SHIFT  6
 #define IXGBE_EEPROM_OPCODE_BITS      8
 /* Part Number String Length */
 #define IXGBE_PBANUM_LENGTH 11
 /* Checksum and EEPROM pointers */
 #define IXGBE_PBANUM_PTR_GUARD  0xFAFA
 #define IXGBE_EEPROM_CHECKSUM   0x3F
 #define IXGBE_EEPROM_SUM        0xBABA
 #define IXGBE_PCIE_ANALOG_PTR   0x03
 #define IXGBE_ATLAS0_CONFIG_PTR 0x04
 #define IXGBE_PHY_PTR           0x04
 #define IXGBE_ATLAS1_CONFIG_PTR 0x05
 #define IXGBE_OPTION_ROM_PTR    0x05
 #define IXGBE_PCIE_GENERAL_PTR  0x06
 #define IXGBE_PCIE_CONFIG0_PTR  0x07
 #define IXGBE_PCIE_CONFIG1_PTR  0x08
 #define IXGBE_CORE0_PTR         0x09
 #define IXGBE_CORE1_PTR         0x0A
 #define IXGBE_MAC0_PTR          0x0B
 #define IXGBE_MAC1_PTR          0x0C
 #define IXGBE_CSR0_CONFIG_PTR   0x0D
 #define IXGBE_CSR1_CONFIG_PTR   0x0E
 #define IXGBE_FW_PTR            0x0F
 #define IXGBE_PBANUM0_PTR       0x15
 #define IXGBE_PBANUM1_PTR       0x16
 #define IXGBE_FREE_SPACE_PTR    0X3E
 /* External Thermal Sensor Config */
 #define IXGBE_ETS_CFG                   0x26
 #define IXGBE_ETS_LTHRES_DELTA_MASK     0x07C0
 #define IXGBE_ETS_LTHRES_DELTA_SHIFT    6
 #define IXGBE_ETS_TYPE_MASK             0x0038
 #define IXGBE_ETS_TYPE_SHIFT            3
 #define IXGBE_ETS_TYPE_EMC              0x000
 #define IXGBE_ETS_TYPE_EMC_SHIFTED      0x000
 #define IXGBE_ETS_NUM_SENSORS_MASK      0x0007
 #define IXGBE_ETS_DATA_LOC_MASK         0x3C00
 #define IXGBE_ETS_DATA_LOC_SHIFT        10
 #define IXGBE_ETS_DATA_INDEX_MASK       0x0300
 #define IXGBE_ETS_DATA_INDEX_SHIFT      8
 #define IXGBE_ETS_DATA_HTHRESH_MASK     0x00FF
 #define IXGBE_SAN_MAC_ADDR_PTR  0x28
 #define IXGBE_DEVICE_CAPS       0x2C
 #define IXGBE_SERIAL_NUMBER_MAC_ADDR 0x11
 #define IXGBE_PCIE_MSIX_82599_CAPS  0x72
 #define IXGBE_MAX_MSIX_VECTORS_82599	0x40
 #define IXGBE_PCIE_MSIX_82598_CAPS  0x62
 #define IXGBE_MAX_MSIX_VECTORS_82598	0x13
 /* MSI-X capability fields masks */
 #define IXGBE_PCIE_MSIX_TBL_SZ_MASK     0x7FF
 /* Legacy EEPROM word offsets */
 #define IXGBE_ISCSI_BOOT_CAPS           0x0033
 #define IXGBE_ISCSI_SETUP_PORT_0        0x0030
 #define IXGBE_ISCSI_SETUP_PORT_1        0x0034
 /* EEPROM Commands - SPI */
 #define IXGBE_EEPROM_MAX_RETRY_SPI      5000 /* Max wait 5ms for RDY signal */
 #define IXGBE_EEPROM_STATUS_RDY_SPI     0x01
 #define IXGBE_EEPROM_READ_OPCODE_SPI    0x03  /* EEPROM read opcode */
 #define IXGBE_EEPROM_WRITE_OPCODE_SPI   0x02  /* EEPROM write opcode */
 #define IXGBE_EEPROM_A8_OPCODE_SPI      0x08  /* opcode bit-3 = addr bit-8 */
 #define IXGBE_EEPROM_WREN_OPCODE_SPI    0x06  /* EEPROM set Write Ena latch */
 /* EEPROM reset Write Enable latch */
 #define IXGBE_EEPROM_WRDI_OPCODE_SPI    0x04
 #define IXGBE_EEPROM_RDSR_OPCODE_SPI    0x05  /* EEPROM read Status reg */
 #define IXGBE_EEPROM_WRSR_OPCODE_SPI    0x01  /* EEPROM write Status reg */
 #define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20  /* EEPROM ERASE 4KB */
 #define IXGBE_EEPROM_ERASE64K_OPCODE_SPI  0xD8  /* EEPROM ERASE 64KB */
 #define IXGBE_EEPROM_ERASE256_OPCODE_SPI  0xDB  /* EEPROM ERASE 256B */
 /* EEPROM Read Register */
 #define IXGBE_EEPROM_RW_REG_DATA   16 /* data offset in EEPROM read reg */
 #define IXGBE_EEPROM_RW_REG_DONE   2  /* Offset to READ done bit */
 #define IXGBE_EEPROM_RW_REG_START  1  /* First bit to start operation */
 #define IXGBE_EEPROM_RW_ADDR_SHIFT 2  /* Shift to the address bits */
 #define IXGBE_NVM_POLL_WRITE       1  /* Flag for polling for write complete */
 #define IXGBE_NVM_POLL_READ        0  /* Flag for polling for read complete */
 #define IXGBE_EEPROM_PAGE_SIZE_MAX       128
 #define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 512 /* EEPROM words # read in burst */
 #define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* EEPROM words # wr in burst */
 #ifndef IXGBE_EEPROM_GRANT_ATTEMPTS
 #define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
 #endif
 #ifndef IXGBE_EERD_EEWR_ATTEMPTS
 /* Number of 5 microseconds we wait for EERD read and
  * EERW write to complete */
 #define IXGBE_EERD_EEWR_ATTEMPTS 100000
 #endif
 #ifndef IXGBE_FLUDONE_ATTEMPTS
 /* # attempts we wait for flush update to complete */
 #define IXGBE_FLUDONE_ATTEMPTS 20000
 #endif
 #define IXGBE_PCIE_CTRL2                 0x5   /* PCIe Control 2 Offset */
 #define IXGBE_PCIE_CTRL2_DUMMY_ENABLE    0x8   /* Dummy Function Enable */
 #define IXGBE_PCIE_CTRL2_LAN_DISABLE     0x2   /* LAN PCI Disable */
 #define IXGBE_PCIE_CTRL2_DISABLE_SELECT  0x1   /* LAN Disable Select */
 #define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET  0x0
 #define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET  0x3
 #define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP  0x1
 #define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS  0x2
 #define IXGBE_FW_LESM_PARAMETERS_PTR     0x2
 #define IXGBE_FW_LESM_STATE_1            0x1
 #define IXGBE_FW_LESM_STATE_ENABLED      0x8000 /* LESM Enable bit */
 #define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR   0x4
 #define IXGBE_FW_PATCH_VERSION_4         0x7
 #define IXGBE_FCOE_IBA_CAPS_BLK_PTR         0x33 /* iSCSI/FCOE block */
 #define IXGBE_FCOE_IBA_CAPS_FCOE            0x20 /* FCOE flags */
 #define IXGBE_ISCSI_FCOE_BLK_PTR            0x17 /* iSCSI/FCOE block */
 #define IXGBE_ISCSI_FCOE_FLAGS_OFFSET       0x0  /* FCOE flags */
 #define IXGBE_ISCSI_FCOE_FLAGS_ENABLE       0x1  /* FCOE flags enable bit */
 #define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR      0x27 /* Alt. SAN MAC block */
 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET  0x0 /* Alt. SAN MAC capability */
 #define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt. SAN MAC 0 offset */
 #define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt. SAN MAC 1 offset */
 #define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET  0x7 /* Alt. WWNN prefix offset */
 #define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET  0x8 /* Alt. WWPN prefix offset */
 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC  0x0 /* Alt. SAN MAC exists */
 #define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN  0x1 /* Alt. WWN base exists */
 #define IXGBE_DEVICE_CAPS_WOL_PORT0_1  0x4 /* WoL supported on ports 0 & 1 */
 #define IXGBE_DEVICE_CAPS_WOL_PORT0    0x8 /* WoL supported on port 0 */
 #define IXGBE_DEVICE_CAPS_WOL_MASK     0xC /* Mask for WoL capabilities */
 /* PCI Bus Info */
 #define IXGBE_PCI_DEVICE_STATUS   0xAA
 #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING   0x0020
 #define IXGBE_PCI_LINK_STATUS     0xB2
 #define IXGBE_PCI_DEVICE_CONTROL2 0xC8
 #define IXGBE_PCI_LINK_WIDTH      0x3F0
 #define IXGBE_PCI_LINK_WIDTH_1    0x10
 #define IXGBE_PCI_LINK_WIDTH_2    0x20
 #define IXGBE_PCI_LINK_WIDTH_4    0x40
 #define IXGBE_PCI_LINK_WIDTH_8    0x80
 #define IXGBE_PCI_LINK_SPEED      0xF
 #define IXGBE_PCI_LINK_SPEED_2500 0x1
 #define IXGBE_PCI_LINK_SPEED_5000 0x2
 #define IXGBE_PCI_LINK_SPEED_8000 0x3
 #define IXGBE_PCI_HEADER_TYPE_REGISTER  0x0E
 #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80
 #define IXGBE_PCI_DEVICE_CONTROL2_16ms  0x0005
 /* Number of 100 microseconds we wait for PCI Express master disable */
 #define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800
 /* RAH */
 #define IXGBE_RAH_VIND_MASK     0x003C0000
 #define IXGBE_RAH_VIND_SHIFT    18
 #define IXGBE_RAH_AV            0x80000000
 #define IXGBE_CLEAR_VMDQ_ALL    0xFFFFFFFF
 /* Header split receive */
 #define IXGBE_RFCTL_ISCSI_DIS       0x00000001
 #define IXGBE_RFCTL_ISCSI_DWC_MASK  0x0000003E
 #define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1
 #define IXGBE_RFCTL_NFSW_DIS        0x00000040
 #define IXGBE_RFCTL_NFSR_DIS        0x00000080
 #define IXGBE_RFCTL_NFS_VER_MASK    0x00000300
 #define IXGBE_RFCTL_NFS_VER_SHIFT   8
 #define IXGBE_RFCTL_NFS_VER_2       0
 #define IXGBE_RFCTL_NFS_VER_3       1
 #define IXGBE_RFCTL_NFS_VER_4       2
 #define IXGBE_RFCTL_IPV6_DIS        0x00000400
 #define IXGBE_RFCTL_IPV6_XSUM_DIS   0x00000800
 #define IXGBE_RFCTL_IPFRSP_DIS      0x00004000
 #define IXGBE_RFCTL_IPV6_EX_DIS     0x00010000
 #define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000
 /* Transmit Config masks */
 #define IXGBE_TXDCTL_ENABLE     0x02000000 /* Enable specific Tx Queue */
 #define IXGBE_TXDCTL_SWFLSH     0x04000000 /* Tx Desc. write-back flushing */
 #define IXGBE_TXDCTL_WTHRESH_SHIFT      16 /* shift to WTHRESH bits */
 /* Enable short packet padding to 64 bytes */
 #define IXGBE_TX_PAD_ENABLE     0x00000400
 #define IXGBE_JUMBO_FRAME_ENABLE 0x00000004  /* Allow jumbo frames */
 /* This allows for 16K packets + 4k for vlan */
 #define IXGBE_MAX_FRAME_SZ      0x40040000
 #define IXGBE_TDWBAL_HEAD_WB_ENABLE   0x1      /* Tx head write-back enable */
 #define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2      /* Tx seq# write-back enable */
 /* Receive Config masks */
 #define IXGBE_RXCTRL_RXEN       0x00000001  /* Enable Receiver */
 #define IXGBE_RXCTRL_DMBYPS     0x00000002  /* Descriptor Monitor Bypass */
 #define IXGBE_RXDCTL_ENABLE     0x02000000  /* Enable specific Rx Queue */
 #define IXGBE_RXDCTL_SWFLSH     0x04000000  /* Rx Desc. write-back flushing */
 #define IXGBE_RXDCTL_RLPMLMASK  0x00003FFF  /* Only supported on the X540 */
 #define IXGBE_RXDCTL_RLPML_EN   0x00008000
 #define IXGBE_RXDCTL_VME        0x40000000  /* VLAN mode enable */
 #define IXGBE_TSAUXC_EN_CLK   0x00000004
 #define IXGBE_TSAUXC_SYNCLK   0x00000008
 #define IXGBE_TSAUXC_SDP0_INT 0x00000040
 #define IXGBE_TSYNCTXCTL_VALID		0x00000001 /* Tx timestamp valid */
 #define IXGBE_TSYNCTXCTL_ENABLED	0x00000010 /* Tx timestamping enabled */
 #define IXGBE_TSYNCRXCTL_VALID		0x00000001 /* Rx timestamp valid */
 #define IXGBE_TSYNCRXCTL_TYPE_MASK	0x0000000E /* Rx type mask */
 #define IXGBE_TSYNCRXCTL_TYPE_L2_V2	0x00
 #define IXGBE_TSYNCRXCTL_TYPE_L4_V1	0x02
 #define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2	0x04
 #define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2	0x0A
 #define IXGBE_TSYNCRXCTL_ENABLED	0x00000010 /* Rx Timestamping enabled */
 #define IXGBE_RXMTRL_V1_CTRLT_MASK	0x000000FF
 #define IXGBE_RXMTRL_V1_SYNC_MSG	0x00
 #define IXGBE_RXMTRL_V1_DELAY_REQ_MSG	0x01
 #define IXGBE_RXMTRL_V1_FOLLOWUP_MSG	0x02
 #define IXGBE_RXMTRL_V1_DELAY_RESP_MSG	0x03
 #define IXGBE_RXMTRL_V1_MGMT_MSG	0x04
 #define IXGBE_RXMTRL_V2_MSGID_MASK		0x0000FF00
 #define IXGBE_RXMTRL_V2_SYNC_MSG		0x0000
 #define IXGBE_RXMTRL_V2_DELAY_REQ_MSG		0x0100
 #define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG		0x0200
 #define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG		0x0300
 #define IXGBE_RXMTRL_V2_FOLLOWUP_MSG		0x0800
 #define IXGBE_RXMTRL_V2_DELAY_RESP_MSG		0x0900
 #define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG	0x0A00
 #define IXGBE_RXMTRL_V2_ANNOUNCE_MSG		0x0B00
 #define IXGBE_RXMTRL_V2_SIGNALING_MSG		0x0C00
 #define IXGBE_RXMTRL_V2_MGMT_MSG		0x0D00
 #define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */
 #define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
 #define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
 #define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
 #define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */
 #define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */
 /* Receive Priority Flow Control Enable */
 #define IXGBE_FCTRL_RPFCE 0x00004000
 #define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */
 #define IXGBE_MFLCN_PMCF        0x00000001 /* Pass MAC Control Frames */
 #define IXGBE_MFLCN_DPF         0x00000002 /* Discard Pause Frame */
 #define IXGBE_MFLCN_RPFCE       0x00000004 /* Receive Priority FC Enable */
 #define IXGBE_MFLCN_RFCE        0x00000008 /* Receive FC Enable */
 #define IXGBE_MFLCN_RPFCE_MASK	0x00000FF4 /* Receive FC Mask */
 #define IXGBE_MFLCN_RPFCE_SHIFT		 4
 /* Multiple Receive Queue Control */
 #define IXGBE_MRQC_RSSEN                 0x00000001  /* RSS Enable */
 #define IXGBE_MRQC_MRQE_MASK                    0xF /* Bits 3:0 */
 #define IXGBE_MRQC_RT8TCEN               0x00000002 /* 8 TC no RSS */
 #define IXGBE_MRQC_RT4TCEN               0x00000003 /* 4 TC no RSS */
 #define IXGBE_MRQC_RTRSS8TCEN            0x00000004 /* 8 TC w/ RSS */
 #define IXGBE_MRQC_RTRSS4TCEN            0x00000005 /* 4 TC w/ RSS */
 #define IXGBE_MRQC_VMDQEN                0x00000008 /* VMDq2 64 pools no RSS */
 #define IXGBE_MRQC_VMDQRSS32EN           0x0000000A /* VMDq2 32 pools w/ RSS */
 #define IXGBE_MRQC_VMDQRSS64EN           0x0000000B /* VMDq2 64 pools w/ RSS */
 #define IXGBE_MRQC_VMDQRT8TCEN           0x0000000C /* VMDq2/RT 16 pool 8 TC */
 #define IXGBE_MRQC_VMDQRT4TCEN           0x0000000D /* VMDq2/RT 32 pool 4 TC */
 #define IXGBE_MRQC_RSS_FIELD_MASK        0xFFFF0000
 #define IXGBE_MRQC_RSS_FIELD_IPV4_TCP    0x00010000
 #define IXGBE_MRQC_RSS_FIELD_IPV4        0x00020000
 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000
 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX     0x00080000
 #define IXGBE_MRQC_RSS_FIELD_IPV6        0x00100000
 #define IXGBE_MRQC_RSS_FIELD_IPV6_TCP    0x00200000
 #define IXGBE_MRQC_RSS_FIELD_IPV4_UDP    0x00400000
 #define IXGBE_MRQC_RSS_FIELD_IPV6_UDP    0x00800000
 #define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000
 #define IXGBE_MRQC_L3L4TXSWEN            0x00008000
 #define IXGBE_FWSM_TS_ENABLED	0x1
 /* Queue Drop Enable */
 #define IXGBE_QDE_ENABLE     0x00000001
 #define IXGBE_QDE_IDX_MASK   0x00007F00
 #define IXGBE_QDE_IDX_SHIFT           8
 #define IXGBE_TXD_POPTS_IXSM 0x01       /* Insert IP checksum */
 #define IXGBE_TXD_POPTS_TXSM 0x02       /* Insert TCP/UDP checksum */
 #define IXGBE_TXD_CMD_EOP    0x01000000 /* End of Packet */
 #define IXGBE_TXD_CMD_IFCS   0x02000000 /* Insert FCS (Ethernet CRC) */
 #define IXGBE_TXD_CMD_IC     0x04000000 /* Insert Checksum */
 #define IXGBE_TXD_CMD_RS     0x08000000 /* Report Status */
 #define IXGBE_TXD_CMD_DEXT   0x20000000 /* Descriptor extension (0 = legacy) */
 #define IXGBE_TXD_CMD_VLE    0x40000000 /* Add VLAN tag */
 #define IXGBE_TXD_STAT_DD    0x00000001 /* Descriptor Done */
 #define IXGBE_RXDADV_IPSEC_STATUS_SECP                  0x00020000
 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL       0x08000000
 #define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH         0x10000000
 #define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED            0x18000000
 #define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK               0x18000000
 /* Multiple Transmit Queue Command Register */
 #define IXGBE_MTQC_RT_ENA       0x1 /* DCB Enable */
 #define IXGBE_MTQC_VT_ENA       0x2 /* VMDQ2 Enable */
 #define IXGBE_MTQC_64Q_1PB      0x0 /* 64 queues 1 pack buffer */
 #define IXGBE_MTQC_32VF         0x8 /* 4 TX Queues per pool w/32VF's */
 #define IXGBE_MTQC_64VF         0x4 /* 2 TX Queues per pool w/64VF's */
 #define IXGBE_MTQC_8TC_8TQ      0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */
 #define IXGBE_MTQC_4TC_4TQ	0x8 /* 4 TC if RT_ENA or 4 TQ if VT_ENA */
 /* Receive Descriptor bit definitions */
 #define IXGBE_RXD_STAT_DD       0x01    /* Descriptor Done */
 #define IXGBE_RXD_STAT_EOP      0x02    /* End of Packet */
 #define IXGBE_RXD_STAT_FLM      0x04    /* FDir Match */
 #define IXGBE_RXD_STAT_VP       0x08    /* IEEE VLAN Packet */
 #define IXGBE_RXDADV_NEXTP_MASK   0x000FFFF0 /* Next Descriptor Index */
 #define IXGBE_RXDADV_NEXTP_SHIFT  0x00000004
 #define IXGBE_RXD_STAT_UDPCS    0x10    /* UDP xsum calculated */
 #define IXGBE_RXD_STAT_L4CS     0x20    /* L4 xsum calculated */
 #define IXGBE_RXD_STAT_IPCS     0x40    /* IP xsum calculated */
 #define IXGBE_RXD_STAT_PIF      0x80    /* passed in-exact filter */
 #define IXGBE_RXD_STAT_CRCV     0x100   /* Speculative CRC Valid */
 #define IXGBE_RXD_STAT_VEXT     0x200   /* 1st VLAN found */
 #define IXGBE_RXD_STAT_UDPV     0x400   /* Valid UDP checksum */
 #define IXGBE_RXD_STAT_DYNINT   0x800   /* Pkt caused INT via DYNINT */
 #define IXGBE_RXD_STAT_LLINT    0x800   /* Pkt caused Low Latency Interrupt */
 #define IXGBE_RXD_STAT_TS       0x10000 /* Time Stamp */
 #define IXGBE_RXD_STAT_SECP     0x20000 /* Security Processing */
 #define IXGBE_RXD_STAT_LB       0x40000 /* Loopback Status */
 #define IXGBE_RXD_STAT_ACK      0x8000  /* ACK Packet indication */
 #define IXGBE_RXD_ERR_CE        0x01    /* CRC Error */
 #define IXGBE_RXD_ERR_LE        0x02    /* Length Error */
 #define IXGBE_RXD_ERR_PE        0x08    /* Packet Error */
 #define IXGBE_RXD_ERR_OSE       0x10    /* Oversize Error */
 #define IXGBE_RXD_ERR_USE       0x20    /* Undersize Error */
 #define IXGBE_RXD_ERR_TCPE      0x40    /* TCP/UDP Checksum Error */
 #define IXGBE_RXD_ERR_IPE       0x80    /* IP Checksum Error */
 #define IXGBE_RXDADV_ERR_MASK           0xfff00000 /* RDESC.ERRORS mask */
 #define IXGBE_RXDADV_ERR_SHIFT          20         /* RDESC.ERRORS shift */
 #define IXGBE_RXDADV_ERR_FCEOFE         0x80000000 /* FCoEFe/IPE */
 #define IXGBE_RXDADV_ERR_FCERR          0x00700000 /* FCERR/FDIRERR */
 #define IXGBE_RXDADV_ERR_FDIR_LEN       0x00100000 /* FDIR Length error */
 #define IXGBE_RXDADV_ERR_FDIR_DROP      0x00200000 /* FDIR Drop error */
 #define IXGBE_RXDADV_ERR_FDIR_COLL      0x00400000 /* FDIR Collision error */
 #define IXGBE_RXDADV_ERR_HBO    0x00800000 /*Header Buffer Overflow */
 #define IXGBE_RXDADV_ERR_CE     0x01000000 /* CRC Error */
 #define IXGBE_RXDADV_ERR_LE     0x02000000 /* Length Error */
 #define IXGBE_RXDADV_ERR_PE     0x08000000 /* Packet Error */
 #define IXGBE_RXDADV_ERR_OSE    0x10000000 /* Oversize Error */
 #define IXGBE_RXDADV_ERR_USE    0x20000000 /* Undersize Error */
 #define IXGBE_RXDADV_ERR_TCPE   0x40000000 /* TCP/UDP Checksum Error */
 #define IXGBE_RXDADV_ERR_IPE    0x80000000 /* IP Checksum Error */
 #define IXGBE_RXD_VLAN_ID_MASK  0x0FFF  /* VLAN ID is in lower 12 bits */
 #define IXGBE_RXD_PRI_MASK      0xE000  /* Priority is in upper 3 bits */
 #define IXGBE_RXD_PRI_SHIFT     13
 #define IXGBE_RXD_CFI_MASK      0x1000  /* CFI is bit 12 */
 #define IXGBE_RXD_CFI_SHIFT     12
 #define IXGBE_RXDADV_STAT_DD            IXGBE_RXD_STAT_DD  /* Done */
 #define IXGBE_RXDADV_STAT_EOP           IXGBE_RXD_STAT_EOP /* End of Packet */
 #define IXGBE_RXDADV_STAT_FLM           IXGBE_RXD_STAT_FLM /* FDir Match */
 #define IXGBE_RXDADV_STAT_VP            IXGBE_RXD_STAT_VP  /* IEEE VLAN Pkt */
 #define IXGBE_RXDADV_STAT_MASK          0x000fffff /* Stat/NEXTP: bit 0-19 */
 #define IXGBE_RXDADV_STAT_FCEOFS        0x00000040 /* FCoE EOF/SOF Stat */
 #define IXGBE_RXDADV_STAT_FCSTAT        0x00000030 /* FCoE Pkt Stat */
 #define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */
 #define IXGBE_RXDADV_STAT_FCSTAT_NODDP  0x00000010 /* 01: Ctxt w/o DDP */
 #define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */
 #define IXGBE_RXDADV_STAT_FCSTAT_DDP    0x00000030 /* 11: Ctxt w/ DDP */
 #define IXGBE_RXDADV_STAT_TS		0x00010000 /* IEEE 1588 Time Stamp */
 /* PSRTYPE bit definitions */
 #define IXGBE_PSRTYPE_TCPHDR    0x00000010
 #define IXGBE_PSRTYPE_UDPHDR    0x00000020
 #define IXGBE_PSRTYPE_IPV4HDR   0x00000100
 #define IXGBE_PSRTYPE_IPV6HDR   0x00000200
 #define IXGBE_PSRTYPE_L2HDR     0x00001000
 /* SRRCTL bit definitions */
 #define IXGBE_SRRCTL_BSIZEPKT_SHIFT     10     /* so many KBs */
 #define IXGBE_SRRCTL_RDMTS_SHIFT        22
 #define IXGBE_SRRCTL_RDMTS_MASK         0x01C00000
 #define IXGBE_SRRCTL_DROP_EN            0x10000000
 #define IXGBE_SRRCTL_BSIZEPKT_MASK      0x0000007F
 #define IXGBE_SRRCTL_BSIZEHDR_MASK      0x00003F00
 #define IXGBE_SRRCTL_DESCTYPE_LEGACY    0x00000000
 #define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT  0x04000000
 #define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
 #define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
 #define IXGBE_SRRCTL_DESCTYPE_MASK      0x0E000000
 #define IXGBE_RXDPS_HDRSTAT_HDRSP       0x00008000
 #define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF
 #define IXGBE_RXDADV_RSSTYPE_MASK       0x0000000F
 #define IXGBE_RXDADV_PKTTYPE_MASK       0x0000FFF0
 #define IXGBE_RXDADV_PKTTYPE_MASK_EX    0x0001FFF0
 #define IXGBE_RXDADV_HDRBUFLEN_MASK     0x00007FE0
 #define IXGBE_RXDADV_RSCCNT_MASK        0x001E0000
 #define IXGBE_RXDADV_RSCCNT_SHIFT       17
 #define IXGBE_RXDADV_HDRBUFLEN_SHIFT    5
 #define IXGBE_RXDADV_SPLITHEADER_EN     0x00001000
 #define IXGBE_RXDADV_SPH                0x8000
 /* RSS Hash results */
 #define IXGBE_RXDADV_RSSTYPE_NONE       0x00000000
 #define IXGBE_RXDADV_RSSTYPE_IPV4_TCP   0x00000001
 #define IXGBE_RXDADV_RSSTYPE_IPV4       0x00000002
 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP   0x00000003
 #define IXGBE_RXDADV_RSSTYPE_IPV6_EX    0x00000004
 #define IXGBE_RXDADV_RSSTYPE_IPV6       0x00000005
 #define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006
 #define IXGBE_RXDADV_RSSTYPE_IPV4_UDP   0x00000007
 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP   0x00000008
 #define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009
 /* RSS Packet Types as indicated in the receive descriptor. */
 #define IXGBE_RXDADV_PKTTYPE_NONE       0x00000000
 #define IXGBE_RXDADV_PKTTYPE_IPV4       0x00000010 /* IPv4 hdr present */
 #define IXGBE_RXDADV_PKTTYPE_IPV4_EX    0x00000020 /* IPv4 hdr + extensions */
 #define IXGBE_RXDADV_PKTTYPE_IPV6       0x00000040 /* IPv6 hdr present */
 #define IXGBE_RXDADV_PKTTYPE_IPV6_EX    0x00000080 /* IPv6 hdr + extensions */
 #define IXGBE_RXDADV_PKTTYPE_TCP        0x00000100 /* TCP hdr present */
 #define IXGBE_RXDADV_PKTTYPE_UDP        0x00000200 /* UDP hdr present */
 #define IXGBE_RXDADV_PKTTYPE_SCTP       0x00000400 /* SCTP hdr present */
 #define IXGBE_RXDADV_PKTTYPE_NFS        0x00000800 /* NFS hdr present */
 #define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP  0x00001000 /* IPSec ESP */
 #define IXGBE_RXDADV_PKTTYPE_IPSEC_AH   0x00002000 /* IPSec AH */
 #define IXGBE_RXDADV_PKTTYPE_LINKSEC    0x00004000 /* LinkSec Encap */
 #define IXGBE_RXDADV_PKTTYPE_ETQF       0x00008000 /* PKTTYPE is ETQF index */
 #define IXGBE_RXDADV_PKTTYPE_ETQF_MASK  0x00000070 /* ETQF has 8 indices */
 #define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4          /* Right-shift 4 bits */
 /* Security Processing bit Indication */
 #define IXGBE_RXDADV_LNKSEC_STATUS_SECP         0x00020000
 #define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH   0x08000000
 #define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR  0x10000000
 #define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK      0x18000000
 #define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG       0x18000000
 /* Masks to determine if packets should be dropped due to frame errors */
 #define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \
                                       IXGBE_RXD_ERR_CE | \
                                       IXGBE_RXD_ERR_LE | \
                                       IXGBE_RXD_ERR_PE | \
                                       IXGBE_RXD_ERR_OSE | \
                                       IXGBE_RXD_ERR_USE)
 #define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \
                                       IXGBE_RXDADV_ERR_CE | \
                                       IXGBE_RXDADV_ERR_LE | \
                                       IXGBE_RXDADV_ERR_PE | \
                                       IXGBE_RXDADV_ERR_OSE | \
                                       IXGBE_RXDADV_ERR_USE)
 /* Multicast bit mask */
 #define IXGBE_MCSTCTRL_MFE      0x4
 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */
 #define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE  8
 #define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE  8
 #define IXGBE_REQ_TX_BUFFER_GRANULARITY   1024
 /* Vlan-specific macros */
 #define IXGBE_RX_DESC_SPECIAL_VLAN_MASK  0x0FFF /* VLAN ID in lower 12 bits */
 #define IXGBE_RX_DESC_SPECIAL_PRI_MASK   0xE000 /* Priority in upper 3 bits */
 #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT  0x000D /* Priority in upper 3 of 16 */
 #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT  IXGBE_RX_DESC_SPECIAL_PRI_SHIFT
 /* SR-IOV specific macros */
 #define IXGBE_MBVFICR_INDEX(vf_number)   (vf_number >> 4)
 #define IXGBE_MBVFICR(_i)		(0x00710 + ((_i) * 4))
 #define IXGBE_VFLRE(_i)		((((_i) & 1) ? 0x001C0 : 0x00600))
 #define IXGBE_VFLREC(_i)		(0x00700 + ((_i) * 4))
 enum ixgbe_fdir_pballoc_type {
 	IXGBE_FDIR_PBALLOC_NONE = 0,
 	IXGBE_FDIR_PBALLOC_64K  = 1,
 	IXGBE_FDIR_PBALLOC_128K = 2,
 	IXGBE_FDIR_PBALLOC_256K = 3,
 };
 #define IXGBE_FDIR_PBALLOC_SIZE_SHIFT           16
 /* Flow Director register values */
 #define IXGBE_FDIRCTRL_PBALLOC_64K              0x00000001
 #define IXGBE_FDIRCTRL_PBALLOC_128K             0x00000002
 #define IXGBE_FDIRCTRL_PBALLOC_256K             0x00000003
 #define IXGBE_FDIRCTRL_INIT_DONE                0x00000008
 #define IXGBE_FDIRCTRL_PERFECT_MATCH            0x00000010
 #define IXGBE_FDIRCTRL_REPORT_STATUS            0x00000020
 #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS     0x00000080
 #define IXGBE_FDIRCTRL_DROP_Q_SHIFT             8
 #define IXGBE_FDIRCTRL_FLEX_SHIFT               16
 #define IXGBE_FDIRCTRL_SEARCHLIM                0x00800000
 #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT         24
 #define IXGBE_FDIRCTRL_FULL_THRESH_MASK         0xF0000000
 #define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT        28
 #define IXGBE_FDIRTCPM_DPORTM_SHIFT             16
 #define IXGBE_FDIRUDPM_DPORTM_SHIFT             16
 #define IXGBE_FDIRIP6M_DIPM_SHIFT               16
 #define IXGBE_FDIRM_VLANID                      0x00000001
 #define IXGBE_FDIRM_VLANP                       0x00000002
 #define IXGBE_FDIRM_POOL                        0x00000004
 #define IXGBE_FDIRM_L4P                         0x00000008
 #define IXGBE_FDIRM_FLEX                        0x00000010
 #define IXGBE_FDIRM_DIPv6                       0x00000020
 #define IXGBE_FDIRFREE_FREE_MASK                0xFFFF
 #define IXGBE_FDIRFREE_FREE_SHIFT               0
 #define IXGBE_FDIRFREE_COLL_MASK                0x7FFF0000
 #define IXGBE_FDIRFREE_COLL_SHIFT               16
 #define IXGBE_FDIRLEN_MAXLEN_MASK               0x3F
 #define IXGBE_FDIRLEN_MAXLEN_SHIFT              0
 #define IXGBE_FDIRLEN_MAXHASH_MASK              0x7FFF0000
 #define IXGBE_FDIRLEN_MAXHASH_SHIFT             16
 #define IXGBE_FDIRUSTAT_ADD_MASK                0xFFFF
 #define IXGBE_FDIRUSTAT_ADD_SHIFT               0
 #define IXGBE_FDIRUSTAT_REMOVE_MASK             0xFFFF0000
 #define IXGBE_FDIRUSTAT_REMOVE_SHIFT            16
 #define IXGBE_FDIRFSTAT_FADD_MASK               0x00FF
 #define IXGBE_FDIRFSTAT_FADD_SHIFT              0
 #define IXGBE_FDIRFSTAT_FREMOVE_MASK            0xFF00
 #define IXGBE_FDIRFSTAT_FREMOVE_SHIFT           8
 #define IXGBE_FDIRPORT_DESTINATION_SHIFT        16
 #define IXGBE_FDIRVLAN_FLEX_SHIFT               16
 #define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT       15
 #define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT       16
 #define IXGBE_FDIRCMD_CMD_MASK                  0x00000003
 #define IXGBE_FDIRCMD_CMD_ADD_FLOW              0x00000001
 #define IXGBE_FDIRCMD_CMD_REMOVE_FLOW           0x00000002
 #define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT        0x00000003
 #define IXGBE_FDIRCMD_FILTER_VALID              0x00000004
 #define IXGBE_FDIRCMD_FILTER_UPDATE             0x00000008
 #define IXGBE_FDIRCMD_IPv6DMATCH                0x00000010
 #define IXGBE_FDIRCMD_L4TYPE_UDP                0x00000020
 #define IXGBE_FDIRCMD_L4TYPE_TCP                0x00000040
 #define IXGBE_FDIRCMD_L4TYPE_SCTP               0x00000060
 #define IXGBE_FDIRCMD_IPV6                      0x00000080
 #define IXGBE_FDIRCMD_CLEARHT                   0x00000100
 #define IXGBE_FDIRCMD_DROP                      0x00000200
 #define IXGBE_FDIRCMD_INT                       0x00000400
 #define IXGBE_FDIRCMD_LAST                      0x00000800
 #define IXGBE_FDIRCMD_COLLISION                 0x00001000
 #define IXGBE_FDIRCMD_QUEUE_EN                  0x00008000
 #define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT           5
 #define IXGBE_FDIRCMD_RX_QUEUE_SHIFT            16
 #define IXGBE_FDIRCMD_VT_POOL_SHIFT             24
 #define IXGBE_FDIR_INIT_DONE_POLL               10
 #define IXGBE_FDIRCMD_CMD_POLL                  10
 #define IXGBE_FDIR_DROP_QUEUE                   127
 /* Manageablility Host Interface defines */
 #define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH       1792 /* Num of bytes in range */
 #define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH      448 /* Num of dwords in range */
 #define IXGBE_HI_COMMAND_TIMEOUT             500 /* Process HI command limit */
 /* CEM Support */
 #define FW_CEM_HDR_LEN                0x4
 #define FW_CEM_CMD_DRIVER_INFO        0xDD
 #define FW_CEM_CMD_DRIVER_INFO_LEN    0x5
 #define FW_CEM_CMD_RESERVED           0x0
 #define FW_CEM_UNUSED_VER             0x0
 #define FW_CEM_MAX_RETRIES            3
 #define FW_CEM_RESP_STATUS_SUCCESS    0x1
 /* Host Interface Command Structures */
 struct ixgbe_hic_hdr {
 	u8 cmd;
 	u8 buf_len;
 	union {
 		u8 cmd_resv;
 		u8 ret_status;
 	} cmd_or_resp;
 	u8 checksum;
 };
 struct ixgbe_hic_drv_info {
 	struct ixgbe_hic_hdr hdr;
 	u8 port_num;
 	u8 ver_sub;
 	u8 ver_build;
 	u8 ver_min;
 	u8 ver_maj;
 	u8 pad; /* end spacing to ensure length is mult. of dword */
 	u16 pad2; /* end spacing to ensure length is mult. of dword2 */
 };
 /* Transmit Descriptor - Advanced */
 union ixgbe_adv_tx_desc {
 	struct {
 		__le64 buffer_addr;      /* Address of descriptor's data buf */
 		__le32 cmd_type_len;
 		__le32 olinfo_status;
 	} read;
 	struct {
 		__le64 rsvd;       /* Reserved */
 		__le32 nxtseq_seed;
 		__le32 status;
 	} wb;
 };
 /* Receive Descriptor - Advanced */
 union ixgbe_adv_rx_desc {
 	struct {
 		__le64 pkt_addr; /* Packet buffer address */
 		__le64 hdr_addr; /* Header buffer address */
 	} read;
 	struct {
 		struct {
 			union {
 				__le32 data;
 				struct {
 					__le16 pkt_info; /* RSS, Pkt type */
 					__le16 hdr_info; /* Splithdr, hdrlen */
 				} hs_rss;
 			} lo_dword;
 			union {
 				__le32 rss; /* RSS Hash */
 				struct {
 					__le16 ip_id; /* IP id */
 					__le16 csum; /* Packet Checksum */
 				} csum_ip;
 			} hi_dword;
 		} lower;
 		struct {
 			__le32 status_error; /* ext status/error */
 			__le16 length; /* Packet length */
 			__le16 vlan; /* VLAN tag */
 		} upper;
 	} wb;  /* writeback */
 };
 /* Context descriptors */
 struct ixgbe_adv_tx_context_desc {
 	__le32 vlan_macip_lens;
 	__le32 seqnum_seed;
 	__le32 type_tucmd_mlhl;
 	__le32 mss_l4len_idx;
 };
 /* Adv Transmit Descriptor Config Masks */
 #define IXGBE_ADVTXD_DTALEN_MASK      0x0000FFFF /* Data buf length(bytes) */
 #define IXGBE_ADVTXD_MAC_LINKSEC      0x00040000 /* Insert LinkSec */
 #define IXGBE_ADVTXD_MAC_TSTAMP	      0x00080000 /* IEEE 1588 Time Stamp */
 #define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK   0x000003FF /* IPSec SA index */
 #define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK    0x000001FF /* IPSec ESP length */
 #define IXGBE_ADVTXD_DTYP_MASK  0x00F00000 /* DTYP mask */
 #define IXGBE_ADVTXD_DTYP_CTXT  0x00200000 /* Advanced Context Desc */
 #define IXGBE_ADVTXD_DTYP_DATA  0x00300000 /* Advanced Data Descriptor */
 #define IXGBE_ADVTXD_DCMD_EOP   IXGBE_TXD_CMD_EOP  /* End of Packet */
 #define IXGBE_ADVTXD_DCMD_IFCS  IXGBE_TXD_CMD_IFCS /* Insert FCS */
 #define IXGBE_ADVTXD_DCMD_RS    IXGBE_TXD_CMD_RS   /* Report Status */
 #define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000    /* DDP hdr type or iSCSI */
 #define IXGBE_ADVTXD_DCMD_DEXT  IXGBE_TXD_CMD_DEXT /* Desc ext (1=Adv) */
 #define IXGBE_ADVTXD_DCMD_VLE   IXGBE_TXD_CMD_VLE  /* VLAN pkt enable */
 #define IXGBE_ADVTXD_DCMD_TSE   0x80000000 /* TCP Seg enable */
 #define IXGBE_ADVTXD_STAT_DD    IXGBE_TXD_STAT_DD  /* Descriptor Done */
 #define IXGBE_ADVTXD_STAT_SN_CRC      0x00000002 /* NXTSEQ/SEED pres in WB */
 #define IXGBE_ADVTXD_STAT_RSV   0x0000000C /* STA Reserved */
 #define IXGBE_ADVTXD_IDX_SHIFT  4 /* Adv desc Index shift */
 #define IXGBE_ADVTXD_CC         0x00000080 /* Check Context */
 #define IXGBE_ADVTXD_POPTS_SHIFT      8  /* Adv desc POPTS shift */
 #define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \
                                  IXGBE_ADVTXD_POPTS_SHIFT)
 #define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \
                                  IXGBE_ADVTXD_POPTS_SHIFT)
 #define IXGBE_ADVTXD_POPTS_ISCO_1ST  0x00000000 /* 1st TSO of iSCSI PDU */
 #define IXGBE_ADVTXD_POPTS_ISCO_MDL  0x00000800 /* Middle TSO of iSCSI PDU */
 #define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */
 #define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 /* 1st&Last TSO-full iSCSI PDU */
 #define IXGBE_ADVTXD_POPTS_RSV       0x00002000 /* POPTS Reserved */
 #define IXGBE_ADVTXD_PAYLEN_SHIFT    14 /* Adv desc PAYLEN shift */
 #define IXGBE_ADVTXD_MACLEN_SHIFT    9  /* Adv ctxt desc mac len shift */
 #define IXGBE_ADVTXD_VLAN_SHIFT      16  /* Adv ctxt vlan tag shift */
 #define IXGBE_ADVTXD_TUCMD_IPV4      0x00000400  /* IP Packet Type: 1=IPv4 */
 #define IXGBE_ADVTXD_TUCMD_IPV6      0x00000000  /* IP Packet Type: 0=IPv6 */
 #define IXGBE_ADVTXD_TUCMD_L4T_UDP   0x00000000  /* L4 Packet TYPE of UDP */
 #define IXGBE_ADVTXD_TUCMD_L4T_TCP   0x00000800  /* L4 Packet TYPE of TCP */
 #define IXGBE_ADVTXD_TUCMD_L4T_SCTP  0x00001000  /* L4 Packet TYPE of SCTP */
 #define IXGBE_ADVTXD_TUCMD_MKRREQ    0x00002000 /*Req requires Markers and CRC*/
 #define IXGBE_ADVTXD_POPTS_IPSEC      0x00000400 /* IPSec offload request */
 #define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */
 #define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */
 #define IXGBE_ADVTXT_TUCMD_FCOE      0x00008000       /* FCoE Frame Type */
 #define IXGBE_ADVTXD_FCOEF_EOF_MASK  (0x3 << 10)      /* FC EOF index */
 #define IXGBE_ADVTXD_FCOEF_SOF       ((1 << 2) << 10) /* FC SOF index */
 #define IXGBE_ADVTXD_FCOEF_PARINC    ((1 << 3) << 10) /* Rel_Off in F_CTL */
 #define IXGBE_ADVTXD_FCOEF_ORIE      ((1 << 4) << 10) /* Orientation: End */
 #define IXGBE_ADVTXD_FCOEF_ORIS      ((1 << 5) << 10) /* Orientation: Start */
 #define IXGBE_ADVTXD_FCOEF_EOF_N     (0x0 << 10)      /* 00: EOFn */
 #define IXGBE_ADVTXD_FCOEF_EOF_T     (0x1 << 10)      /* 01: EOFt */
 #define IXGBE_ADVTXD_FCOEF_EOF_NI    (0x2 << 10)      /* 10: EOFni */
 #define IXGBE_ADVTXD_FCOEF_EOF_A     (0x3 << 10)      /* 11: EOFa */
 #define IXGBE_ADVTXD_L4LEN_SHIFT     8  /* Adv ctxt L4LEN shift */
 #define IXGBE_ADVTXD_MSS_SHIFT       16  /* Adv ctxt MSS shift */
 /* Autonegotiation advertised speeds */
 typedef u32 ixgbe_autoneg_advertised;
 /* Link speed */
 typedef u32 ixgbe_link_speed;
 #define IXGBE_LINK_SPEED_UNKNOWN   0
 #define IXGBE_LINK_SPEED_100_FULL  0x0008
 #define IXGBE_LINK_SPEED_1GB_FULL  0x0020
 #define IXGBE_LINK_SPEED_10GB_FULL 0x0080
 #define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \
                                         IXGBE_LINK_SPEED_10GB_FULL)
 #define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \
                                         IXGBE_LINK_SPEED_1GB_FULL | \
                                         IXGBE_LINK_SPEED_10GB_FULL)
 /* Physical layer type */
 typedef u32 ixgbe_physical_layer;
 #define IXGBE_PHYSICAL_LAYER_UNKNOWN      0
 #define IXGBE_PHYSICAL_LAYER_10GBASE_T    0x0001
 #define IXGBE_PHYSICAL_LAYER_1000BASE_T   0x0002
 #define IXGBE_PHYSICAL_LAYER_100BASE_TX   0x0004
 #define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU  0x0008
 #define IXGBE_PHYSICAL_LAYER_10GBASE_LR   0x0010
 #define IXGBE_PHYSICAL_LAYER_10GBASE_LRM  0x0020
 #define IXGBE_PHYSICAL_LAYER_10GBASE_SR   0x0040
 #define IXGBE_PHYSICAL_LAYER_10GBASE_KX4  0x0080
 #define IXGBE_PHYSICAL_LAYER_10GBASE_CX4  0x0100
 #define IXGBE_PHYSICAL_LAYER_1000BASE_KX  0x0200
 #define IXGBE_PHYSICAL_LAYER_1000BASE_BX  0x0400
 #define IXGBE_PHYSICAL_LAYER_10GBASE_KR   0x0800
 #define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000
 #define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000
 /* Flow Control Data Sheet defined values
  * Calculation and defines taken from 802.1bb Annex O
  */
 /* BitTimes (BT) conversion */
 #define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024))
 #define IXGBE_B2BT(BT) (BT * 8)
 /* Calculate Delay to respond to PFC */
 #define IXGBE_PFC_D	672
 /* Calculate Cable Delay */
 #define IXGBE_CABLE_DC	5556 /* Delay Copper */
 #define IXGBE_CABLE_DO	5000 /* Delay Optical */
 /* Calculate Interface Delay X540 */
 #define IXGBE_PHY_DC	25600	/* Delay 10G BASET */
 #define IXGBE_MAC_DC	8192	/* Delay Copper XAUI interface */
 #define IXGBE_XAUI_DC	(2 * 2048) /* Delay Copper Phy */
 #define IXGBE_ID_X540	(IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC)
 /* Calculate Interface Delay 82598, 82599 */
 #define IXGBE_PHY_D	12800
 #define IXGBE_MAC_D	4096
 #define IXGBE_XAUI_D	(2 * 1024)
 #define IXGBE_ID	(IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D)
 /* Calculate Delay incurred from higher layer */
 #define IXGBE_HD	6144
 /* Calculate PCI Bus delay for low thresholds */
 #define IXGBE_PCI_DELAY	10000
 /* Calculate X540 delay value in bit times */
 #define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \
 			((36 * \
 			  (IXGBE_B2BT(_max_frame_link) + \
 			   IXGBE_PFC_D + \
 			   (2 * IXGBE_CABLE_DC) + \
 			   (2 * IXGBE_ID_X540) + \
 			   IXGBE_HD) / 25 + 1) + \
 			 2 * IXGBE_B2BT(_max_frame_tc))
 /* Calculate 82599, 82598 delay value in bit times */
 #define IXGBE_DV(_max_frame_link, _max_frame_tc) \
 			((36 * \
 			  (IXGBE_B2BT(_max_frame_link) + \
 			   IXGBE_PFC_D + \
 			   (2 * IXGBE_CABLE_DC) + \
 			   (2 * IXGBE_ID) + \
 			   IXGBE_HD) / 25 + 1) + \
 			 2 * IXGBE_B2BT(_max_frame_tc))
 /* Calculate low threshold delay values */
 #define IXGBE_LOW_DV_X540(_max_frame_tc) \
 			(2 * IXGBE_B2BT(_max_frame_tc) + \
 			(36 * IXGBE_PCI_DELAY / 25) + 1)
 #define IXGBE_LOW_DV(_max_frame_tc) \
 			(2 * IXGBE_LOW_DV_X540(_max_frame_tc))
 /* Software ATR hash keys */
 #define IXGBE_ATR_BUCKET_HASH_KEY    0x3DAD14E2
 #define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614
 /* Software ATR input stream values and masks */
 #define IXGBE_ATR_HASH_MASK     0x7fff
 #define IXGBE_ATR_L4TYPE_MASK      0x3
 #define IXGBE_ATR_L4TYPE_UDP       0x1
 #define IXGBE_ATR_L4TYPE_TCP       0x2
 #define IXGBE_ATR_L4TYPE_SCTP      0x3
 #define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4
 enum ixgbe_atr_flow_type {
 	IXGBE_ATR_FLOW_TYPE_IPV4   = 0x0,
 	IXGBE_ATR_FLOW_TYPE_UDPV4  = 0x1,
 	IXGBE_ATR_FLOW_TYPE_TCPV4  = 0x2,
 	IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3,
 	IXGBE_ATR_FLOW_TYPE_IPV6   = 0x4,
 	IXGBE_ATR_FLOW_TYPE_UDPV6  = 0x5,
 	IXGBE_ATR_FLOW_TYPE_TCPV6  = 0x6,
 	IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7,
 };
 /* Flow Director ATR input struct. */
 union ixgbe_atr_input {
 	/*
 	 * Byte layout in order, all values with MSB first:
 	 *
 	 * vm_pool    - 1 byte
 	 * flow_type  - 1 byte
 	 * vlan_id    - 2 bytes
 	 * src_ip     - 16 bytes
 	 * dst_ip     - 16 bytes
 	 * src_port   - 2 bytes
 	 * dst_port   - 2 bytes
 	 * flex_bytes - 2 bytes
 	 * bkt_hash   - 2 bytes
 	 */
 	struct {
 		u8     vm_pool;
 		u8     flow_type;
 		__be16 vlan_id;
 		__be32 dst_ip[4];
 		__be32 src_ip[4];
 		__be16 src_port;
 		__be16 dst_port;
 		__be16 flex_bytes;
 		__be16 bkt_hash;
 	} formatted;
 	__be32 dword_stream[11];
 };
 /* Flow Director compressed ATR hash input struct */
 union ixgbe_atr_hash_dword {
 	struct {
 		u8 vm_pool;
 		u8 flow_type;
 		__be16 vlan_id;
 	} formatted;
 	__be32 ip;
 	struct {
 		__be16 src;
 		__be16 dst;
 	} port;
 	__be16 flex_bytes;
 	__be32 dword;
 };
 enum ixgbe_eeprom_type {
 	ixgbe_eeprom_uninitialized = 0,
 	ixgbe_eeprom_spi,
 	ixgbe_flash,
 	ixgbe_eeprom_none /* No NVM support */
 };
 enum ixgbe_mac_type {
 	ixgbe_mac_unknown = 0,
 	ixgbe_mac_82598EB,
 	ixgbe_mac_82599EB,
 	ixgbe_mac_X540,
 	ixgbe_num_macs
 };
 enum ixgbe_phy_type {
 	ixgbe_phy_unknown = 0,
 	ixgbe_phy_none,
 	ixgbe_phy_tn,
 	ixgbe_phy_aq,
 	ixgbe_phy_cu_unknown,
 	ixgbe_phy_qt,
 	ixgbe_phy_xaui,
 	ixgbe_phy_nl,
 	ixgbe_phy_sfp_passive_tyco,
 	ixgbe_phy_sfp_passive_unknown,
 	ixgbe_phy_sfp_active_unknown,
 	ixgbe_phy_sfp_avago,
 	ixgbe_phy_sfp_ftl,
 	ixgbe_phy_sfp_ftl_active,
 	ixgbe_phy_sfp_unknown,
 	ixgbe_phy_sfp_intel,
 	ixgbe_phy_sfp_unsupported,
 	ixgbe_phy_generic
 };
 /*
  * SFP+ module type IDs:
  *
  * ID   Module Type
  * =============
  * 0    SFP_DA_CU
  * 1    SFP_SR
  * 2    SFP_LR
  * 3    SFP_DA_CU_CORE0 - 82599-specific
  * 4    SFP_DA_CU_CORE1 - 82599-specific
  * 5    SFP_SR/LR_CORE0 - 82599-specific
  * 6    SFP_SR/LR_CORE1 - 82599-specific
  */
 enum ixgbe_sfp_type {
 	ixgbe_sfp_type_da_cu = 0,
 	ixgbe_sfp_type_sr = 1,
 	ixgbe_sfp_type_lr = 2,
 	ixgbe_sfp_type_da_cu_core0 = 3,
 	ixgbe_sfp_type_da_cu_core1 = 4,
 	ixgbe_sfp_type_srlr_core0 = 5,
 	ixgbe_sfp_type_srlr_core1 = 6,
 	ixgbe_sfp_type_da_act_lmt_core0 = 7,
 	ixgbe_sfp_type_da_act_lmt_core1 = 8,
 	ixgbe_sfp_type_1g_cu_core0 = 9,
 	ixgbe_sfp_type_1g_cu_core1 = 10,
 	ixgbe_sfp_type_1g_sx_core0 = 11,
 	ixgbe_sfp_type_1g_sx_core1 = 12,
 	ixgbe_sfp_type_1g_lx_core0 = 13,
 	ixgbe_sfp_type_1g_lx_core1 = 14,
 	ixgbe_sfp_type_not_present = 0xFFFE,
 	ixgbe_sfp_type_unknown = 0xFFFF
 };
 enum ixgbe_media_type {
 	ixgbe_media_type_unknown = 0,
 	ixgbe_media_type_fiber,
+	ixgbe_media_type_fiber_fixed,
 	ixgbe_media_type_fiber_lco,
 	ixgbe_media_type_copper,
 	ixgbe_media_type_backplane,
 	ixgbe_media_type_cx4,
 	ixgbe_media_type_virtual
 };
 /* Flow Control Settings */
 enum ixgbe_fc_mode {
 	ixgbe_fc_none = 0,
 	ixgbe_fc_rx_pause,
 	ixgbe_fc_tx_pause,
 	ixgbe_fc_full,
 	ixgbe_fc_default
 };
 /* Smart Speed Settings */
 #define IXGBE_SMARTSPEED_MAX_RETRIES	3
 enum ixgbe_smart_speed {
 	ixgbe_smart_speed_auto = 0,
 	ixgbe_smart_speed_on,
 	ixgbe_smart_speed_off
 };
 /* PCI bus types */
 enum ixgbe_bus_type {
 	ixgbe_bus_type_unknown = 0,
 	ixgbe_bus_type_pci,
 	ixgbe_bus_type_pcix,
 	ixgbe_bus_type_pci_express,
 	ixgbe_bus_type_reserved
 };
 /* PCI bus speeds */
 enum ixgbe_bus_speed {
 	ixgbe_bus_speed_unknown = 0,
 	ixgbe_bus_speed_33      = 33,
 	ixgbe_bus_speed_66      = 66,
 	ixgbe_bus_speed_100     = 100,
 	ixgbe_bus_speed_120     = 120,
 	ixgbe_bus_speed_133     = 133,
 	ixgbe_bus_speed_2500    = 2500,
 	ixgbe_bus_speed_5000    = 5000,
 	ixgbe_bus_speed_8000    = 8000,
 	ixgbe_bus_speed_reserved
 };
 /* PCI bus widths */
 enum ixgbe_bus_width {
 	ixgbe_bus_width_unknown = 0,
 	ixgbe_bus_width_pcie_x1 = 1,
 	ixgbe_bus_width_pcie_x2 = 2,
 	ixgbe_bus_width_pcie_x4 = 4,
 	ixgbe_bus_width_pcie_x8 = 8,
 	ixgbe_bus_width_32      = 32,
 	ixgbe_bus_width_64      = 64,
 	ixgbe_bus_width_reserved
 };
 struct ixgbe_addr_filter_info {
 	u32 num_mc_addrs;
 	u32 rar_used_count;
 	u32 mta_in_use;
 	u32 overflow_promisc;
 	bool uc_set_promisc;
 	bool user_set_promisc;
 };
 /* Bus parameters */
 struct ixgbe_bus_info {
 	enum ixgbe_bus_speed speed;
 	enum ixgbe_bus_width width;
 	enum ixgbe_bus_type type;
 	u16 func;
 	u16 lan_id;
 };
 /* Flow control parameters */
 struct ixgbe_fc_info {
 	u32 high_water[MAX_TRAFFIC_CLASS]; /* Flow Control High-water */
 	u32 low_water; /* Flow Control Low-water */
 	u16 pause_time; /* Flow Control Pause timer */
 	bool send_xon; /* Flow control send XON */
 	bool strict_ieee; /* Strict IEEE mode */
 	bool disable_fc_autoneg; /* Do not autonegotiate FC */
 	bool fc_was_autonegged; /* Is current_mode the result of autonegging? */
 	enum ixgbe_fc_mode current_mode; /* FC mode in effect */
 	enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */
 };
 /* Statistics counters collected by the MAC */
 struct ixgbe_hw_stats {
 	u64 crcerrs;
 	u64 illerrc;
 	u64 errbc;
 	u64 mspdc;
 	u64 mpctotal;
 	u64 mpc[8];
 	u64 mlfc;
 	u64 mrfc;
 	u64 rlec;
 	u64 lxontxc;
 	u64 lxonrxc;
 	u64 lxofftxc;
 	u64 lxoffrxc;
 	u64 pxontxc[8];
 	u64 pxonrxc[8];
 	u64 pxofftxc[8];
 	u64 pxoffrxc[8];
 	u64 prc64;
 	u64 prc127;
 	u64 prc255;
 	u64 prc511;
 	u64 prc1023;
 	u64 prc1522;
 	u64 gprc;
 	u64 bprc;
 	u64 mprc;
 	u64 gptc;
 	u64 gorc;
 	u64 gotc;
 	u64 rnbc[8];
 	u64 ruc;
 	u64 rfc;
 	u64 roc;
 	u64 rjc;
 	u64 mngprc;
 	u64 mngpdc;
 	u64 mngptc;
 	u64 tor;
 	u64 tpr;
 	u64 tpt;
 	u64 ptc64;
 	u64 ptc127;
 	u64 ptc255;
 	u64 ptc511;
 	u64 ptc1023;
 	u64 ptc1522;
 	u64 mptc;
 	u64 bptc;
 	u64 xec;
 	u64 rqsmr[16];
 	u64 tqsmr[8];
 	u64 qprc[16];
 	u64 qptc[16];
 	u64 qbrc[16];
 	u64 qbtc[16];
 	u64 qprdc[16];
 	u64 pxon2offc[8];
 	u64 fdirustat_add;
 	u64 fdirustat_remove;
 	u64 fdirfstat_fadd;
 	u64 fdirfstat_fremove;
 	u64 fdirmatch;
 	u64 fdirmiss;
 	u64 fccrc;
 	u64 fcoerpdc;
 	u64 fcoeprc;
 	u64 fcoeptc;
 	u64 fcoedwrc;
 	u64 fcoedwtc;
 	u64 fcoe_noddp;
 	u64 fcoe_noddp_ext_buff;
 	u64 b2ospc;
 	u64 b2ogprc;
 	u64 o2bgptc;
 	u64 o2bspc;
 };
 /* forward declaration */
 struct ixgbe_hw;
 /* iterator type for walking multicast address lists */
 typedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr,
                                   u32 *vmdq);
 /* Function pointer table */
 struct ixgbe_eeprom_operations {
 	s32 (*init_params)(struct ixgbe_hw *);
 	s32 (*read)(struct ixgbe_hw *, u16, u16 *);
 	s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
 	s32 (*write)(struct ixgbe_hw *, u16, u16);
 	s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *);
 	s32 (*validate_checksum)(struct ixgbe_hw *, u16 *);
 	s32 (*update_checksum)(struct ixgbe_hw *);
 	u16 (*calc_checksum)(struct ixgbe_hw *);
 };
 struct ixgbe_mac_operations {
 	s32 (*init_hw)(struct ixgbe_hw *);
 	s32 (*reset_hw)(struct ixgbe_hw *);
 	s32 (*start_hw)(struct ixgbe_hw *);
 	s32 (*clear_hw_cntrs)(struct ixgbe_hw *);
 	enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *);
 	u32 (*get_supported_physical_layer)(struct ixgbe_hw *);
 	s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *);
 	s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *);
 	s32 (*get_device_caps)(struct ixgbe_hw *, u16 *);
 	s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *);
 	s32 (*stop_adapter)(struct ixgbe_hw *);
 	s32 (*get_bus_info)(struct ixgbe_hw *);
 	void (*set_lan_id)(struct ixgbe_hw *);
 	s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*);
 	s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8);
 	s32 (*setup_sfp)(struct ixgbe_hw *);
 	s32 (*disable_rx_buff)(struct ixgbe_hw *);
 	s32 (*enable_rx_buff)(struct ixgbe_hw *);
 	s32 (*enable_rx_dma)(struct ixgbe_hw *, u32);
 	s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u16);
 	void (*release_swfw_sync)(struct ixgbe_hw *, u16);
 	/* Link */
 	void (*disable_tx_laser)(struct ixgbe_hw *);
 	void (*enable_tx_laser)(struct ixgbe_hw *);
 	void (*flap_tx_laser)(struct ixgbe_hw *);
 	s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool);
 	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool);
 	s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *,
 	                             bool *);
 	/* Packet Buffer Manipulation */
 	void (*set_rxpba)(struct ixgbe_hw *, int, u32, int);
 	/* LED */
 	s32 (*led_on)(struct ixgbe_hw *, u32);
 	s32 (*led_off)(struct ixgbe_hw *, u32);
 	s32 (*blink_led_start)(struct ixgbe_hw *, u32);
 	s32 (*blink_led_stop)(struct ixgbe_hw *, u32);
 	/* RAR, Multicast, VLAN */
 	s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32);
 	s32 (*clear_rar)(struct ixgbe_hw *, u32);
 	s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32);
 	s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32);
 	s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32);
 	s32 (*init_rx_addrs)(struct ixgbe_hw *);
 	s32 (*update_mc_addr_list)(struct ixgbe_hw *, struct net_device *);
 	s32 (*enable_mc)(struct ixgbe_hw *);
 	s32 (*disable_mc)(struct ixgbe_hw *);
 	s32 (*clear_vfta)(struct ixgbe_hw *);
 	s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool);
 	s32 (*init_uta_tables)(struct ixgbe_hw *);
 	void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int);
 	void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int);
 	/* Flow Control */
 	s32 (*fc_enable)(struct ixgbe_hw *);
 	/* Manageability interface */
 	s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8);
 	s32 (*get_thermal_sensor_data)(struct ixgbe_hw *);
 	s32 (*init_thermal_sensor_thresh)(struct ixgbe_hw *hw);
 	bool (*mng_fw_enabled)(struct ixgbe_hw *hw);
 };
 struct ixgbe_phy_operations {
 	s32 (*identify)(struct ixgbe_hw *);
 	s32 (*identify_sfp)(struct ixgbe_hw *);
 	s32 (*init)(struct ixgbe_hw *);
 	s32 (*reset)(struct ixgbe_hw *);
 	s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *);
 	s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16);
 	s32 (*setup_link)(struct ixgbe_hw *);
 	s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool);
 	s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *);
 	s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *);
 	s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *);
 	s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8);
 	s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *);
 	s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *);
 	s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8);
 	s32 (*check_overtemp)(struct ixgbe_hw *);
 };
 struct ixgbe_eeprom_info {
 	struct ixgbe_eeprom_operations  ops;
 	enum ixgbe_eeprom_type          type;
 	u32                             semaphore_delay;
 	u16                             word_size;
 	u16                             address_bits;
 	u16                             word_page_size;
 };
 #define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED	0x01
 struct ixgbe_mac_info {
 	struct ixgbe_mac_operations     ops;
 	enum ixgbe_mac_type             type;
 	u8                              addr[ETH_ALEN];
 	u8                              perm_addr[ETH_ALEN];
 	u8                              san_addr[ETH_ALEN];
 	/* prefix for World Wide Node Name (WWNN) */
 	u16                             wwnn_prefix;
 	/* prefix for World Wide Port Name (WWPN) */
 	u16                             wwpn_prefix;
 	u16				max_msix_vectors;
 #define IXGBE_MAX_MTA			128
 	u32				mta_shadow[IXGBE_MAX_MTA];
 	s32                             mc_filter_type;
 	u32                             mcft_size;
 	u32                             vft_size;
 	u32                             num_rar_entries;
 	u32                             rar_highwater;
 	u32				rx_pb_size;
 	u32                             max_tx_queues;
 	u32                             max_rx_queues;
 	u32                             orig_autoc;
 	u32                             cached_autoc;
 	u32                             orig_autoc2;
 	bool                            orig_link_settings_stored;
 	bool                            autotry_restart;
 	u8                              flags;
 	u8				san_mac_rar_index;
 	struct ixgbe_thermal_sensor_data  thermal_sensor_data;
 };
 struct ixgbe_phy_info {
 	struct ixgbe_phy_operations     ops;
 	struct mdio_if_info		mdio;
 	enum ixgbe_phy_type             type;
 	u32                             id;
 	enum ixgbe_sfp_type             sfp_type;
 	bool                            sfp_setup_needed;
 	u32                             revision;
 	enum ixgbe_media_type           media_type;
 	bool                            reset_disable;
 	ixgbe_autoneg_advertised        autoneg_advertised;
 	enum ixgbe_smart_speed          smart_speed;
 	bool                            smart_speed_active;
 	bool                            multispeed_fiber;
 	bool                            reset_if_overtemp;
 };
 #include "ixgbe_mbx.h"
 struct ixgbe_mbx_operations {
 	s32 (*init_params)(struct ixgbe_hw *hw);
 	s32 (*read)(struct ixgbe_hw *, u32 *, u16,  u16);
 	s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16);
 	s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16,  u16);
 	s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16);
 	s32 (*check_for_msg)(struct ixgbe_hw *, u16);
 	s32 (*check_for_ack)(struct ixgbe_hw *, u16);
 	s32 (*check_for_rst)(struct ixgbe_hw *, u16);
 };
 struct ixgbe_mbx_stats {
 	u32 msgs_tx;
 	u32 msgs_rx;
 	u32 acks;
 	u32 reqs;
 	u32 rsts;
 };
 struct ixgbe_mbx_info {
 	struct ixgbe_mbx_operations ops;
 	struct ixgbe_mbx_stats stats;
 	u32 timeout;
 	u32 usec_delay;
 	u32 v2p_mailbox;
 	u16 size;
 };
 struct ixgbe_hw {
 	u8 __iomem			*hw_addr;
 	void				*back;
 	struct ixgbe_mac_info		mac;
 	struct ixgbe_addr_filter_info	addr_ctrl;
 	struct ixgbe_fc_info		fc;
 	struct ixgbe_phy_info		phy;
 	struct ixgbe_eeprom_info	eeprom;
 	struct ixgbe_bus_info		bus;
 	struct ixgbe_mbx_info		mbx;
 	u16				device_id;
 	u16				vendor_id;
 	u16				subsystem_device_id;
 	u16				subsystem_vendor_id;
 	u8				revision_id;
 	bool				adapter_stopped;
 	bool				force_full_reset;
 	bool				allow_unsupported_sfp;
 	bool				mng_fw_enabled;
 	bool				wol_enabled;
 };
 struct ixgbe_info {
 	enum ixgbe_mac_type		mac;
 	s32 				(*get_invariants)(struct ixgbe_hw *);
 	struct ixgbe_mac_operations	*mac_ops;
 	struct ixgbe_eeprom_operations	*eeprom_ops;
 	struct ixgbe_phy_operations	*phy_ops;
 	struct ixgbe_mbx_operations	*mbx_ops;
 };
 /* Error Codes */
 #define IXGBE_ERR_EEPROM                        -1
 #define IXGBE_ERR_EEPROM_CHECKSUM               -2
 #define IXGBE_ERR_PHY                           -3
 #define IXGBE_ERR_CONFIG                        -4
 #define IXGBE_ERR_PARAM                         -5
 #define IXGBE_ERR_MAC_TYPE                      -6
 #define IXGBE_ERR_UNKNOWN_PHY                   -7
 #define IXGBE_ERR_LINK_SETUP                    -8
 #define IXGBE_ERR_ADAPTER_STOPPED               -9
 #define IXGBE_ERR_INVALID_MAC_ADDR              -10
 #define IXGBE_ERR_DEVICE_NOT_SUPPORTED          -11
 #define IXGBE_ERR_MASTER_REQUESTS_PENDING       -12
 #define IXGBE_ERR_INVALID_LINK_SETTINGS         -13
 #define IXGBE_ERR_AUTONEG_NOT_COMPLETE          -14
 #define IXGBE_ERR_RESET_FAILED                  -15
 #define IXGBE_ERR_SWFW_SYNC                     -16
 #define IXGBE_ERR_PHY_ADDR_INVALID              -17
 #define IXGBE_ERR_I2C                           -18
 #define IXGBE_ERR_SFP_NOT_SUPPORTED             -19
 #define IXGBE_ERR_SFP_NOT_PRESENT               -20
 #define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT       -21
 #define IXGBE_ERR_NO_SAN_ADDR_PTR               -22
 #define IXGBE_ERR_FDIR_REINIT_FAILED            -23
 #define IXGBE_ERR_EEPROM_VERSION                -24
 #define IXGBE_ERR_NO_SPACE                      -25
 #define IXGBE_ERR_OVERTEMP                      -26
 #define IXGBE_ERR_FC_NOT_NEGOTIATED             -27
 #define IXGBE_ERR_FC_NOT_SUPPORTED              -28
 #define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE        -30
 #define IXGBE_ERR_PBA_SECTION                   -31
 #define IXGBE_ERR_INVALID_ARGUMENT              -32
 #define IXGBE_ERR_HOST_INTERFACE_COMMAND        -33
 #define IXGBE_NOT_IMPLEMENTED                   0x7FFFFFFF
 #endif /* _IXGBE_TYPE_H_ */