ixgbe: add new media type.

This patch adds support for a new media type fiber_fixed. This is useful to avoid all the SFP+ hot plug support path on devices who's fix fiber need not worry about such things. This patch is needed for a following patch that adds support for "fiber_fixed" devices. v2: cleaned up logging message based on feedback from David Miller Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>

ixgbe: add new media type.
This patch adds support for a new media type fiber_fixed. This is useful to avoid all the SFP+ hot plug support path on devices who's fix fiber need not worry about such things. This patch is needed for a following patch that adds support for "fiber_fixed" devices. v2: cleaned up logging message based on feedback from David Miller Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Don Skidmore · Jeff Kirsher
1 parent 73d80953df
Showing 4 changed files with 95 additions and 7 deletions Side-by-side Diff
drivers/net/ethernet/intel/ixgbe/ixgbe_82599.c
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
drivers/net/ethernet/intel/ixgbe/ixgbe_phy.h
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
@@ -527,6 +527,75 @@
 }
  
 /**
+ *  ixgbe_set_fiber_fixed_speed - Set module link speed for fixed fiber
+ *  @hw: pointer to hardware structure
+ *  @speed: link speed to set
+ *
+ *  We set the module speed differently for fixed fiber.  For other
+ *  multi-speed devices we don't have an error value so here if we
+ *  detect an error we just log it and exit.
+ */
+static void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw,
+					ixgbe_link_speed speed)
+{
+	s32 status;
+	u8 rs, eeprom_data;
+
+	switch (speed) {
+	case IXGBE_LINK_SPEED_10GB_FULL:
+		/* one bit mask same as setting on */
+		rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
+		break;
+	case IXGBE_LINK_SPEED_1GB_FULL:
+		rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
+		break;
+	default:
+		hw_dbg(hw, "Invalid fixed module speed\n");
+		return;
+	}
+
+	/* Set RS0 */
+	status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
+					   IXGBE_I2C_EEPROM_DEV_ADDR2,
+					   &eeprom_data);
+	if (status) {
+		hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
+		goto out;
+	}
+
+	eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
+
+	status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
+					    IXGBE_I2C_EEPROM_DEV_ADDR2,
+					    eeprom_data);
+	if (status) {
+		hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
+		goto out;
+	}
+
+	/* Set RS1 */
+	status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
+					   IXGBE_I2C_EEPROM_DEV_ADDR2,
+					   &eeprom_data);
+	if (status) {
+		hw_dbg(hw, "Failed to read Rx Rate Select RS1\n");
+		goto out;
+	}
+
+	eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
+
+	status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
+					    IXGBE_I2C_EEPROM_DEV_ADDR2,
+					    eeprom_data);
+	if (status) {
+		hw_dbg(hw, "Failed to write Rx Rate Select RS1\n");
+		goto out;
+	}
+out:
+	return;
+}
+
+/**
  *  ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
  *  @hw: pointer to hardware structure
  *  @speed: new link speed
@@ -573,9 +642,14 @@
 			goto out;
  
 		/* Set the module link speed */
-		esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
-		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
-		IXGBE_WRITE_FLUSH(hw);
+		if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
+			ixgbe_set_fiber_fixed_speed(hw,
+					IXGBE_LINK_SPEED_10GB_FULL);
+		} else {
+			esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
+			IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
+			IXGBE_WRITE_FLUSH(hw);
+		}
  
 		/* Allow module to change analog characteristics (1G->10G) */
 		msleep(40);
@@ -625,10 +699,15 @@
 			goto out;
  
 		/* Set the module link speed */
-		esdp_reg &= ~IXGBE_ESDP_SDP5;
-		esdp_reg |= IXGBE_ESDP_SDP5_DIR;
-		IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
-		IXGBE_WRITE_FLUSH(hw);
+		if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
+			ixgbe_set_fiber_fixed_speed(hw,
+						IXGBE_LINK_SPEED_1GB_FULL);
+		} else {
+			esdp_reg &= ~IXGBE_ESDP_SDP5;
+			esdp_reg |= IXGBE_ESDP_SDP5_DIR;
+			IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
+			IXGBE_WRITE_FLUSH(hw);
+		}
  
 		/* Allow module to change analog characteristics (10G->1G) */
 		msleep(40);
@@ -72,6 +72,7 @@
 	bool link_up;
  
 	switch (hw->phy.media_type) {
+	case ixgbe_media_type_fiber_fixed:
 	case ixgbe_media_type_fiber:
 		hw->mac.ops.check_link(hw, &speed, &link_up, false);
 		/* if link is down, assume supported */
@@ -138,6 +139,7 @@
 	 * we link at 10G, the 1G advertisement is harmless and vice versa.
 	 */
 	switch (hw->phy.media_type) {
+	case ixgbe_media_type_fiber_fixed:
 	case ixgbe_media_type_fiber:
 	case ixgbe_media_type_backplane:
 		reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
@@ -2404,6 +2406,7 @@
  
 	switch (hw->phy.media_type) {
 	/* Autoneg flow control on fiber adapters */
+	case ixgbe_media_type_fiber_fixed:
 	case ixgbe_media_type_fiber:
 		if (speed == IXGBE_LINK_SPEED_1GB_FULL)
 			ret_val = ixgbe_fc_autoneg_fiber(hw);
@@ -44,6 +44,8 @@
 #define IXGBE_SFF_CABLE_SPEC_COMP    0x3C
 #define IXGBE_SFF_SFF_8472_SWAP      0x5C
 #define IXGBE_SFF_SFF_8472_COMP      0x5E
+#define IXGBE_SFF_SFF_8472_OSCB	0x6E
+#define IXGBE_SFF_SFF_8472_ESCB	0x76
  
 /* Bitmasks */
 #define IXGBE_SFF_DA_PASSIVE_CABLE           0x4
@@ -54,6 +56,9 @@
 #define IXGBE_SFF_1GBASET_CAPABLE            0x8
 #define IXGBE_SFF_10GBASESR_CAPABLE          0x10
 #define IXGBE_SFF_10GBASELR_CAPABLE          0x20
+#define IXGBE_SFF_SOFT_RS_SELECT_MASK	0x8
+#define IXGBE_SFF_SOFT_RS_SELECT_10G	0x8
+#define IXGBE_SFF_SOFT_RS_SELECT_1G	0x0
 #define IXGBE_SFF_ADDRESSING_MODE	     0x4
 #define IXGBE_I2C_EEPROM_READ_MASK           0x100
 #define IXGBE_I2C_EEPROM_STATUS_MASK         0x3
@@ -2622,6 +2622,7 @@
 enum ixgbe_media_type {
 	ixgbe_media_type_unknown = 0,
 	ixgbe_media_type_fiber,
+	ixgbe_media_type_fiber_fixed,
 	ixgbe_media_type_fiber_lco,
 	ixgbe_media_type_copper,
 	ixgbe_media_type_backplane,
...	...	@@ -527,6 +527,75 @@
527	527	}
528	528
529	529	/**
	530	+ * ixgbe_set_fiber_fixed_speed - Set module link speed for fixed fiber
	531	+ * @hw: pointer to hardware structure
	532	+ * @speed: link speed to set
	533	+ *
	534	+ * We set the module speed differently for fixed fiber. For other
	535	+ * multi-speed devices we don't have an error value so here if we
	536	+ * detect an error we just log it and exit.
	537	+ */
	538	+static void ixgbe_set_fiber_fixed_speed(struct ixgbe_hw *hw,
	539	+ ixgbe_link_speed speed)
	540	+{
	541	+ s32 status;
	542	+ u8 rs, eeprom_data;
	543	+
	544	+ switch (speed) {
	545	+ case IXGBE_LINK_SPEED_10GB_FULL:
	546	+ /* one bit mask same as setting on */
	547	+ rs = IXGBE_SFF_SOFT_RS_SELECT_10G;
	548	+ break;
	549	+ case IXGBE_LINK_SPEED_1GB_FULL:
	550	+ rs = IXGBE_SFF_SOFT_RS_SELECT_1G;
	551	+ break;
	552	+ default:
	553	+ hw_dbg(hw, "Invalid fixed module speed\n");
	554	+ return;
	555	+ }
	556	+
	557	+ /* Set RS0 */
	558	+ status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
	559	+ IXGBE_I2C_EEPROM_DEV_ADDR2,
	560	+ &eeprom_data);
	561	+ if (status) {
	562	+ hw_dbg(hw, "Failed to read Rx Rate Select RS0\n");
	563	+ goto out;
	564	+ }
	565	+
	566	+ eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
	567	+
	568	+ status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_OSCB,
	569	+ IXGBE_I2C_EEPROM_DEV_ADDR2,
	570	+ eeprom_data);
	571	+ if (status) {
	572	+ hw_dbg(hw, "Failed to write Rx Rate Select RS0\n");
	573	+ goto out;
	574	+ }
	575	+
	576	+ /* Set RS1 */
	577	+ status = hw->phy.ops.read_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
	578	+ IXGBE_I2C_EEPROM_DEV_ADDR2,
	579	+ &eeprom_data);
	580	+ if (status) {
	581	+ hw_dbg(hw, "Failed to read Rx Rate Select RS1\n");
	582	+ goto out;
	583	+ }
	584	+
	585	+ eeprom_data = (eeprom_data & ~IXGBE_SFF_SOFT_RS_SELECT_MASK) & rs;
	586	+
	587	+ status = hw->phy.ops.write_i2c_byte(hw, IXGBE_SFF_SFF_8472_ESCB,
	588	+ IXGBE_I2C_EEPROM_DEV_ADDR2,
	589	+ eeprom_data);
	590	+ if (status) {
	591	+ hw_dbg(hw, "Failed to write Rx Rate Select RS1\n");
	592	+ goto out;
	593	+ }
	594	+out:
	595	+ return;
	596	+}
	597	+
	598	+/**
530	599	* ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
531	600	* @hw: pointer to hardware structure
532	601	* @speed: new link speed
...	...	@@ -573,9 +642,14 @@
573	642	goto out;
574	643
575	644	/* Set the module link speed */
576		- esdp_reg \|= (IXGBE_ESDP_SDP5_DIR \| IXGBE_ESDP_SDP5);
577		- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
578		- IXGBE_WRITE_FLUSH(hw);
	645	+ if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
	646	+ ixgbe_set_fiber_fixed_speed(hw,
	647	+ IXGBE_LINK_SPEED_10GB_FULL);
	648	+ } else {
	649	+ esdp_reg \|= (IXGBE_ESDP_SDP5_DIR \| IXGBE_ESDP_SDP5);
	650	+ IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
	651	+ IXGBE_WRITE_FLUSH(hw);
	652	+ }
579	653
580	654	/* Allow module to change analog characteristics (1G->10G) */
581	655	msleep(40);
...	...	@@ -625,10 +699,15 @@
625	699	goto out;
626	700
627	701	/* Set the module link speed */
628		- esdp_reg &= ~IXGBE_ESDP_SDP5;
629		- esdp_reg \|= IXGBE_ESDP_SDP5_DIR;
630		- IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
631		- IXGBE_WRITE_FLUSH(hw);
	702	+ if (hw->phy.media_type == ixgbe_media_type_fiber_fixed) {
	703	+ ixgbe_set_fiber_fixed_speed(hw,
	704	+ IXGBE_LINK_SPEED_1GB_FULL);
	705	+ } else {
	706	+ esdp_reg &= ~IXGBE_ESDP_SDP5;
	707	+ esdp_reg \|= IXGBE_ESDP_SDP5_DIR;
	708	+ IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
	709	+ IXGBE_WRITE_FLUSH(hw);
	710	+ }
632	711
633	712	/* Allow module to change analog characteristics (10G->1G) */
634	713	msleep(40);
...	...	@@ -72,6 +72,7 @@
72	72	bool link_up;
73	73
74	74	switch (hw->phy.media_type) {
	75	+ case ixgbe_media_type_fiber_fixed:
75	76	case ixgbe_media_type_fiber:
76	77	hw->mac.ops.check_link(hw, &speed, &link_up, false);
77	78	/* if link is down, assume supported */
...	...	@@ -138,6 +139,7 @@
138	139	* we link at 10G, the 1G advertisement is harmless and vice versa.
139	140	*/
140	141	switch (hw->phy.media_type) {
	142	+ case ixgbe_media_type_fiber_fixed:
141	143	case ixgbe_media_type_fiber:
142	144	case ixgbe_media_type_backplane:
143	145	reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
...	...	@@ -2404,6 +2406,7 @@
2404	2406
2405	2407	switch (hw->phy.media_type) {
2406	2408	/* Autoneg flow control on fiber adapters */
	2409	+ case ixgbe_media_type_fiber_fixed:
2407	2410	case ixgbe_media_type_fiber:
2408	2411	if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2409	2412	ret_val = ixgbe_fc_autoneg_fiber(hw);
...	...	@@ -44,6 +44,8 @@
44	44	#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
45	45	#define IXGBE_SFF_SFF_8472_SWAP 0x5C
46	46	#define IXGBE_SFF_SFF_8472_COMP 0x5E
	47	+#define IXGBE_SFF_SFF_8472_OSCB 0x6E
	48	+#define IXGBE_SFF_SFF_8472_ESCB 0x76
47	49
48	50	/* Bitmasks */
49	51	#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
...	...	@@ -54,6 +56,9 @@
54	56	#define IXGBE_SFF_1GBASET_CAPABLE 0x8
55	57	#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
56	58	#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
	59	+#define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
	60	+#define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8
	61	+#define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0
57	62	#define IXGBE_SFF_ADDRESSING_MODE 0x4
58	63	#define IXGBE_I2C_EEPROM_READ_MASK 0x100
59	64	#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
...	...	@@ -2622,6 +2622,7 @@
2622	2622	enum ixgbe_media_type {
2623	2623	ixgbe_media_type_unknown = 0,
2624	2624	ixgbe_media_type_fiber,
	2625	+ ixgbe_media_type_fiber_fixed,
2625	2626	ixgbe_media_type_fiber_lco,
2626	2627	ixgbe_media_type_copper,
2627	2628	ixgbe_media_type_backplane,