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Commit 4f71612ee3a1b2d15c8246d926a40c4f7d21cc3b

Authored by Shawn Guo
1 parent 66acaf3f89
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

ARM: imx: fix vf610 enet module clock selection 

The fec/enet driver calculates MDC rate with the formula below.

  ref_freq / ((MII_SPEED + 1) x 2)

The ref_freq here is the fec internal module clock, which is missing
from clk-vf610 clock driver right now.  And clk-vf610 driver mistakenly
supplies RMII clock (50 MHz) as the source to fec.  This results in the
situation that fec driver gets ref_freq as 50 MHz, while physically it
runs at 66 MHz (fec module clock physically sources from ipg which runs
at 66 MHz).  That's why software expects MDC runs at 2.5 MHz, while the
measurement tells it runs at 3.3 MHz.  And this causes the PHY KSZ8041
keeps swithing between Full and Half mode as below.

  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half
  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half
  libphy: 400d0000.etherne:00 - Link is Up - 100/Full
  libphy: 400d0000.etherne:00 - Link is Up - 100/Half

Add the missing module clock for ENET0 and ENET1, and correct the clock
supplying in device tree to fix above issue.

Thanks to Alison Wang <b18965@freescale.com> for debugging the issue.

Signed-off-by: Shawn Guo <shawn.guo@linaro.org>

Showing 3 changed files with 9 additions and 5 deletions Side-by-side Diff

arch/arm/boot/dts/vf610.dtsi
Diff comments   View file @ 4f71612
... ... @@ -442,8 +442,8 @@
442 442 compatible = "fsl,mvf600-fec";
443 443 reg = <0x400d0000 0x1000>;
444 444 interrupts = <0 78 0x04>;
445   - clocks = <&clks VF610_CLK_ENET>,
446   - <&clks VF610_CLK_ENET>,
  445 + clocks = <&clks VF610_CLK_ENET0>,
  446 + <&clks VF610_CLK_ENET0>,
447 447 <&clks VF610_CLK_ENET>;
448 448 clock-names = "ipg", "ahb", "ptp";
449 449 status = "disabled";
... ... @@ -453,8 +453,8 @@
453 453 compatible = "fsl,mvf600-fec";
454 454 reg = <0x400d1000 0x1000>;
455 455 interrupts = <0 79 0x04>;
456   - clocks = <&clks VF610_CLK_ENET>,
457   - <&clks VF610_CLK_ENET>,
  456 + clocks = <&clks VF610_CLK_ENET1>,
  457 + <&clks VF610_CLK_ENET1>,
458 458 <&clks VF610_CLK_ENET>;
459 459 clock-names = "ipg", "ahb", "ptp";
460 460 status = "disabled";
arch/arm/mach-imx/clk-vf610.c
Diff comments   View file @ 4f71612
... ... @@ -183,6 +183,8 @@
183 183 clk[VF610_CLK_ENET_TS_SEL] = imx_clk_mux("enet_ts_sel", CCM_CSCMR2, 0, 3, enet_ts_sels, 7);
184 184 clk[VF610_CLK_ENET] = imx_clk_gate("enet", "enet_sel", CCM_CSCDR1, 24);
185 185 clk[VF610_CLK_ENET_TS] = imx_clk_gate("enet_ts", "enet_ts_sel", CCM_CSCDR1, 23);
  186 + clk[VF610_CLK_ENET0] = imx_clk_gate2("enet0", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(0));
  187 + clk[VF610_CLK_ENET1] = imx_clk_gate2("enet1", "ipg_bus", CCM_CCGR9, CCM_CCGRx_CGn(1));
186 188  
187 189 clk[VF610_CLK_PIT] = imx_clk_gate2("pit", "ipg_bus", CCM_CCGR1, CCM_CCGRx_CGn(7));
188 190  
include/dt-bindings/clock/vf610-clock.h
Diff comments   View file @ 4f71612
... ... @@ -158,7 +158,9 @@
158 158 #define VF610_CLK_GPU_SEL 145
159 159 #define VF610_CLK_GPU_EN 146
160 160 #define VF610_CLK_GPU2D 147
161   -#define VF610_CLK_END 148
  161 +#define VF610_CLK_ENET0 148
  162 +#define VF610_CLK_ENET1 149
  163 +#define VF610_CLK_END 150
162 164  
163 165 #endif /* __DT_BINDINGS_CLOCK_VF610_H */