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Commit 4f8a6b1ab222d08931a36d6770a60cff405968bd

Authored by Stephane Eranian
Committed by Thomas Gleixner
1 parent 54ef34009a
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

i386: i386 add AMD64 Barcelona PMU MSR definitions to msr.h 

[i386] add AMD Barcelona PMU MSR definitions

AK: Not used right now, but will presumably at some point.

[ tglx: arch/x86 adaptation ]

Signed-off-by: Stephane Eranian <eranian@hpl.hp.com>
Signed-off-by: Robert Richter <robert.richter@amd.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

Showing 1 changed file with 25 additions and 11 deletions Side-by-side Diff

include/asm-x86/msr-index.h
Diff comments   View file @ 4f8a6b1
... ... @@ -73,8 +73,32 @@
73 73 #define MSR_P6_EVNTSEL0 0x00000186
74 74 #define MSR_P6_EVNTSEL1 0x00000187
75 75  
76   -/* K7/K8 MSRs. Not complete. See the architecture manual for a more
  76 +/* AMD64 MSRs. Not complete. See the architecture manual for a more
77 77 complete list. */
  78 +
  79 +#define MSR_AMD64_IBSFETCHCTL 0xc0011030
  80 +#define MSR_AMD64_IBSFETCHLINAD 0xc0011031
  81 +#define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032
  82 +#define MSR_AMD64_IBSOPCTL 0xc0011033
  83 +#define MSR_AMD64_IBSOPRIP 0xc0011034
  84 +#define MSR_AMD64_IBSOPDATA 0xc0011035
  85 +#define MSR_AMD64_IBSOPDATA2 0xc0011036
  86 +#define MSR_AMD64_IBSOPDATA3 0xc0011037
  87 +#define MSR_AMD64_IBSDCLINAD 0xc0011038
  88 +#define MSR_AMD64_IBSDCPHYSAD 0xc0011039
  89 +#define MSR_AMD64_IBSCTL 0xc001103a
  90 +
  91 +/* K8 MSRs */
  92 +#define MSR_K8_TOP_MEM1 0xc001001a
  93 +#define MSR_K8_TOP_MEM2 0xc001001d
  94 +#define MSR_K8_SYSCFG 0xc0010010
  95 +#define MSR_K8_HWCR 0xc0010015
  96 +#define MSR_K8_ENABLE_C1E 0xc0010055
  97 +#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
  98 +#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
  99 +#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
  100 +
  101 +/* K7 MSRs */
78 102 #define MSR_K7_EVNTSEL0 0xc0010000
79 103 #define MSR_K7_PERFCTR0 0xc0010004
80 104 #define MSR_K7_EVNTSEL1 0xc0010001
81 105  
82 106  
83 107  
... ... @@ -83,20 +107,10 @@
83 107 #define MSR_K7_PERFCTR2 0xc0010006
84 108 #define MSR_K7_EVNTSEL3 0xc0010003
85 109 #define MSR_K7_PERFCTR3 0xc0010007
86   -#define MSR_K8_TOP_MEM1 0xc001001a
87 110 #define MSR_K7_CLK_CTL 0xc001001b
88   -#define MSR_K8_TOP_MEM2 0xc001001d
89   -#define MSR_K8_SYSCFG 0xc0010010
90   -
91   -#define K8_MTRRFIXRANGE_DRAM_ENABLE 0x00040000 /* MtrrFixDramEn bit */
92   -#define K8_MTRRFIXRANGE_DRAM_MODIFY 0x00080000 /* MtrrFixDramModEn bit */
93   -#define K8_MTRR_RDMEM_WRMEM_MASK 0x18181818 /* Mask: RdMem|WrMem */
94   -
95 111 #define MSR_K7_HWCR 0xc0010015
96   -#define MSR_K8_HWCR 0xc0010015
97 112 #define MSR_K7_FID_VID_CTL 0xc0010041
98 113 #define MSR_K7_FID_VID_STATUS 0xc0010042
99   -#define MSR_K8_ENABLE_C1E 0xc0010055
100 114  
101 115 /* K6 MSRs */
102 116 #define MSR_K6_EFER 0xc0000080