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Commit 5026dafa177133f9b6bf0000dfc98596fa4ad2fd

Authored by Chris Metcalf
1 parent 02b67e0954
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

tile PCI RC: support PCIe TRIO 0 MAC 0 on Gx72 system 

On Tilera Gx72 systems, the logic for figuring out whether
a given port is root complex is slightly different.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

Showing 2 changed files with 33 additions and 3 deletions Side-by-side Diff

arch/tile/include/hv/drv_trio_intf.h
Diff comments   View file @ 5026daf
... ... @@ -168,6 +168,9 @@
168 168 struct pcie_trio_ports_property
169 169 {
170 170 struct pcie_port_property ports[TILEGX_TRIO_PCIES];
  171 +
  172 + /** Set if this TRIO belongs to a Gx72 device. */
  173 + uint8_t is_gx72;
171 174 };
172 175  
173 176 /* Flags indicating traffic class. */
arch/tile/kernel/pci_gx.c
Diff comments   View file @ 5026daf
... ... @@ -436,9 +436,26 @@
436 436  
437 437 /*
438 438 * Now determine which PCIe ports are configured to operate in RC
439   - * mode. To use a port, it must be allowed to be in RC mode by the
  439 + * mode. There is a differece in the port configuration capability
  440 + * between the Gx36 and Gx72 devices.
  441 + *
  442 + * The Gx36 has configuration capability for each of the 3 PCIe
  443 + * interfaces (disable, auto endpoint, auto RC, etc.).
  444 + * On the Gx72, you can only select one of the 3 PCIe interfaces per
  445 + * TRIO to train automatically. Further, the allowable training modes
  446 + * are reduced to four options (auto endpoint, auto RC, stream x1,
  447 + * stream x4).
  448 + *
  449 + * For Gx36 ports, it must be allowed to be in RC mode by the
440 450 * Board Information Block, and the hardware strapping pins must be
441 451 * set to RC mode.
  452 + *
  453 + * For Gx72 ports, the port will operate in RC mode if either of the
  454 + * following is true:
  455 + * 1. It is allowed to be in RC mode by the Board Information Block,
  456 + * and the BIB doesn't allow the EP mode.
  457 + * 2. It is allowed to be in either the RC or the EP mode by the BIB,
  458 + * and the hardware strapping pin is set to RC mode.
442 459 */
443 460 for (i = 0; i < TILEGX_NUM_TRIO; i++) {
444 461 gxio_trio_context_t *context = &trio_contexts[i];
... ... @@ -447,8 +464,18 @@
447 464 continue;
448 465  
449 466 for (j = 0; j < TILEGX_TRIO_PCIES; j++) {
450   - if (pcie_ports[i].ports[j].allow_rc &&
451   - strapped_for_rc(context, j)) {
  467 + int is_rc = 0;
  468 +
  469 + if (pcie_ports[i].is_gx72 &&
  470 + pcie_ports[i].ports[j].allow_rc) {
  471 + if (!pcie_ports[i].ports[j].allow_ep ||
  472 + strapped_for_rc(context, j))
  473 + is_rc = 1;
  474 + } else if (pcie_ports[i].ports[j].allow_rc &&
  475 + strapped_for_rc(context, j)) {
  476 + is_rc = 1;
  477 + }
  478 + if (is_rc) {
452 479 pcie_rc[i][j] = 1;
453 480 num_rc_controllers++;
454 481 }