Merge remote branch 'kumar/next' into merge

Benjamin Herrenschmidt
2 parents 12fcdba1b7 b49d81ded4
Showing 9 changed files Side-by-side Diff
arch/powerpc/boot/dts/mpc8308rdb.dts
arch/powerpc/boot/dts/p1022ds.dts
arch/powerpc/include/asm/immap_qe.h
arch/powerpc/include/asm/reg.h
arch/powerpc/include/asm/reg_booke.h
arch/powerpc/kernel/cpu_setup_fsl_booke.S
arch/powerpc/platforms/83xx/mpc83xx.h
arch/powerpc/platforms/83xx/usb.c
arch/powerpc/sysdev/fsl_rio.c
@@ -109,7 +109,7 @@
 		#address-cells = <1>;
 		#size-cells = <1>;
 		device_type = "soc";
-		compatible = "fsl,mpc8315-immr", "simple-bus";
+		compatible = "fsl,mpc8308-immr", "simple-bus";
 		ranges = <0 0xe0000000 0x00100000>;
 		reg = <0xe0000000 0x00000200>;
 		bus-frequency = <0>;
@@ -291,13 +291,13 @@
 			ranges = <0x0 0xc100 0x200>;
 			cell-index = <1>;
 			dma00: dma-channel@0 {
-				compatible = "fsl,eloplus-dma-channel";
+				compatible = "fsl,ssi-dma-channel";
 				reg = <0x0 0x80>;
 				cell-index = <0>;
 				interrupts = <76 2>;
 			};
 			dma01: dma-channel@80 {
-				compatible = "fsl,eloplus-dma-channel";
+				compatible = "fsl,ssi-dma-channel";
 				reg = <0x80 0x80>;
 				cell-index = <1>;
 				interrupts = <77 2>;
@@ -467,13 +467,22 @@
 extern struct qe_immap __iomem *qe_immr;
 extern phys_addr_t get_qe_base(void);
  
-static inline unsigned long immrbar_virt_to_phys(void *address)
+/*
+ * Returns the offset within the QE address space of the given pointer.
+ *
+ * Note that the QE does not support 36-bit physical addresses, so if
+ * get_qe_base() returns a number above 4GB, the caller will probably fail.
+ */
+static inline phys_addr_t immrbar_virt_to_phys(void *address)
 {
-	if ( ((u32)address >= (u32)qe_immr) &&
-			((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
-		return (unsigned long)(address - (u32)qe_immr +
-				(u32)get_qe_base());
-	return (unsigned long)virt_to_phys(address);
+	void *q = (void *)qe_immr;
+
+	/* Is it a MURAM address? */
+	if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
+		return get_qe_base() + (address - q);
+
+	/* It's an address returned by kmalloc */
+	return virt_to_phys(address);
 }
  
 #endif /* __KERNEL__ */
@@ -283,6 +283,7 @@
 #define HID0_NOPTI	(1<<0)		/* No-op dcbt and dcbst instr. */
  
 #define SPRN_HID1	0x3F1		/* Hardware Implementation Register 1 */
+#ifdef CONFIG_6xx
 #define HID1_EMCP	(1<<31)		/* 7450 Machine Check Pin Enable */
 #define HID1_DFS	(1<<22)		/* 7447A Dynamic Frequency Scaling */
 #define HID1_PC0	(1<<16)		/* 7450 PLL_CFG[0] */
@@ -292,6 +293,7 @@
 #define HID1_SYNCBE	(1<<11)		/* 7450 ABE for sync, eieio */
 #define HID1_ABE	(1<<10)		/* 7450 Address Broadcast Enable */
 #define HID1_PS		(1<<16)		/* 750FX PLL selection */
+#endif
 #define SPRN_HID2	0x3F8		/* Hardware Implementation Register 2 */
 #define SPRN_HID2_GEKKO	0x398		/* Gekko HID2 Register */
 #define SPRN_IABR	0x3F2	/* Instruction Address Breakpoint Register */
@@ -246,6 +246,20 @@
 					store or cache line push */
 #endif
  
+/* Bit definitions for the HID1 */
+#ifdef CONFIG_E500
+/* e500v1/v2 */
+#define HID1_PLL_CFG_MASK 0xfc000000	/* PLL_CFG input pins */
+#define HID1_RFXE	0x00020000	/* Read fault exception enable */
+#define HID1_R1DPE	0x00008000	/* R1 data bus parity enable */
+#define HID1_R2DPE	0x00004000	/* R2 data bus parity enable */
+#define HID1_ASTME	0x00002000	/* Address bus streaming mode enable */
+#define HID1_ABE	0x00001000	/* Address broadcast enable */
+#define HID1_MPXTT	0x00000400	/* MPX re-map transfer type */
+#define HID1_ATS	0x00000080	/* Atomic status */
+#define HID1_MID_MASK	0x0000000f	/* MID input pins */
+#endif
+
 /* Bit definitions for the DBSR. */
 /*
  * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
@@ -64,6 +64,12 @@
 	bl	__e500_icache_setup
 	bl	__e500_dcache_setup
 	bl	__setup_e500_ivors
+#ifdef CONFIG_RAPIDIO
+	/* Ensure that RFXE is set */
+	mfspr	r3,SPRN_HID1
+	oris	r3,r3,HID1_RFXE@h
+	mtspr	SPRN_HID1,r3
+#endif
 	mtlr	r4
 	blr
 _GLOBAL(__setup_cpu_e500mc)
@@ -35,6 +35,8 @@
  
 /* system i/o configuration register high */
 #define MPC83XX_SICRH_OFFS         0x118
+#define MPC8308_SICRH_USB_MASK     0x000c0000
+#define MPC8308_SICRH_USB_ULPI     0x00040000
 #define MPC834X_SICRH_USB_UTMI     0x00020000
 #define MPC831X_SICRH_USB_MASK     0x000000e0
 #define MPC831X_SICRH_USB_ULPI     0x000000a0
@@ -127,7 +127,8 @@
  
 	/* Configure clock */
 	immr_node = of_get_parent(np);
-	if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
+	if (immr_node && (of_device_is_compatible(immr_node, "fsl,mpc8315-immr") ||
+			of_device_is_compatible(immr_node, "fsl,mpc8308-immr")))
 		clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
 		                MPC8315_SCCR_USB_MASK,
 		                MPC8315_SCCR_USB_DRCM_01);
@@ -138,7 +139,11 @@
  
 	/* Configure pin mux for ULPI.  There is no pin mux for UTMI */
 	if (prop && !strcmp(prop, "ulpi")) {
-		if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) {
+		if (of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) {
+			clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
+					MPC8308_SICRH_USB_MASK,
+					MPC8308_SICRH_USB_ULPI);
+		} else if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) {
 			clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
 					MPC8315_SICRL_USB_MASK,
 					MPC8315_SICRL_USB_ULPI);
@@ -173,6 +178,9 @@
 		     !strcmp(prop, "utmi"))) {
 		u32 refsel;
  
+		if (of_device_is_compatible(immr_node, "fsl,mpc8308-immr"))
+			goto out;
+
 		if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
 			refsel = CONTROL_REFSEL_24MHZ;
 		else
@@ -186,9 +194,11 @@
 		temp = CONTROL_PHY_CLK_SEL_ULPI;
 #ifdef CONFIG_USB_OTG
 		/* Set OTG_PORT */
-		dr_mode = of_get_property(np, "dr_mode", NULL);
-		if (dr_mode && !strcmp(dr_mode, "otg"))
-			temp |= CONTROL_OTG_PORT;
+		if (!of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) {
+			dr_mode = of_get_property(np, "dr_mode", NULL);
+			if (dr_mode && !strcmp(dr_mode, "otg"))
+				temp |= CONTROL_OTG_PORT;
+		}
 #endif /* CONFIG_USB_OTG */
 		out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, temp);
 	} else {
@@ -196,6 +206,7 @@
 		ret = -EINVAL;
 	}
  
+out:
 	iounmap(usb_regs);
 	of_node_put(np);
 	return ret;
@@ -1555,8 +1555,6 @@
 	saved_mcheck_exception = ppc_md.machine_check_exception;
 	ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
 #endif
-	/* Ensure that RFXE is set */
-	mtspr(SPRN_HID1, (mfspr(SPRN_HID1) | 0x20000));
  
 	return 0;
 err:
...	...	@@ -109,7 +109,7 @@
109	109	#address-cells = <1>;
110	110	#size-cells = <1>;
111	111	device_type = "soc";
112		- compatible = "fsl,mpc8315-immr", "simple-bus";
	112	+ compatible = "fsl,mpc8308-immr", "simple-bus";
113	113	ranges = <0 0xe0000000 0x00100000>;
114	114	reg = <0xe0000000 0x00000200>;
115	115	bus-frequency = <0>;
...	...	@@ -291,13 +291,13 @@
291	291	ranges = <0x0 0xc100 0x200>;
292	292	cell-index = <1>;
293	293	dma00: dma-channel@0 {
294		- compatible = "fsl,eloplus-dma-channel";
	294	+ compatible = "fsl,ssi-dma-channel";
295	295	reg = <0x0 0x80>;
296	296	cell-index = <0>;
297	297	interrupts = <76 2>;
298	298	};
299	299	dma01: dma-channel@80 {
300		- compatible = "fsl,eloplus-dma-channel";
	300	+ compatible = "fsl,ssi-dma-channel";
301	301	reg = <0x80 0x80>;
302	302	cell-index = <1>;
303	303	interrupts = <77 2>;
...	...	@@ -467,13 +467,22 @@
467	467	extern struct qe_immap __iomem *qe_immr;
468	468	extern phys_addr_t get_qe_base(void);
469	469
470		-static inline unsigned long immrbar_virt_to_phys(void *address)
	470	+/*
	471	+ * Returns the offset within the QE address space of the given pointer.
	472	+ *
	473	+ * Note that the QE does not support 36-bit physical addresses, so if
	474	+ * get_qe_base() returns a number above 4GB, the caller will probably fail.
	475	+ */
	476	+static inline phys_addr_t immrbar_virt_to_phys(void *address)
471	477	{
472		- if ( ((u32)address >= (u32)qe_immr) &&
473		- ((u32)address < ((u32)qe_immr + QE_IMMAP_SIZE)) )
474		- return (unsigned long)(address - (u32)qe_immr +
475		- (u32)get_qe_base());
476		- return (unsigned long)virt_to_phys(address);
	478	+ void q = (void )qe_immr;
	479	+
	480	+ /* Is it a MURAM address? */
	481	+ if ((address >= q) && (address < (q + QE_IMMAP_SIZE)))
	482	+ return get_qe_base() + (address - q);
	483	+
	484	+ /* It's an address returned by kmalloc */
	485	+ return virt_to_phys(address);
477	486	}
478	487
479	488	#endif /* __KERNEL__ */
...	...	@@ -283,6 +283,7 @@
283	283	#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
284	284
285	285	#define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
	286	+#ifdef CONFIG_6xx
286	287	#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
287	288	#define HID1_DFS (1<<22) /* 7447A Dynamic Frequency Scaling */
288	289	#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
...	...	@@ -292,6 +293,7 @@
292	293	#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
293	294	#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
294	295	#define HID1_PS (1<<16) /* 750FX PLL selection */
	296	+#endif
295	297	#define SPRN_HID2 0x3F8 /* Hardware Implementation Register 2 */
296	298	#define SPRN_HID2_GEKKO 0x398 /* Gekko HID2 Register */
297	299	#define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
...	...	@@ -246,6 +246,20 @@
246	246	store or cache line push */
247	247	#endif
248	248
	249	+/* Bit definitions for the HID1 */
	250	+#ifdef CONFIG_E500
	251	+/* e500v1/v2 */
	252	+#define HID1_PLL_CFG_MASK 0xfc000000 /* PLL_CFG input pins */
	253	+#define HID1_RFXE 0x00020000 /* Read fault exception enable */
	254	+#define HID1_R1DPE 0x00008000 /* R1 data bus parity enable */
	255	+#define HID1_R2DPE 0x00004000 /* R2 data bus parity enable */
	256	+#define HID1_ASTME 0x00002000 /* Address bus streaming mode enable */
	257	+#define HID1_ABE 0x00001000 /* Address broadcast enable */
	258	+#define HID1_MPXTT 0x00000400 /* MPX re-map transfer type */
	259	+#define HID1_ATS 0x00000080 /* Atomic status */
	260	+#define HID1_MID_MASK 0x0000000f /* MID input pins */
	261	+#endif
	262	+
249	263	/* Bit definitions for the DBSR. */
250	264	/*
251	265	* DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
...	...	@@ -64,6 +64,12 @@
64	64	bl __e500_icache_setup
65	65	bl __e500_dcache_setup
66	66	bl __setup_e500_ivors
	67	+#ifdef CONFIG_RAPIDIO
	68	+ /* Ensure that RFXE is set */
	69	+ mfspr r3,SPRN_HID1
	70	+ oris r3,r3,HID1_RFXE@h
	71	+ mtspr SPRN_HID1,r3
	72	+#endif
67	73	mtlr r4
68	74	blr
69	75	_GLOBAL(__setup_cpu_e500mc)
...	...	@@ -35,6 +35,8 @@
35	35
36	36	/* system i/o configuration register high */
37	37	#define MPC83XX_SICRH_OFFS 0x118
	38	+#define MPC8308_SICRH_USB_MASK 0x000c0000
	39	+#define MPC8308_SICRH_USB_ULPI 0x00040000
38	40	#define MPC834X_SICRH_USB_UTMI 0x00020000
39	41	#define MPC831X_SICRH_USB_MASK 0x000000e0
40	42	#define MPC831X_SICRH_USB_ULPI 0x000000a0
...	...	@@ -127,7 +127,8 @@
127	127
128	128	/* Configure clock */
129	129	immr_node = of_get_parent(np);
130		- if (immr_node && of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
	130	+ if (immr_node && (of_device_is_compatible(immr_node, "fsl,mpc8315-immr") \|\|
	131	+ of_device_is_compatible(immr_node, "fsl,mpc8308-immr")))
131	132	clrsetbits_be32(immap + MPC83XX_SCCR_OFFS,
132	133	MPC8315_SCCR_USB_MASK,
133	134	MPC8315_SCCR_USB_DRCM_01);
...	...	@@ -138,7 +139,11 @@
138	139
139	140	/* Configure pin mux for ULPI. There is no pin mux for UTMI */
140	141	if (prop && !strcmp(prop, "ulpi")) {
141		- if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) {
	142	+ if (of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) {
	143	+ clrsetbits_be32(immap + MPC83XX_SICRH_OFFS,
	144	+ MPC8308_SICRH_USB_MASK,
	145	+ MPC8308_SICRH_USB_ULPI);
	146	+ } else if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr")) {
142	147	clrsetbits_be32(immap + MPC83XX_SICRL_OFFS,
143	148	MPC8315_SICRL_USB_MASK,
144	149	MPC8315_SICRL_USB_ULPI);
...	...	@@ -173,6 +178,9 @@
173	178	!strcmp(prop, "utmi"))) {
174	179	u32 refsel;
175	180
	181	+ if (of_device_is_compatible(immr_node, "fsl,mpc8308-immr"))
	182	+ goto out;
	183	+
176	184	if (of_device_is_compatible(immr_node, "fsl,mpc8315-immr"))
177	185	refsel = CONTROL_REFSEL_24MHZ;
178	186	else
...	...	@@ -186,9 +194,11 @@
186	194	temp = CONTROL_PHY_CLK_SEL_ULPI;
187	195	#ifdef CONFIG_USB_OTG
188	196	/* Set OTG_PORT */
189		- dr_mode = of_get_property(np, "dr_mode", NULL);
190		- if (dr_mode && !strcmp(dr_mode, "otg"))
191		- temp \|= CONTROL_OTG_PORT;
	197	+ if (!of_device_is_compatible(immr_node, "fsl,mpc8308-immr")) {
	198	+ dr_mode = of_get_property(np, "dr_mode", NULL);
	199	+ if (dr_mode && !strcmp(dr_mode, "otg"))
	200	+ temp \|= CONTROL_OTG_PORT;
	201	+ }
192	202	#endif /* CONFIG_USB_OTG */
193	203	out_be32(usb_regs + FSL_USB2_CONTROL_OFFS, temp);
194	204	} else {
...	...	@@ -196,6 +206,7 @@
196	206	ret = -EINVAL;
197	207	}
198	208
	209	+out:
199	210	iounmap(usb_regs);
200	211	of_node_put(np);
201	212	return ret;
...	...	@@ -1555,8 +1555,6 @@
1555	1555	saved_mcheck_exception = ppc_md.machine_check_exception;
1556	1556	ppc_md.machine_check_exception = fsl_rio_mcheck_exception;
1557	1557	#endif
1558		- /* Ensure that RFXE is set */
1559		- mtspr(SPRN_HID1, (mfspr(SPRN_HID1) \| 0x20000));
1560	1558
1561	1559	return 0;
1562	1560	err: