Commit 52604b1ffabac61eb07cce711f18e18ac74fbeae
Committed by
Daniel Vetter
Daniel Vetter
1 parent
2f63315692
Exists in
smarc-imx_3.14.28_1.0.0_ga
and in
1 other branch
drm: Added SDP and VSC structures for handling PSR for eDP
SDP header and SDP VSC header as per eDP 1.3 spec, section 3.5,
chapter "PSR Secondary Data Package Support".
v2: Modified and corrected the structures to be more in line for
kernel coding guidelines and rebased the code on Paulo's DP patchset
v3: removing unecessary identation at DP_RECEIVER_CAP_SIZE
v4: moving them to include/drm/drm_dp_helper.h and also already
icluding EDP_PSR_RECEIVER_CAP_SIZE to add everything needed
for PSR at once at drm_dp_helper.h
v5: Fix SDP VSC header and identation by (Paulo Zanoni) and
remove i915 from title (Daniel Vetter)
v6: Fix spec version and move comments from code to commit message
since numbers might change in the future (by Paulo Zanoni).
CC: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Sateesh Kavuri <sateesh.kavuri@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.kumar@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Showing 1 changed file with 30 additions and 1 deletions Side-by-side Diff
include/drm/drm_dp_helper.h
| ... | ... | @@ -342,12 +342,41 @@ |
| 342 | 342 | u8 drm_dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE], |
| 343 | 343 | int lane); |
| 344 | 344 | |
| 345 | -#define DP_RECEIVER_CAP_SIZE 0xf | |
| 345 | +#define DP_RECEIVER_CAP_SIZE 0xf | |
| 346 | +#define EDP_PSR_RECEIVER_CAP_SIZE 2 | |
| 347 | + | |
| 346 | 348 | void drm_dp_link_train_clock_recovery_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| 347 | 349 | void drm_dp_link_train_channel_eq_delay(u8 dpcd[DP_RECEIVER_CAP_SIZE]); |
| 348 | 350 | |
| 349 | 351 | u8 drm_dp_link_rate_to_bw_code(int link_rate); |
| 350 | 352 | int drm_dp_bw_code_to_link_rate(u8 link_bw); |
| 353 | + | |
| 354 | +struct edp_sdp_header { | |
| 355 | + u8 HB0; /* Secondary Data Packet ID */ | |
| 356 | + u8 HB1; /* Secondary Data Packet Type */ | |
| 357 | + u8 HB2; /* 7:5 reserved, 4:0 revision number */ | |
| 358 | + u8 HB3; /* 7:5 reserved, 4:0 number of valid data bytes */ | |
| 359 | +} __packed; | |
| 360 | + | |
| 361 | +#define EDP_SDP_HEADER_REVISION_MASK 0x1F | |
| 362 | +#define EDP_SDP_HEADER_VALID_PAYLOAD_BYTES 0x1F | |
| 363 | + | |
| 364 | +struct edp_vsc_psr { | |
| 365 | + struct edp_sdp_header sdp_header; | |
| 366 | + u8 DB0; /* Stereo Interface */ | |
| 367 | + u8 DB1; /* 0 - PSR State; 1 - Update RFB; 2 - CRC Valid */ | |
| 368 | + u8 DB2; /* CRC value bits 7:0 of the R or Cr component */ | |
| 369 | + u8 DB3; /* CRC value bits 15:8 of the R or Cr component */ | |
| 370 | + u8 DB4; /* CRC value bits 7:0 of the G or Y component */ | |
| 371 | + u8 DB5; /* CRC value bits 15:8 of the G or Y component */ | |
| 372 | + u8 DB6; /* CRC value bits 7:0 of the B or Cb component */ | |
| 373 | + u8 DB7; /* CRC value bits 15:8 of the B or Cb component */ | |
| 374 | + u8 DB8_31[24]; /* Reserved */ | |
| 375 | +} __packed; | |
| 376 | + | |
| 377 | +#define EDP_VSC_PSR_STATE_ACTIVE (1<<0) | |
| 378 | +#define EDP_VSC_PSR_UPDATE_RFB (1<<1) | |
| 379 | +#define EDP_VSC_PSR_CRC_VALUES_VALID (1<<2) | |
| 351 | 380 | |
| 352 | 381 | static inline int |
| 353 | 382 | drm_dp_max_link_rate(u8 dpcd[DP_RECEIVER_CAP_SIZE]) |