ixgbe: fix for 82598 Si errata causing buffer overflow

The failure happens when an interrupt occurs and the driver is reading EICR. This read will cause a clear-by-read which leads to two TLP being inserted in the PCIe retry buffer leading to an overflow of the buffer and corruption of TLPs. The solution is different depending where the reading of EICR takes place. For ixgbe_msix_lsc() since we are in MSIX mode and know OCD is enabled a clear-by-write is done instead of the normal clear-by-read. For ixgbe_intr() 0xffffffff is written to EIMC before the read, masking the interrupts. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Acked-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>

ixgbe: fix for 82598 Si errata causing buffer overflow
The failure happens when an interrupt occurs and the driver is reading EICR. This read will cause a clear-by-read which leads to two TLP being inserted in the PCIe retry buffer leading to an overflow of the buffer and corruption of TLPs. The solution is different depending where the reading of EICR takes place. For ixgbe_msix_lsc() since we are in MSIX mode and know OCD is enabled a clear-by-write is done instead of the normal clear-by-read. For ixgbe_intr() 0xffffffff is written to EIMC before the read, masking the interrupts. Signed-off-by: Don Skidmore <donald.c.skidmore@intel.com> Acked-by: Peter P Waskiewicz Jr <peter.p.waskiewicz.jr@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Don Skidmore · David S. Miller
1 parent cd4d8fdad1
Showing 1 changed file with 16 additions and 1 deletions Side-by-side Diff
drivers/net/ixgbe/ixgbe_main.c
@@ -936,8 +936,17 @@
 	struct net_device *netdev = data;
 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
 	struct ixgbe_hw *hw = &adapter->hw;
-	u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
+	u32 eicr;
  
+	/*
+	 * Workaround for Silicon errata.  Use clear-by-write instead
+	 * of clear-by-read.  Reading with EICS will return the
+	 * interrupt causes without clearing, which later be done
+	 * with the write to EICR.
+	 */
+	eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
+	IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
+
 	if (eicr & IXGBE_EICR_LSC)
 		ixgbe_check_lsc(adapter);
  
@@ -1354,6 +1363,12 @@
 	struct ixgbe_adapter *adapter = netdev_priv(netdev);
 	struct ixgbe_hw *hw = &adapter->hw;
 	u32 eicr;
+
+	/*
+	 * Workaround for silicon errata.  Mask the interrupts
+	 * before the read of EICR.
+	 */
+	IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
  
 	/* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
 	 * therefore no explict interrupt disable is necessary */
...	...	@@ -936,8 +936,17 @@
936	936	struct net_device *netdev = data;
937	937	struct ixgbe_adapter *adapter = netdev_priv(netdev);
938	938	struct ixgbe_hw *hw = &adapter->hw;
939		- u32 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
	939	+ u32 eicr;
940	940
	941	+ /*
	942	+ * Workaround for Silicon errata. Use clear-by-write instead
	943	+ * of clear-by-read. Reading with EICS will return the
	944	+ * interrupt causes without clearing, which later be done
	945	+ * with the write to EICR.
	946	+ */
	947	+ eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
	948	+ IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
	949	+
941	950	if (eicr & IXGBE_EICR_LSC)
942	951	ixgbe_check_lsc(adapter);
943	952
...	...	@@ -1354,6 +1363,12 @@
1354	1363	struct ixgbe_adapter *adapter = netdev_priv(netdev);
1355	1364	struct ixgbe_hw *hw = &adapter->hw;
1356	1365	u32 eicr;
	1366	+
	1367	+ /*
	1368	+ * Workaround for silicon errata. Mask the interrupts
	1369	+ * before the read of EICR.
	1370	+ */
	1371	+ IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1357	1372
1358	1373	/* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1359	1374	* therefore no explict interrupt disable is necessary */