Doug / smarc-fsl-linux-kernel

Download as
Browse Code ยป

Commit 55bf75b7dd8ec875d048824f3cdecf8254e292e5

Authored by Michel Stempin
Committed by Artem Bityutskiy
1 parent 62116e5171
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

mtd: chips: Add support for GigaDevice GD25Q32/GD25Q64 SPI Flash in m25p80.c 

Add support for GigaDevice GD25Q32 32 Mbit (4 MB) SPI Flash (see datasheet:
http://www.gigadevice.com/UserFiles/GD25Q32_Rev0.2(1).pdf) used in Hame MPR-A1
and clones, and for GigaDevice GD25Q64 64 Mbit (8 MB) SPI Flash used in
Hame MPR-A2 devices (datasheet: http://www.gigadevice.com/UserFiles/GD25Q64.pdf).

Signed-off-by: Michel Stempin <michel.stempin@wanadoo.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>

Showing 1 changed file with 4 additions and 0 deletions Inline Diff

drivers/mtd/devices/m25p80.c
Diff comments   View file @ 55bf75b
1 /* 1 /*
2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips 2 * MTD SPI driver for ST M25Pxx (and similar) serial flash chips
3 * 3 *
4 * Author: Mike Lavender, mike@steroidmicros.com 4 * Author: Mike Lavender, mike@steroidmicros.com
5 * 5 *
6 * Copyright (c) 2005, Intec Automation Inc. 6 * Copyright (c) 2005, Intec Automation Inc.
7 * 7 *
8 * Some parts are based on lart.c by Abraham Van Der Merwe 8 * Some parts are based on lart.c by Abraham Van Der Merwe
9 * 9 *
10 * Cleaned up and generalized based on mtd_dataflash.c 10 * Cleaned up and generalized based on mtd_dataflash.c
11 * 11 *
12 * This code is free software; you can redistribute it and/or modify 12 * This code is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as 13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation. 14 * published by the Free Software Foundation.
15 * 15 *
16 */ 16 */
17 17
18 #include <linux/init.h> 18 #include <linux/init.h>
19 #include <linux/err.h> 19 #include <linux/err.h>
20 #include <linux/errno.h> 20 #include <linux/errno.h>
21 #include <linux/module.h> 21 #include <linux/module.h>
22 #include <linux/device.h> 22 #include <linux/device.h>
23 #include <linux/interrupt.h> 23 #include <linux/interrupt.h>
24 #include <linux/mutex.h> 24 #include <linux/mutex.h>
25 #include <linux/math64.h> 25 #include <linux/math64.h>
26 #include <linux/slab.h> 26 #include <linux/slab.h>
27 #include <linux/sched.h> 27 #include <linux/sched.h>
28 #include <linux/mod_devicetable.h> 28 #include <linux/mod_devicetable.h>
29 29
30 #include <linux/mtd/cfi.h> 30 #include <linux/mtd/cfi.h>
31 #include <linux/mtd/mtd.h> 31 #include <linux/mtd/mtd.h>
32 #include <linux/mtd/partitions.h> 32 #include <linux/mtd/partitions.h>
33 #include <linux/of_platform.h> 33 #include <linux/of_platform.h>
34 34
35 #include <linux/spi/spi.h> 35 #include <linux/spi/spi.h>
36 #include <linux/spi/flash.h> 36 #include <linux/spi/flash.h>
37 37
38 /* Flash opcodes. */ 38 /* Flash opcodes. */
39 #define OPCODE_WREN 0x06 /* Write enable */ 39 #define OPCODE_WREN 0x06 /* Write enable */
40 #define OPCODE_RDSR 0x05 /* Read status register */ 40 #define OPCODE_RDSR 0x05 /* Read status register */
41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */ 41 #define OPCODE_WRSR 0x01 /* Write status register 1 byte */
42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */ 42 #define OPCODE_NORM_READ 0x03 /* Read data bytes (low frequency) */
43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */ 43 #define OPCODE_FAST_READ 0x0b /* Read data bytes (high frequency) */
44 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */ 44 #define OPCODE_PP 0x02 /* Page program (up to 256 bytes) */
45 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */ 45 #define OPCODE_BE_4K 0x20 /* Erase 4KiB block */
46 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */ 46 #define OPCODE_BE_32K 0x52 /* Erase 32KiB block */
47 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */ 47 #define OPCODE_CHIP_ERASE 0xc7 /* Erase whole flash chip */
48 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */ 48 #define OPCODE_SE 0xd8 /* Sector erase (usually 64KiB) */
49 #define OPCODE_RDID 0x9f /* Read JEDEC ID */ 49 #define OPCODE_RDID 0x9f /* Read JEDEC ID */
50 50
51 /* Used for SST flashes only. */ 51 /* Used for SST flashes only. */
52 #define OPCODE_BP 0x02 /* Byte program */ 52 #define OPCODE_BP 0x02 /* Byte program */
53 #define OPCODE_WRDI 0x04 /* Write disable */ 53 #define OPCODE_WRDI 0x04 /* Write disable */
54 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */ 54 #define OPCODE_AAI_WP 0xad /* Auto address increment word program */
55 55
56 /* Used for Macronix flashes only. */ 56 /* Used for Macronix flashes only. */
57 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */ 57 #define OPCODE_EN4B 0xb7 /* Enter 4-byte mode */
58 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */ 58 #define OPCODE_EX4B 0xe9 /* Exit 4-byte mode */
59 59
60 /* Used for Spansion flashes only. */ 60 /* Used for Spansion flashes only. */
61 #define OPCODE_BRWR 0x17 /* Bank register write */ 61 #define OPCODE_BRWR 0x17 /* Bank register write */
62 62
63 /* Status Register bits. */ 63 /* Status Register bits. */
64 #define SR_WIP 1 /* Write in progress */ 64 #define SR_WIP 1 /* Write in progress */
65 #define SR_WEL 2 /* Write enable latch */ 65 #define SR_WEL 2 /* Write enable latch */
66 /* meaning of other SR_* bits may differ between vendors */ 66 /* meaning of other SR_* bits may differ between vendors */
67 #define SR_BP0 4 /* Block protect 0 */ 67 #define SR_BP0 4 /* Block protect 0 */
68 #define SR_BP1 8 /* Block protect 1 */ 68 #define SR_BP1 8 /* Block protect 1 */
69 #define SR_BP2 0x10 /* Block protect 2 */ 69 #define SR_BP2 0x10 /* Block protect 2 */
70 #define SR_SRWD 0x80 /* SR write protect */ 70 #define SR_SRWD 0x80 /* SR write protect */
71 71
72 /* Define max times to check status register before we give up. */ 72 /* Define max times to check status register before we give up. */
73 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */ 73 #define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
74 #define MAX_CMD_SIZE 5 74 #define MAX_CMD_SIZE 5
75 75
76 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16) 76 #define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
77 77
78 /****************************************************************************/ 78 /****************************************************************************/
79 79
80 struct m25p { 80 struct m25p {
81 struct spi_device *spi; 81 struct spi_device *spi;
82 struct mutex lock; 82 struct mutex lock;
83 struct mtd_info mtd; 83 struct mtd_info mtd;
84 u16 page_size; 84 u16 page_size;
85 u16 addr_width; 85 u16 addr_width;
86 u8 erase_opcode; 86 u8 erase_opcode;
87 u8 *command; 87 u8 *command;
88 bool fast_read; 88 bool fast_read;
89 }; 89 };
90 90
91 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd) 91 static inline struct m25p *mtd_to_m25p(struct mtd_info *mtd)
92 { 92 {
93 return container_of(mtd, struct m25p, mtd); 93 return container_of(mtd, struct m25p, mtd);
94 } 94 }
95 95
96 /****************************************************************************/ 96 /****************************************************************************/
97 97
98 /* 98 /*
99 * Internal helper functions 99 * Internal helper functions
100 */ 100 */
101 101
102 /* 102 /*
103 * Read the status register, returning its value in the location 103 * Read the status register, returning its value in the location
104 * Return the status register value. 104 * Return the status register value.
105 * Returns negative if error occurred. 105 * Returns negative if error occurred.
106 */ 106 */
107 static int read_sr(struct m25p *flash) 107 static int read_sr(struct m25p *flash)
108 { 108 {
109 ssize_t retval; 109 ssize_t retval;
110 u8 code = OPCODE_RDSR; 110 u8 code = OPCODE_RDSR;
111 u8 val; 111 u8 val;
112 112
113 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1); 113 retval = spi_write_then_read(flash->spi, &code, 1, &val, 1);
114 114
115 if (retval < 0) { 115 if (retval < 0) {
116 dev_err(&flash->spi->dev, "error %d reading SR\n", 116 dev_err(&flash->spi->dev, "error %d reading SR\n",
117 (int) retval); 117 (int) retval);
118 return retval; 118 return retval;
119 } 119 }
120 120
121 return val; 121 return val;
122 } 122 }
123 123
124 /* 124 /*
125 * Write status register 1 byte 125 * Write status register 1 byte
126 * Returns negative if error occurred. 126 * Returns negative if error occurred.
127 */ 127 */
128 static int write_sr(struct m25p *flash, u8 val) 128 static int write_sr(struct m25p *flash, u8 val)
129 { 129 {
130 flash->command[0] = OPCODE_WRSR; 130 flash->command[0] = OPCODE_WRSR;
131 flash->command[1] = val; 131 flash->command[1] = val;
132 132
133 return spi_write(flash->spi, flash->command, 2); 133 return spi_write(flash->spi, flash->command, 2);
134 } 134 }
135 135
136 /* 136 /*
137 * Set write enable latch with Write Enable command. 137 * Set write enable latch with Write Enable command.
138 * Returns negative if error occurred. 138 * Returns negative if error occurred.
139 */ 139 */
140 static inline int write_enable(struct m25p *flash) 140 static inline int write_enable(struct m25p *flash)
141 { 141 {
142 u8 code = OPCODE_WREN; 142 u8 code = OPCODE_WREN;
143 143
144 return spi_write_then_read(flash->spi, &code, 1, NULL, 0); 144 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
145 } 145 }
146 146
147 /* 147 /*
148 * Send write disble instruction to the chip. 148 * Send write disble instruction to the chip.
149 */ 149 */
150 static inline int write_disable(struct m25p *flash) 150 static inline int write_disable(struct m25p *flash)
151 { 151 {
152 u8 code = OPCODE_WRDI; 152 u8 code = OPCODE_WRDI;
153 153
154 return spi_write_then_read(flash->spi, &code, 1, NULL, 0); 154 return spi_write_then_read(flash->spi, &code, 1, NULL, 0);
155 } 155 }
156 156
157 /* 157 /*
158 * Enable/disable 4-byte addressing mode. 158 * Enable/disable 4-byte addressing mode.
159 */ 159 */
160 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable) 160 static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
161 { 161 {
162 switch (JEDEC_MFR(jedec_id)) { 162 switch (JEDEC_MFR(jedec_id)) {
163 case CFI_MFR_MACRONIX: 163 case CFI_MFR_MACRONIX:
164 case 0xEF /* winbond */: 164 case 0xEF /* winbond */:
165 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B; 165 flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
166 return spi_write(flash->spi, flash->command, 1); 166 return spi_write(flash->spi, flash->command, 1);
167 default: 167 default:
168 /* Spansion style */ 168 /* Spansion style */
169 flash->command[0] = OPCODE_BRWR; 169 flash->command[0] = OPCODE_BRWR;
170 flash->command[1] = enable << 7; 170 flash->command[1] = enable << 7;
171 return spi_write(flash->spi, flash->command, 2); 171 return spi_write(flash->spi, flash->command, 2);
172 } 172 }
173 } 173 }
174 174
175 /* 175 /*
176 * Service routine to read status register until ready, or timeout occurs. 176 * Service routine to read status register until ready, or timeout occurs.
177 * Returns non-zero if error. 177 * Returns non-zero if error.
178 */ 178 */
179 static int wait_till_ready(struct m25p *flash) 179 static int wait_till_ready(struct m25p *flash)
180 { 180 {
181 unsigned long deadline; 181 unsigned long deadline;
182 int sr; 182 int sr;
183 183
184 deadline = jiffies + MAX_READY_WAIT_JIFFIES; 184 deadline = jiffies + MAX_READY_WAIT_JIFFIES;
185 185
186 do { 186 do {
187 if ((sr = read_sr(flash)) < 0) 187 if ((sr = read_sr(flash)) < 0)
188 break; 188 break;
189 else if (!(sr & SR_WIP)) 189 else if (!(sr & SR_WIP))
190 return 0; 190 return 0;
191 191
192 cond_resched(); 192 cond_resched();
193 193
194 } while (!time_after_eq(jiffies, deadline)); 194 } while (!time_after_eq(jiffies, deadline));
195 195
196 return 1; 196 return 1;
197 } 197 }
198 198
199 /* 199 /*
200 * Erase the whole flash memory 200 * Erase the whole flash memory
201 * 201 *
202 * Returns 0 if successful, non-zero otherwise. 202 * Returns 0 if successful, non-zero otherwise.
203 */ 203 */
204 static int erase_chip(struct m25p *flash) 204 static int erase_chip(struct m25p *flash)
205 { 205 {
206 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__, 206 pr_debug("%s: %s %lldKiB\n", dev_name(&flash->spi->dev), __func__,
207 (long long)(flash->mtd.size >> 10)); 207 (long long)(flash->mtd.size >> 10));
208 208
209 /* Wait until finished previous write command. */ 209 /* Wait until finished previous write command. */
210 if (wait_till_ready(flash)) 210 if (wait_till_ready(flash))
211 return 1; 211 return 1;
212 212
213 /* Send write enable, then erase commands. */ 213 /* Send write enable, then erase commands. */
214 write_enable(flash); 214 write_enable(flash);
215 215
216 /* Set up command buffer. */ 216 /* Set up command buffer. */
217 flash->command[0] = OPCODE_CHIP_ERASE; 217 flash->command[0] = OPCODE_CHIP_ERASE;
218 218
219 spi_write(flash->spi, flash->command, 1); 219 spi_write(flash->spi, flash->command, 1);
220 220
221 return 0; 221 return 0;
222 } 222 }
223 223
224 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd) 224 static void m25p_addr2cmd(struct m25p *flash, unsigned int addr, u8 *cmd)
225 { 225 {
226 /* opcode is in cmd[0] */ 226 /* opcode is in cmd[0] */
227 cmd[1] = addr >> (flash->addr_width * 8 - 8); 227 cmd[1] = addr >> (flash->addr_width * 8 - 8);
228 cmd[2] = addr >> (flash->addr_width * 8 - 16); 228 cmd[2] = addr >> (flash->addr_width * 8 - 16);
229 cmd[3] = addr >> (flash->addr_width * 8 - 24); 229 cmd[3] = addr >> (flash->addr_width * 8 - 24);
230 cmd[4] = addr >> (flash->addr_width * 8 - 32); 230 cmd[4] = addr >> (flash->addr_width * 8 - 32);
231 } 231 }
232 232
233 static int m25p_cmdsz(struct m25p *flash) 233 static int m25p_cmdsz(struct m25p *flash)
234 { 234 {
235 return 1 + flash->addr_width; 235 return 1 + flash->addr_width;
236 } 236 }
237 237
238 /* 238 /*
239 * Erase one sector of flash memory at offset ``offset'' which is any 239 * Erase one sector of flash memory at offset ``offset'' which is any
240 * address within the sector which should be erased. 240 * address within the sector which should be erased.
241 * 241 *
242 * Returns 0 if successful, non-zero otherwise. 242 * Returns 0 if successful, non-zero otherwise.
243 */ 243 */
244 static int erase_sector(struct m25p *flash, u32 offset) 244 static int erase_sector(struct m25p *flash, u32 offset)
245 { 245 {
246 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev), 246 pr_debug("%s: %s %dKiB at 0x%08x\n", dev_name(&flash->spi->dev),
247 __func__, flash->mtd.erasesize / 1024, offset); 247 __func__, flash->mtd.erasesize / 1024, offset);
248 248
249 /* Wait until finished previous write command. */ 249 /* Wait until finished previous write command. */
250 if (wait_till_ready(flash)) 250 if (wait_till_ready(flash))
251 return 1; 251 return 1;
252 252
253 /* Send write enable, then erase commands. */ 253 /* Send write enable, then erase commands. */
254 write_enable(flash); 254 write_enable(flash);
255 255
256 /* Set up command buffer. */ 256 /* Set up command buffer. */
257 flash->command[0] = flash->erase_opcode; 257 flash->command[0] = flash->erase_opcode;
258 m25p_addr2cmd(flash, offset, flash->command); 258 m25p_addr2cmd(flash, offset, flash->command);
259 259
260 spi_write(flash->spi, flash->command, m25p_cmdsz(flash)); 260 spi_write(flash->spi, flash->command, m25p_cmdsz(flash));
261 261
262 return 0; 262 return 0;
263 } 263 }
264 264
265 /****************************************************************************/ 265 /****************************************************************************/
266 266
267 /* 267 /*
268 * MTD implementation 268 * MTD implementation
269 */ 269 */
270 270
271 /* 271 /*
272 * Erase an address range on the flash chip. The address range may extend 272 * Erase an address range on the flash chip. The address range may extend
273 * one or more erase sectors. Return an error is there is a problem erasing. 273 * one or more erase sectors. Return an error is there is a problem erasing.
274 */ 274 */
275 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr) 275 static int m25p80_erase(struct mtd_info *mtd, struct erase_info *instr)
276 { 276 {
277 struct m25p *flash = mtd_to_m25p(mtd); 277 struct m25p *flash = mtd_to_m25p(mtd);
278 u32 addr,len; 278 u32 addr,len;
279 uint32_t rem; 279 uint32_t rem;
280 280
281 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev), 281 pr_debug("%s: %s at 0x%llx, len %lld\n", dev_name(&flash->spi->dev),
282 __func__, (long long)instr->addr, 282 __func__, (long long)instr->addr,
283 (long long)instr->len); 283 (long long)instr->len);
284 284
285 div_u64_rem(instr->len, mtd->erasesize, &rem); 285 div_u64_rem(instr->len, mtd->erasesize, &rem);
286 if (rem) 286 if (rem)
287 return -EINVAL; 287 return -EINVAL;
288 288
289 addr = instr->addr; 289 addr = instr->addr;
290 len = instr->len; 290 len = instr->len;
291 291
292 mutex_lock(&flash->lock); 292 mutex_lock(&flash->lock);
293 293
294 /* whole-chip erase? */ 294 /* whole-chip erase? */
295 if (len == flash->mtd.size) { 295 if (len == flash->mtd.size) {
296 if (erase_chip(flash)) { 296 if (erase_chip(flash)) {
297 instr->state = MTD_ERASE_FAILED; 297 instr->state = MTD_ERASE_FAILED;
298 mutex_unlock(&flash->lock); 298 mutex_unlock(&flash->lock);
299 return -EIO; 299 return -EIO;
300 } 300 }
301 301
302 /* REVISIT in some cases we could speed up erasing large regions 302 /* REVISIT in some cases we could speed up erasing large regions
303 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up 303 * by using OPCODE_SE instead of OPCODE_BE_4K. We may have set up
304 * to use "small sector erase", but that's not always optimal. 304 * to use "small sector erase", but that's not always optimal.
305 */ 305 */
306 306
307 /* "sector"-at-a-time erase */ 307 /* "sector"-at-a-time erase */
308 } else { 308 } else {
309 while (len) { 309 while (len) {
310 if (erase_sector(flash, addr)) { 310 if (erase_sector(flash, addr)) {
311 instr->state = MTD_ERASE_FAILED; 311 instr->state = MTD_ERASE_FAILED;
312 mutex_unlock(&flash->lock); 312 mutex_unlock(&flash->lock);
313 return -EIO; 313 return -EIO;
314 } 314 }
315 315
316 addr += mtd->erasesize; 316 addr += mtd->erasesize;
317 len -= mtd->erasesize; 317 len -= mtd->erasesize;
318 } 318 }
319 } 319 }
320 320
321 mutex_unlock(&flash->lock); 321 mutex_unlock(&flash->lock);
322 322
323 instr->state = MTD_ERASE_DONE; 323 instr->state = MTD_ERASE_DONE;
324 mtd_erase_callback(instr); 324 mtd_erase_callback(instr);
325 325
326 return 0; 326 return 0;
327 } 327 }
328 328
329 /* 329 /*
330 * Read an address range from the flash chip. The address range 330 * Read an address range from the flash chip. The address range
331 * may be any size provided it is within the physical boundaries. 331 * may be any size provided it is within the physical boundaries.
332 */ 332 */
333 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len, 333 static int m25p80_read(struct mtd_info *mtd, loff_t from, size_t len,
334 size_t *retlen, u_char *buf) 334 size_t *retlen, u_char *buf)
335 { 335 {
336 struct m25p *flash = mtd_to_m25p(mtd); 336 struct m25p *flash = mtd_to_m25p(mtd);
337 struct spi_transfer t[2]; 337 struct spi_transfer t[2];
338 struct spi_message m; 338 struct spi_message m;
339 uint8_t opcode; 339 uint8_t opcode;
340 340
341 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev), 341 pr_debug("%s: %s from 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
342 __func__, (u32)from, len); 342 __func__, (u32)from, len);
343 343
344 spi_message_init(&m); 344 spi_message_init(&m);
345 memset(t, 0, (sizeof t)); 345 memset(t, 0, (sizeof t));
346 346
347 /* NOTE: 347 /* NOTE:
348 * OPCODE_FAST_READ (if available) is faster. 348 * OPCODE_FAST_READ (if available) is faster.
349 * Should add 1 byte DUMMY_BYTE. 349 * Should add 1 byte DUMMY_BYTE.
350 */ 350 */
351 t[0].tx_buf = flash->command; 351 t[0].tx_buf = flash->command;
352 t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0); 352 t[0].len = m25p_cmdsz(flash) + (flash->fast_read ? 1 : 0);
353 spi_message_add_tail(&t[0], &m); 353 spi_message_add_tail(&t[0], &m);
354 354
355 t[1].rx_buf = buf; 355 t[1].rx_buf = buf;
356 t[1].len = len; 356 t[1].len = len;
357 spi_message_add_tail(&t[1], &m); 357 spi_message_add_tail(&t[1], &m);
358 358
359 mutex_lock(&flash->lock); 359 mutex_lock(&flash->lock);
360 360
361 /* Wait till previous write/erase is done. */ 361 /* Wait till previous write/erase is done. */
362 if (wait_till_ready(flash)) { 362 if (wait_till_ready(flash)) {
363 /* REVISIT status return?? */ 363 /* REVISIT status return?? */
364 mutex_unlock(&flash->lock); 364 mutex_unlock(&flash->lock);
365 return 1; 365 return 1;
366 } 366 }
367 367
368 /* FIXME switch to OPCODE_FAST_READ. It's required for higher 368 /* FIXME switch to OPCODE_FAST_READ. It's required for higher
369 * clocks; and at this writing, every chip this driver handles 369 * clocks; and at this writing, every chip this driver handles
370 * supports that opcode. 370 * supports that opcode.
371 */ 371 */
372 372
373 /* Set up the write data buffer. */ 373 /* Set up the write data buffer. */
374 opcode = flash->fast_read ? OPCODE_FAST_READ : OPCODE_NORM_READ; 374 opcode = flash->fast_read ? OPCODE_FAST_READ : OPCODE_NORM_READ;
375 flash->command[0] = opcode; 375 flash->command[0] = opcode;
376 m25p_addr2cmd(flash, from, flash->command); 376 m25p_addr2cmd(flash, from, flash->command);
377 377
378 spi_sync(flash->spi, &m); 378 spi_sync(flash->spi, &m);
379 379
380 *retlen = m.actual_length - m25p_cmdsz(flash) - 380 *retlen = m.actual_length - m25p_cmdsz(flash) -
381 (flash->fast_read ? 1 : 0); 381 (flash->fast_read ? 1 : 0);
382 382
383 mutex_unlock(&flash->lock); 383 mutex_unlock(&flash->lock);
384 384
385 return 0; 385 return 0;
386 } 386 }
387 387
388 /* 388 /*
389 * Write an address range to the flash chip. Data must be written in 389 * Write an address range to the flash chip. Data must be written in
390 * FLASH_PAGESIZE chunks. The address range may be any size provided 390 * FLASH_PAGESIZE chunks. The address range may be any size provided
391 * it is within the physical boundaries. 391 * it is within the physical boundaries.
392 */ 392 */
393 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len, 393 static int m25p80_write(struct mtd_info *mtd, loff_t to, size_t len,
394 size_t *retlen, const u_char *buf) 394 size_t *retlen, const u_char *buf)
395 { 395 {
396 struct m25p *flash = mtd_to_m25p(mtd); 396 struct m25p *flash = mtd_to_m25p(mtd);
397 u32 page_offset, page_size; 397 u32 page_offset, page_size;
398 struct spi_transfer t[2]; 398 struct spi_transfer t[2];
399 struct spi_message m; 399 struct spi_message m;
400 400
401 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev), 401 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
402 __func__, (u32)to, len); 402 __func__, (u32)to, len);
403 403
404 spi_message_init(&m); 404 spi_message_init(&m);
405 memset(t, 0, (sizeof t)); 405 memset(t, 0, (sizeof t));
406 406
407 t[0].tx_buf = flash->command; 407 t[0].tx_buf = flash->command;
408 t[0].len = m25p_cmdsz(flash); 408 t[0].len = m25p_cmdsz(flash);
409 spi_message_add_tail(&t[0], &m); 409 spi_message_add_tail(&t[0], &m);
410 410
411 t[1].tx_buf = buf; 411 t[1].tx_buf = buf;
412 spi_message_add_tail(&t[1], &m); 412 spi_message_add_tail(&t[1], &m);
413 413
414 mutex_lock(&flash->lock); 414 mutex_lock(&flash->lock);
415 415
416 /* Wait until finished previous write command. */ 416 /* Wait until finished previous write command. */
417 if (wait_till_ready(flash)) { 417 if (wait_till_ready(flash)) {
418 mutex_unlock(&flash->lock); 418 mutex_unlock(&flash->lock);
419 return 1; 419 return 1;
420 } 420 }
421 421
422 write_enable(flash); 422 write_enable(flash);
423 423
424 /* Set up the opcode in the write buffer. */ 424 /* Set up the opcode in the write buffer. */
425 flash->command[0] = OPCODE_PP; 425 flash->command[0] = OPCODE_PP;
426 m25p_addr2cmd(flash, to, flash->command); 426 m25p_addr2cmd(flash, to, flash->command);
427 427
428 page_offset = to & (flash->page_size - 1); 428 page_offset = to & (flash->page_size - 1);
429 429
430 /* do all the bytes fit onto one page? */ 430 /* do all the bytes fit onto one page? */
431 if (page_offset + len <= flash->page_size) { 431 if (page_offset + len <= flash->page_size) {
432 t[1].len = len; 432 t[1].len = len;
433 433
434 spi_sync(flash->spi, &m); 434 spi_sync(flash->spi, &m);
435 435
436 *retlen = m.actual_length - m25p_cmdsz(flash); 436 *retlen = m.actual_length - m25p_cmdsz(flash);
437 } else { 437 } else {
438 u32 i; 438 u32 i;
439 439
440 /* the size of data remaining on the first page */ 440 /* the size of data remaining on the first page */
441 page_size = flash->page_size - page_offset; 441 page_size = flash->page_size - page_offset;
442 442
443 t[1].len = page_size; 443 t[1].len = page_size;
444 spi_sync(flash->spi, &m); 444 spi_sync(flash->spi, &m);
445 445
446 *retlen = m.actual_length - m25p_cmdsz(flash); 446 *retlen = m.actual_length - m25p_cmdsz(flash);
447 447
448 /* write everything in flash->page_size chunks */ 448 /* write everything in flash->page_size chunks */
449 for (i = page_size; i < len; i += page_size) { 449 for (i = page_size; i < len; i += page_size) {
450 page_size = len - i; 450 page_size = len - i;
451 if (page_size > flash->page_size) 451 if (page_size > flash->page_size)
452 page_size = flash->page_size; 452 page_size = flash->page_size;
453 453
454 /* write the next page to flash */ 454 /* write the next page to flash */
455 m25p_addr2cmd(flash, to + i, flash->command); 455 m25p_addr2cmd(flash, to + i, flash->command);
456 456
457 t[1].tx_buf = buf + i; 457 t[1].tx_buf = buf + i;
458 t[1].len = page_size; 458 t[1].len = page_size;
459 459
460 wait_till_ready(flash); 460 wait_till_ready(flash);
461 461
462 write_enable(flash); 462 write_enable(flash);
463 463
464 spi_sync(flash->spi, &m); 464 spi_sync(flash->spi, &m);
465 465
466 *retlen += m.actual_length - m25p_cmdsz(flash); 466 *retlen += m.actual_length - m25p_cmdsz(flash);
467 } 467 }
468 } 468 }
469 469
470 mutex_unlock(&flash->lock); 470 mutex_unlock(&flash->lock);
471 471
472 return 0; 472 return 0;
473 } 473 }
474 474
475 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len, 475 static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
476 size_t *retlen, const u_char *buf) 476 size_t *retlen, const u_char *buf)
477 { 477 {
478 struct m25p *flash = mtd_to_m25p(mtd); 478 struct m25p *flash = mtd_to_m25p(mtd);
479 struct spi_transfer t[2]; 479 struct spi_transfer t[2];
480 struct spi_message m; 480 struct spi_message m;
481 size_t actual; 481 size_t actual;
482 int cmd_sz, ret; 482 int cmd_sz, ret;
483 483
484 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev), 484 pr_debug("%s: %s to 0x%08x, len %zd\n", dev_name(&flash->spi->dev),
485 __func__, (u32)to, len); 485 __func__, (u32)to, len);
486 486
487 spi_message_init(&m); 487 spi_message_init(&m);
488 memset(t, 0, (sizeof t)); 488 memset(t, 0, (sizeof t));
489 489
490 t[0].tx_buf = flash->command; 490 t[0].tx_buf = flash->command;
491 t[0].len = m25p_cmdsz(flash); 491 t[0].len = m25p_cmdsz(flash);
492 spi_message_add_tail(&t[0], &m); 492 spi_message_add_tail(&t[0], &m);
493 493
494 t[1].tx_buf = buf; 494 t[1].tx_buf = buf;
495 spi_message_add_tail(&t[1], &m); 495 spi_message_add_tail(&t[1], &m);
496 496
497 mutex_lock(&flash->lock); 497 mutex_lock(&flash->lock);
498 498
499 /* Wait until finished previous write command. */ 499 /* Wait until finished previous write command. */
500 ret = wait_till_ready(flash); 500 ret = wait_till_ready(flash);
501 if (ret) 501 if (ret)
502 goto time_out; 502 goto time_out;
503 503
504 write_enable(flash); 504 write_enable(flash);
505 505
506 actual = to % 2; 506 actual = to % 2;
507 /* Start write from odd address. */ 507 /* Start write from odd address. */
508 if (actual) { 508 if (actual) {
509 flash->command[0] = OPCODE_BP; 509 flash->command[0] = OPCODE_BP;
510 m25p_addr2cmd(flash, to, flash->command); 510 m25p_addr2cmd(flash, to, flash->command);
511 511
512 /* write one byte. */ 512 /* write one byte. */
513 t[1].len = 1; 513 t[1].len = 1;
514 spi_sync(flash->spi, &m); 514 spi_sync(flash->spi, &m);
515 ret = wait_till_ready(flash); 515 ret = wait_till_ready(flash);
516 if (ret) 516 if (ret)
517 goto time_out; 517 goto time_out;
518 *retlen += m.actual_length - m25p_cmdsz(flash); 518 *retlen += m.actual_length - m25p_cmdsz(flash);
519 } 519 }
520 to += actual; 520 to += actual;
521 521
522 flash->command[0] = OPCODE_AAI_WP; 522 flash->command[0] = OPCODE_AAI_WP;
523 m25p_addr2cmd(flash, to, flash->command); 523 m25p_addr2cmd(flash, to, flash->command);
524 524
525 /* Write out most of the data here. */ 525 /* Write out most of the data here. */
526 cmd_sz = m25p_cmdsz(flash); 526 cmd_sz = m25p_cmdsz(flash);
527 for (; actual < len - 1; actual += 2) { 527 for (; actual < len - 1; actual += 2) {
528 t[0].len = cmd_sz; 528 t[0].len = cmd_sz;
529 /* write two bytes. */ 529 /* write two bytes. */
530 t[1].len = 2; 530 t[1].len = 2;
531 t[1].tx_buf = buf + actual; 531 t[1].tx_buf = buf + actual;
532 532
533 spi_sync(flash->spi, &m); 533 spi_sync(flash->spi, &m);
534 ret = wait_till_ready(flash); 534 ret = wait_till_ready(flash);
535 if (ret) 535 if (ret)
536 goto time_out; 536 goto time_out;
537 *retlen += m.actual_length - cmd_sz; 537 *retlen += m.actual_length - cmd_sz;
538 cmd_sz = 1; 538 cmd_sz = 1;
539 to += 2; 539 to += 2;
540 } 540 }
541 write_disable(flash); 541 write_disable(flash);
542 ret = wait_till_ready(flash); 542 ret = wait_till_ready(flash);
543 if (ret) 543 if (ret)
544 goto time_out; 544 goto time_out;
545 545
546 /* Write out trailing byte if it exists. */ 546 /* Write out trailing byte if it exists. */
547 if (actual != len) { 547 if (actual != len) {
548 write_enable(flash); 548 write_enable(flash);
549 flash->command[0] = OPCODE_BP; 549 flash->command[0] = OPCODE_BP;
550 m25p_addr2cmd(flash, to, flash->command); 550 m25p_addr2cmd(flash, to, flash->command);
551 t[0].len = m25p_cmdsz(flash); 551 t[0].len = m25p_cmdsz(flash);
552 t[1].len = 1; 552 t[1].len = 1;
553 t[1].tx_buf = buf + actual; 553 t[1].tx_buf = buf + actual;
554 554
555 spi_sync(flash->spi, &m); 555 spi_sync(flash->spi, &m);
556 ret = wait_till_ready(flash); 556 ret = wait_till_ready(flash);
557 if (ret) 557 if (ret)
558 goto time_out; 558 goto time_out;
559 *retlen += m.actual_length - m25p_cmdsz(flash); 559 *retlen += m.actual_length - m25p_cmdsz(flash);
560 write_disable(flash); 560 write_disable(flash);
561 } 561 }
562 562
563 time_out: 563 time_out:
564 mutex_unlock(&flash->lock); 564 mutex_unlock(&flash->lock);
565 return ret; 565 return ret;
566 } 566 }
567 567
568 static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 568 static int m25p80_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
569 { 569 {
570 struct m25p *flash = mtd_to_m25p(mtd); 570 struct m25p *flash = mtd_to_m25p(mtd);
571 uint32_t offset = ofs; 571 uint32_t offset = ofs;
572 uint8_t status_old, status_new; 572 uint8_t status_old, status_new;
573 int res = 0; 573 int res = 0;
574 574
575 mutex_lock(&flash->lock); 575 mutex_lock(&flash->lock);
576 /* Wait until finished previous command */ 576 /* Wait until finished previous command */
577 if (wait_till_ready(flash)) { 577 if (wait_till_ready(flash)) {
578 res = 1; 578 res = 1;
579 goto err; 579 goto err;
580 } 580 }
581 581
582 status_old = read_sr(flash); 582 status_old = read_sr(flash);
583 583
584 if (offset < flash->mtd.size-(flash->mtd.size/2)) 584 if (offset < flash->mtd.size-(flash->mtd.size/2))
585 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0; 585 status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
586 else if (offset < flash->mtd.size-(flash->mtd.size/4)) 586 else if (offset < flash->mtd.size-(flash->mtd.size/4))
587 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; 587 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
588 else if (offset < flash->mtd.size-(flash->mtd.size/8)) 588 else if (offset < flash->mtd.size-(flash->mtd.size/8))
589 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; 589 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
590 else if (offset < flash->mtd.size-(flash->mtd.size/16)) 590 else if (offset < flash->mtd.size-(flash->mtd.size/16))
591 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2; 591 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
592 else if (offset < flash->mtd.size-(flash->mtd.size/32)) 592 else if (offset < flash->mtd.size-(flash->mtd.size/32))
593 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; 593 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
594 else if (offset < flash->mtd.size-(flash->mtd.size/64)) 594 else if (offset < flash->mtd.size-(flash->mtd.size/64))
595 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1; 595 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
596 else 596 else
597 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0; 597 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
598 598
599 /* Only modify protection if it will not unlock other areas */ 599 /* Only modify protection if it will not unlock other areas */
600 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) > 600 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) >
601 (status_old&(SR_BP2|SR_BP1|SR_BP0))) { 601 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
602 write_enable(flash); 602 write_enable(flash);
603 if (write_sr(flash, status_new) < 0) { 603 if (write_sr(flash, status_new) < 0) {
604 res = 1; 604 res = 1;
605 goto err; 605 goto err;
606 } 606 }
607 } 607 }
608 608
609 err: mutex_unlock(&flash->lock); 609 err: mutex_unlock(&flash->lock);
610 return res; 610 return res;
611 } 611 }
612 612
613 static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len) 613 static int m25p80_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
614 { 614 {
615 struct m25p *flash = mtd_to_m25p(mtd); 615 struct m25p *flash = mtd_to_m25p(mtd);
616 uint32_t offset = ofs; 616 uint32_t offset = ofs;
617 uint8_t status_old, status_new; 617 uint8_t status_old, status_new;
618 int res = 0; 618 int res = 0;
619 619
620 mutex_lock(&flash->lock); 620 mutex_lock(&flash->lock);
621 /* Wait until finished previous command */ 621 /* Wait until finished previous command */
622 if (wait_till_ready(flash)) { 622 if (wait_till_ready(flash)) {
623 res = 1; 623 res = 1;
624 goto err; 624 goto err;
625 } 625 }
626 626
627 status_old = read_sr(flash); 627 status_old = read_sr(flash);
628 628
629 if (offset+len > flash->mtd.size-(flash->mtd.size/64)) 629 if (offset+len > flash->mtd.size-(flash->mtd.size/64))
630 status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0); 630 status_new = status_old & ~(SR_BP2|SR_BP1|SR_BP0);
631 else if (offset+len > flash->mtd.size-(flash->mtd.size/32)) 631 else if (offset+len > flash->mtd.size-(flash->mtd.size/32))
632 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0; 632 status_new = (status_old & ~(SR_BP2|SR_BP1)) | SR_BP0;
633 else if (offset+len > flash->mtd.size-(flash->mtd.size/16)) 633 else if (offset+len > flash->mtd.size-(flash->mtd.size/16))
634 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1; 634 status_new = (status_old & ~(SR_BP2|SR_BP0)) | SR_BP1;
635 else if (offset+len > flash->mtd.size-(flash->mtd.size/8)) 635 else if (offset+len > flash->mtd.size-(flash->mtd.size/8))
636 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0; 636 status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
637 else if (offset+len > flash->mtd.size-(flash->mtd.size/4)) 637 else if (offset+len > flash->mtd.size-(flash->mtd.size/4))
638 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2; 638 status_new = (status_old & ~(SR_BP0|SR_BP1)) | SR_BP2;
639 else if (offset+len > flash->mtd.size-(flash->mtd.size/2)) 639 else if (offset+len > flash->mtd.size-(flash->mtd.size/2))
640 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0; 640 status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
641 else 641 else
642 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1; 642 status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
643 643
644 /* Only modify protection if it will not lock other areas */ 644 /* Only modify protection if it will not lock other areas */
645 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) < 645 if ((status_new&(SR_BP2|SR_BP1|SR_BP0)) <
646 (status_old&(SR_BP2|SR_BP1|SR_BP0))) { 646 (status_old&(SR_BP2|SR_BP1|SR_BP0))) {
647 write_enable(flash); 647 write_enable(flash);
648 if (write_sr(flash, status_new) < 0) { 648 if (write_sr(flash, status_new) < 0) {
649 res = 1; 649 res = 1;
650 goto err; 650 goto err;
651 } 651 }
652 } 652 }
653 653
654 err: mutex_unlock(&flash->lock); 654 err: mutex_unlock(&flash->lock);
655 return res; 655 return res;
656 } 656 }
657 657
658 /****************************************************************************/ 658 /****************************************************************************/
659 659
660 /* 660 /*
661 * SPI device driver setup and teardown 661 * SPI device driver setup and teardown
662 */ 662 */
663 663
664 struct flash_info { 664 struct flash_info {
665 /* JEDEC id zero means "no ID" (most older chips); otherwise it has 665 /* JEDEC id zero means "no ID" (most older chips); otherwise it has
666 * a high byte of zero plus three data bytes: the manufacturer id, 666 * a high byte of zero plus three data bytes: the manufacturer id,
667 * then a two byte device id. 667 * then a two byte device id.
668 */ 668 */
669 u32 jedec_id; 669 u32 jedec_id;
670 u16 ext_id; 670 u16 ext_id;
671 671
672 /* The size listed here is what works with OPCODE_SE, which isn't 672 /* The size listed here is what works with OPCODE_SE, which isn't
673 * necessarily called a "sector" by the vendor. 673 * necessarily called a "sector" by the vendor.
674 */ 674 */
675 unsigned sector_size; 675 unsigned sector_size;
676 u16 n_sectors; 676 u16 n_sectors;
677 677
678 u16 page_size; 678 u16 page_size;
679 u16 addr_width; 679 u16 addr_width;
680 680
681 u16 flags; 681 u16 flags;
682 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */ 682 #define SECT_4K 0x01 /* OPCODE_BE_4K works uniformly */
683 #define M25P_NO_ERASE 0x02 /* No erase command needed */ 683 #define M25P_NO_ERASE 0x02 /* No erase command needed */
684 }; 684 };
685 685
686 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \ 686 #define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
687 ((kernel_ulong_t)&(struct flash_info) { \ 687 ((kernel_ulong_t)&(struct flash_info) { \
688 .jedec_id = (_jedec_id), \ 688 .jedec_id = (_jedec_id), \
689 .ext_id = (_ext_id), \ 689 .ext_id = (_ext_id), \
690 .sector_size = (_sector_size), \ 690 .sector_size = (_sector_size), \
691 .n_sectors = (_n_sectors), \ 691 .n_sectors = (_n_sectors), \
692 .page_size = 256, \ 692 .page_size = 256, \
693 .flags = (_flags), \ 693 .flags = (_flags), \
694 }) 694 })
695 695
696 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \ 696 #define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width) \
697 ((kernel_ulong_t)&(struct flash_info) { \ 697 ((kernel_ulong_t)&(struct flash_info) { \
698 .sector_size = (_sector_size), \ 698 .sector_size = (_sector_size), \
699 .n_sectors = (_n_sectors), \ 699 .n_sectors = (_n_sectors), \
700 .page_size = (_page_size), \ 700 .page_size = (_page_size), \
701 .addr_width = (_addr_width), \ 701 .addr_width = (_addr_width), \
702 .flags = M25P_NO_ERASE, \ 702 .flags = M25P_NO_ERASE, \
703 }) 703 })
704 704
705 /* NOTE: double check command sets and memory organization when you add 705 /* NOTE: double check command sets and memory organization when you add
706 * more flash chips. This current list focusses on newer chips, which 706 * more flash chips. This current list focusses on newer chips, which
707 * have been converging on command sets which including JEDEC ID. 707 * have been converging on command sets which including JEDEC ID.
708 */ 708 */
709 static const struct spi_device_id m25p_ids[] = { 709 static const struct spi_device_id m25p_ids[] = {
710 /* Atmel -- some are (confusingly) marketed as "DataFlash" */ 710 /* Atmel -- some are (confusingly) marketed as "DataFlash" */
711 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) }, 711 { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
712 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) }, 712 { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
713 713
714 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) }, 714 { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
715 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) }, 715 { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
716 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) }, 716 { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
717 717
718 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) }, 718 { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
719 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, 719 { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
720 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) }, 720 { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
721 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) }, 721 { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
722 722
723 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) }, 723 { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
724 724
725 /* EON -- en25xxx */ 725 /* EON -- en25xxx */
726 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) }, 726 { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
727 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) }, 727 { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
728 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) }, 728 { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
729 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) }, 729 { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
730 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) }, 730 { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
731 731
732 /* Everspin */ 732 /* Everspin */
733 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2) }, 733 { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2) },
734 734
735 /* GigaDevice */
736 { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
737 { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
738
735 /* Intel/Numonyx -- xxxs33b */ 739 /* Intel/Numonyx -- xxxs33b */
736 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) }, 740 { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
737 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) }, 741 { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
738 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) }, 742 { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
739 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) }, 743 { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
740 744
741 /* Macronix */ 745 /* Macronix */
742 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, 746 { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
743 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) }, 747 { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
744 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) }, 748 { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
745 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) }, 749 { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
746 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) }, 750 { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
747 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) }, 751 { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
748 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) }, 752 { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
749 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) }, 753 { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
750 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) }, 754 { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
751 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) }, 755 { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
752 756
753 /* Micron */ 757 /* Micron */
754 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) }, 758 { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
755 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) }, 759 { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
756 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) }, 760 { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
757 761
758 /* Spansion -- single (large) sector size only, at least 762 /* Spansion -- single (large) sector size only, at least
759 * for the chips listed here (without boot sectors). 763 * for the chips listed here (without boot sectors).
760 */ 764 */
761 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) }, 765 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, 0) },
762 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) }, 766 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
763 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) }, 767 { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
764 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) }, 768 { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, 0) },
765 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) }, 769 { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, 0) },
766 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) }, 770 { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
767 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) }, 771 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
768 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) }, 772 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
769 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) }, 773 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
770 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) }, 774 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
771 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) }, 775 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
772 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) }, 776 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
773 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) }, 777 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
774 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) }, 778 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
775 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) }, 779 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
776 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) }, 780 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
777 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 781 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
778 782
779 /* SST -- large erase sizes are "overlays", "sectors" are 4K */ 783 /* SST -- large erase sizes are "overlays", "sectors" are 4K */
780 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) }, 784 { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K) },
781 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) }, 785 { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K) },
782 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) }, 786 { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K) },
783 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) }, 787 { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K) },
784 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) }, 788 { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K) },
785 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) }, 789 { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K) },
786 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) }, 790 { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K) },
787 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) }, 791 { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K) },
788 792
789 /* ST Microelectronics -- newer production may have feature updates */ 793 /* ST Microelectronics -- newer production may have feature updates */
790 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) }, 794 { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
791 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) }, 795 { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
792 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) }, 796 { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
793 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) }, 797 { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
794 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) }, 798 { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
795 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) }, 799 { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
796 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) }, 800 { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
797 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) }, 801 { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
798 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) }, 802 { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
799 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) }, 803 { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
800 804
801 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) }, 805 { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
802 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) }, 806 { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
803 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) }, 807 { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
804 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) }, 808 { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
805 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) }, 809 { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
806 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) }, 810 { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
807 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) }, 811 { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
808 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) }, 812 { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
809 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) }, 813 { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
810 814
811 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) }, 815 { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
812 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) }, 816 { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
813 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) }, 817 { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
814 818
815 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) }, 819 { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
816 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) }, 820 { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
817 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) }, 821 { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
818 822
819 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) }, 823 { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
820 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) }, 824 { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
821 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) }, 825 { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
822 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) }, 826 { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
823 827
824 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */ 828 /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
825 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) }, 829 { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
826 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) }, 830 { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
827 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) }, 831 { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
828 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) }, 832 { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
829 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) }, 833 { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
830 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) }, 834 { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
831 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) }, 835 { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
832 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) }, 836 { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
833 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) }, 837 { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
834 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) }, 838 { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
835 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) }, 839 { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
836 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) }, 840 { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
837 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) }, 841 { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
838 842
839 /* Catalyst / On Semiconductor -- non-JEDEC */ 843 /* Catalyst / On Semiconductor -- non-JEDEC */
840 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) }, 844 { "cat25c11", CAT25_INFO( 16, 8, 16, 1) },
841 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) }, 845 { "cat25c03", CAT25_INFO( 32, 8, 16, 2) },
842 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) }, 846 { "cat25c09", CAT25_INFO( 128, 8, 32, 2) },
843 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) }, 847 { "cat25c17", CAT25_INFO( 256, 8, 32, 2) },
844 { "cat25128", CAT25_INFO(2048, 8, 64, 2) }, 848 { "cat25128", CAT25_INFO(2048, 8, 64, 2) },
845 { }, 849 { },
846 }; 850 };
847 MODULE_DEVICE_TABLE(spi, m25p_ids); 851 MODULE_DEVICE_TABLE(spi, m25p_ids);
848 852
849 static const struct spi_device_id *jedec_probe(struct spi_device *spi) 853 static const struct spi_device_id *jedec_probe(struct spi_device *spi)
850 { 854 {
851 int tmp; 855 int tmp;
852 u8 code = OPCODE_RDID; 856 u8 code = OPCODE_RDID;
853 u8 id[5]; 857 u8 id[5];
854 u32 jedec; 858 u32 jedec;
855 u16 ext_jedec; 859 u16 ext_jedec;
856 struct flash_info *info; 860 struct flash_info *info;
857 861
858 /* JEDEC also defines an optional "extended device information" 862 /* JEDEC also defines an optional "extended device information"
859 * string for after vendor-specific data, after the three bytes 863 * string for after vendor-specific data, after the three bytes
860 * we use here. Supporting some chips might require using it. 864 * we use here. Supporting some chips might require using it.
861 */ 865 */
862 tmp = spi_write_then_read(spi, &code, 1, id, 5); 866 tmp = spi_write_then_read(spi, &code, 1, id, 5);
863 if (tmp < 0) { 867 if (tmp < 0) {
864 pr_debug("%s: error %d reading JEDEC ID\n", 868 pr_debug("%s: error %d reading JEDEC ID\n",
865 dev_name(&spi->dev), tmp); 869 dev_name(&spi->dev), tmp);
866 return ERR_PTR(tmp); 870 return ERR_PTR(tmp);
867 } 871 }
868 jedec = id[0]; 872 jedec = id[0];
869 jedec = jedec << 8; 873 jedec = jedec << 8;
870 jedec |= id[1]; 874 jedec |= id[1];
871 jedec = jedec << 8; 875 jedec = jedec << 8;
872 jedec |= id[2]; 876 jedec |= id[2];
873 877
874 ext_jedec = id[3] << 8 | id[4]; 878 ext_jedec = id[3] << 8 | id[4];
875 879
876 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) { 880 for (tmp = 0; tmp < ARRAY_SIZE(m25p_ids) - 1; tmp++) {
877 info = (void *)m25p_ids[tmp].driver_data; 881 info = (void *)m25p_ids[tmp].driver_data;
878 if (info->jedec_id == jedec) { 882 if (info->jedec_id == jedec) {
879 if (info->ext_id != 0 && info->ext_id != ext_jedec) 883 if (info->ext_id != 0 && info->ext_id != ext_jedec)
880 continue; 884 continue;
881 return &m25p_ids[tmp]; 885 return &m25p_ids[tmp];
882 } 886 }
883 } 887 }
884 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec); 888 dev_err(&spi->dev, "unrecognized JEDEC id %06x\n", jedec);
885 return ERR_PTR(-ENODEV); 889 return ERR_PTR(-ENODEV);
886 } 890 }
887 891
888 892
889 /* 893 /*
890 * board specific setup should have ensured the SPI clock used here 894 * board specific setup should have ensured the SPI clock used here
891 * matches what the READ command supports, at least until this driver 895 * matches what the READ command supports, at least until this driver
892 * understands FAST_READ (for clocks over 25 MHz). 896 * understands FAST_READ (for clocks over 25 MHz).
893 */ 897 */
894 static int m25p_probe(struct spi_device *spi) 898 static int m25p_probe(struct spi_device *spi)
895 { 899 {
896 const struct spi_device_id *id = spi_get_device_id(spi); 900 const struct spi_device_id *id = spi_get_device_id(spi);
897 struct flash_platform_data *data; 901 struct flash_platform_data *data;
898 struct m25p *flash; 902 struct m25p *flash;
899 struct flash_info *info; 903 struct flash_info *info;
900 unsigned i; 904 unsigned i;
901 struct mtd_part_parser_data ppdata; 905 struct mtd_part_parser_data ppdata;
902 struct device_node __maybe_unused *np = spi->dev.of_node; 906 struct device_node __maybe_unused *np = spi->dev.of_node;
903 907
904 #ifdef CONFIG_MTD_OF_PARTS 908 #ifdef CONFIG_MTD_OF_PARTS
905 if (!of_device_is_available(np)) 909 if (!of_device_is_available(np))
906 return -ENODEV; 910 return -ENODEV;
907 #endif 911 #endif
908 912
909 /* Platform data helps sort out which chip type we have, as 913 /* Platform data helps sort out which chip type we have, as
910 * well as how this board partitions it. If we don't have 914 * well as how this board partitions it. If we don't have
911 * a chip ID, try the JEDEC id commands; they'll work for most 915 * a chip ID, try the JEDEC id commands; they'll work for most
912 * newer chips, even if we don't recognize the particular chip. 916 * newer chips, even if we don't recognize the particular chip.
913 */ 917 */
914 data = spi->dev.platform_data; 918 data = spi->dev.platform_data;
915 if (data && data->type) { 919 if (data && data->type) {
916 const struct spi_device_id *plat_id; 920 const struct spi_device_id *plat_id;
917 921
918 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) { 922 for (i = 0; i < ARRAY_SIZE(m25p_ids) - 1; i++) {
919 plat_id = &m25p_ids[i]; 923 plat_id = &m25p_ids[i];
920 if (strcmp(data->type, plat_id->name)) 924 if (strcmp(data->type, plat_id->name))
921 continue; 925 continue;
922 break; 926 break;
923 } 927 }
924 928
925 if (i < ARRAY_SIZE(m25p_ids) - 1) 929 if (i < ARRAY_SIZE(m25p_ids) - 1)
926 id = plat_id; 930 id = plat_id;
927 else 931 else
928 dev_warn(&spi->dev, "unrecognized id %s\n", data->type); 932 dev_warn(&spi->dev, "unrecognized id %s\n", data->type);
929 } 933 }
930 934
931 info = (void *)id->driver_data; 935 info = (void *)id->driver_data;
932 936
933 if (info->jedec_id) { 937 if (info->jedec_id) {
934 const struct spi_device_id *jid; 938 const struct spi_device_id *jid;
935 939
936 jid = jedec_probe(spi); 940 jid = jedec_probe(spi);
937 if (IS_ERR(jid)) { 941 if (IS_ERR(jid)) {
938 return PTR_ERR(jid); 942 return PTR_ERR(jid);
939 } else if (jid != id) { 943 } else if (jid != id) {
940 /* 944 /*
941 * JEDEC knows better, so overwrite platform ID. We 945 * JEDEC knows better, so overwrite platform ID. We
942 * can't trust partitions any longer, but we'll let 946 * can't trust partitions any longer, but we'll let
943 * mtd apply them anyway, since some partitions may be 947 * mtd apply them anyway, since some partitions may be
944 * marked read-only, and we don't want to lose that 948 * marked read-only, and we don't want to lose that
945 * information, even if it's not 100% accurate. 949 * information, even if it's not 100% accurate.
946 */ 950 */
947 dev_warn(&spi->dev, "found %s, expected %s\n", 951 dev_warn(&spi->dev, "found %s, expected %s\n",
948 jid->name, id->name); 952 jid->name, id->name);
949 id = jid; 953 id = jid;
950 info = (void *)jid->driver_data; 954 info = (void *)jid->driver_data;
951 } 955 }
952 } 956 }
953 957
954 flash = kzalloc(sizeof *flash, GFP_KERNEL); 958 flash = kzalloc(sizeof *flash, GFP_KERNEL);
955 if (!flash) 959 if (!flash)
956 return -ENOMEM; 960 return -ENOMEM;
957 flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0), 961 flash->command = kmalloc(MAX_CMD_SIZE + (flash->fast_read ? 1 : 0),
958 GFP_KERNEL); 962 GFP_KERNEL);
959 if (!flash->command) { 963 if (!flash->command) {
960 kfree(flash); 964 kfree(flash);
961 return -ENOMEM; 965 return -ENOMEM;
962 } 966 }
963 967
964 flash->spi = spi; 968 flash->spi = spi;
965 mutex_init(&flash->lock); 969 mutex_init(&flash->lock);
966 dev_set_drvdata(&spi->dev, flash); 970 dev_set_drvdata(&spi->dev, flash);
967 971
968 /* 972 /*
969 * Atmel, SST and Intel/Numonyx serial flash tend to power 973 * Atmel, SST and Intel/Numonyx serial flash tend to power
970 * up with the software protection bits set 974 * up with the software protection bits set
971 */ 975 */
972 976
973 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL || 977 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
974 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL || 978 JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
975 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) { 979 JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
976 write_enable(flash); 980 write_enable(flash);
977 write_sr(flash, 0); 981 write_sr(flash, 0);
978 } 982 }
979 983
980 if (data && data->name) 984 if (data && data->name)
981 flash->mtd.name = data->name; 985 flash->mtd.name = data->name;
982 else 986 else
983 flash->mtd.name = dev_name(&spi->dev); 987 flash->mtd.name = dev_name(&spi->dev);
984 988
985 flash->mtd.type = MTD_NORFLASH; 989 flash->mtd.type = MTD_NORFLASH;
986 flash->mtd.writesize = 1; 990 flash->mtd.writesize = 1;
987 flash->mtd.flags = MTD_CAP_NORFLASH; 991 flash->mtd.flags = MTD_CAP_NORFLASH;
988 flash->mtd.size = info->sector_size * info->n_sectors; 992 flash->mtd.size = info->sector_size * info->n_sectors;
989 flash->mtd._erase = m25p80_erase; 993 flash->mtd._erase = m25p80_erase;
990 flash->mtd._read = m25p80_read; 994 flash->mtd._read = m25p80_read;
991 995
992 /* flash protection support for STmicro chips */ 996 /* flash protection support for STmicro chips */
993 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) { 997 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
994 flash->mtd._lock = m25p80_lock; 998 flash->mtd._lock = m25p80_lock;
995 flash->mtd._unlock = m25p80_unlock; 999 flash->mtd._unlock = m25p80_unlock;
996 } 1000 }
997 1001
998 /* sst flash chips use AAI word program */ 1002 /* sst flash chips use AAI word program */
999 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) 1003 if (JEDEC_MFR(info->jedec_id) == CFI_MFR_SST)
1000 flash->mtd._write = sst_write; 1004 flash->mtd._write = sst_write;
1001 else 1005 else
1002 flash->mtd._write = m25p80_write; 1006 flash->mtd._write = m25p80_write;
1003 1007
1004 /* prefer "small sector" erase if possible */ 1008 /* prefer "small sector" erase if possible */
1005 if (info->flags & SECT_4K) { 1009 if (info->flags & SECT_4K) {
1006 flash->erase_opcode = OPCODE_BE_4K; 1010 flash->erase_opcode = OPCODE_BE_4K;
1007 flash->mtd.erasesize = 4096; 1011 flash->mtd.erasesize = 4096;
1008 } else { 1012 } else {
1009 flash->erase_opcode = OPCODE_SE; 1013 flash->erase_opcode = OPCODE_SE;
1010 flash->mtd.erasesize = info->sector_size; 1014 flash->mtd.erasesize = info->sector_size;
1011 } 1015 }
1012 1016
1013 if (info->flags & M25P_NO_ERASE) 1017 if (info->flags & M25P_NO_ERASE)
1014 flash->mtd.flags |= MTD_NO_ERASE; 1018 flash->mtd.flags |= MTD_NO_ERASE;
1015 1019
1016 ppdata.of_node = spi->dev.of_node; 1020 ppdata.of_node = spi->dev.of_node;
1017 flash->mtd.dev.parent = &spi->dev; 1021 flash->mtd.dev.parent = &spi->dev;
1018 flash->page_size = info->page_size; 1022 flash->page_size = info->page_size;
1019 flash->mtd.writebufsize = flash->page_size; 1023 flash->mtd.writebufsize = flash->page_size;
1020 1024
1021 flash->fast_read = false; 1025 flash->fast_read = false;
1022 #ifdef CONFIG_OF 1026 #ifdef CONFIG_OF
1023 if (np && of_property_read_bool(np, "m25p,fast-read")) 1027 if (np && of_property_read_bool(np, "m25p,fast-read"))
1024 flash->fast_read = true; 1028 flash->fast_read = true;
1025 #endif 1029 #endif
1026 1030
1027 #ifdef CONFIG_M25PXX_USE_FAST_READ 1031 #ifdef CONFIG_M25PXX_USE_FAST_READ
1028 flash->fast_read = true; 1032 flash->fast_read = true;
1029 #endif 1033 #endif
1030 1034
1031 if (info->addr_width) 1035 if (info->addr_width)
1032 flash->addr_width = info->addr_width; 1036 flash->addr_width = info->addr_width;
1033 else { 1037 else {
1034 /* enable 4-byte addressing if the device exceeds 16MiB */ 1038 /* enable 4-byte addressing if the device exceeds 16MiB */
1035 if (flash->mtd.size > 0x1000000) { 1039 if (flash->mtd.size > 0x1000000) {
1036 flash->addr_width = 4; 1040 flash->addr_width = 4;
1037 set_4byte(flash, info->jedec_id, 1); 1041 set_4byte(flash, info->jedec_id, 1);
1038 } else 1042 } else
1039 flash->addr_width = 3; 1043 flash->addr_width = 3;
1040 } 1044 }
1041 1045
1042 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name, 1046 dev_info(&spi->dev, "%s (%lld Kbytes)\n", id->name,
1043 (long long)flash->mtd.size >> 10); 1047 (long long)flash->mtd.size >> 10);
1044 1048
1045 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) " 1049 pr_debug("mtd .name = %s, .size = 0x%llx (%lldMiB) "
1046 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n", 1050 ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
1047 flash->mtd.name, 1051 flash->mtd.name,
1048 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20), 1052 (long long)flash->mtd.size, (long long)(flash->mtd.size >> 20),
1049 flash->mtd.erasesize, flash->mtd.erasesize / 1024, 1053 flash->mtd.erasesize, flash->mtd.erasesize / 1024,
1050 flash->mtd.numeraseregions); 1054 flash->mtd.numeraseregions);
1051 1055
1052 if (flash->mtd.numeraseregions) 1056 if (flash->mtd.numeraseregions)
1053 for (i = 0; i < flash->mtd.numeraseregions; i++) 1057 for (i = 0; i < flash->mtd.numeraseregions; i++)
1054 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, " 1058 pr_debug("mtd.eraseregions[%d] = { .offset = 0x%llx, "
1055 ".erasesize = 0x%.8x (%uKiB), " 1059 ".erasesize = 0x%.8x (%uKiB), "
1056 ".numblocks = %d }\n", 1060 ".numblocks = %d }\n",
1057 i, (long long)flash->mtd.eraseregions[i].offset, 1061 i, (long long)flash->mtd.eraseregions[i].offset,
1058 flash->mtd.eraseregions[i].erasesize, 1062 flash->mtd.eraseregions[i].erasesize,
1059 flash->mtd.eraseregions[i].erasesize / 1024, 1063 flash->mtd.eraseregions[i].erasesize / 1024,
1060 flash->mtd.eraseregions[i].numblocks); 1064 flash->mtd.eraseregions[i].numblocks);
1061 1065
1062 1066
1063 /* partitions should match sector boundaries; and it may be good to 1067 /* partitions should match sector boundaries; and it may be good to
1064 * use readonly partitions for writeprotected sectors (BP2..BP0). 1068 * use readonly partitions for writeprotected sectors (BP2..BP0).
1065 */ 1069 */
1066 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata, 1070 return mtd_device_parse_register(&flash->mtd, NULL, &ppdata,
1067 data ? data->parts : NULL, 1071 data ? data->parts : NULL,
1068 data ? data->nr_parts : 0); 1072 data ? data->nr_parts : 0);
1069 } 1073 }
1070 1074
1071 1075
1072 static int m25p_remove(struct spi_device *spi) 1076 static int m25p_remove(struct spi_device *spi)
1073 { 1077 {
1074 struct m25p *flash = dev_get_drvdata(&spi->dev); 1078 struct m25p *flash = dev_get_drvdata(&spi->dev);
1075 int status; 1079 int status;
1076 1080
1077 /* Clean up MTD stuff. */ 1081 /* Clean up MTD stuff. */
1078 status = mtd_device_unregister(&flash->mtd); 1082 status = mtd_device_unregister(&flash->mtd);
1079 if (status == 0) { 1083 if (status == 0) {
1080 kfree(flash->command); 1084 kfree(flash->command);
1081 kfree(flash); 1085 kfree(flash);
1082 } 1086 }
1083 return 0; 1087 return 0;
1084 } 1088 }
1085 1089
1086 1090
1087 static struct spi_driver m25p80_driver = { 1091 static struct spi_driver m25p80_driver = {
1088 .driver = { 1092 .driver = {
1089 .name = "m25p80", 1093 .name = "m25p80",
1090 .owner = THIS_MODULE, 1094 .owner = THIS_MODULE,
1091 }, 1095 },
1092 .id_table = m25p_ids, 1096 .id_table = m25p_ids,
1093 .probe = m25p_probe, 1097 .probe = m25p_probe,
1094 .remove = m25p_remove, 1098 .remove = m25p_remove,
1095 1099
1096 /* REVISIT: many of these chips have deep power-down modes, which 1100 /* REVISIT: many of these chips have deep power-down modes, which
1097 * should clearly be entered on suspend() to minimize power use. 1101 * should clearly be entered on suspend() to minimize power use.
1098 * And also when they're otherwise idle... 1102 * And also when they're otherwise idle...
1099 */ 1103 */
1100 }; 1104 };
1101 1105
1102 module_spi_driver(m25p80_driver); 1106 module_spi_driver(m25p80_driver);
1103 1107
1104 MODULE_LICENSE("GPL"); 1108 MODULE_LICENSE("GPL");
1105 MODULE_AUTHOR("Mike Lavender"); 1109 MODULE_AUTHOR("Mike Lavender");
1106 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips"); 1110 MODULE_DESCRIPTION("MTD SPI driver for ST M25Pxx flash chips");
1107 1111