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Commit 592578a1dd1be0c940e36f769acdd3cc6651a7a1

Authored by Richard Retanubun
Committed by Greg Ungerer
1 parent ccc5ff94c6
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

m68knommu: Fixed GPIO pin initialization for CONFIG_M5271 FEC. 

This processor only have one FEC and its MDIO pins are
located at a different offset than the code used for
the current CONFIG_M527x.

Tesed on M5271EVB eval platform.
Without this patch the FEC driver will report no PHY attached
if the bootloader does not pre-initialize the PAR_FECI2C GPIO register.

Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
Signed-off-by: Greg Ungerer <gerg@uclinux.org>

Showing 1 changed file with 5 additions and 0 deletions Side-by-side Diff

arch/m68knommu/platform/527x/config.c
Diff comments   View file @ 592578a
... ... @@ -189,10 +189,15 @@
189 189 m527x_fec_irq_init(0);
190 190  
191 191 /* Set multi-function pins to ethernet mode for fec0 */
  192 +#if defined(CONFIG_M5271)
  193 + v = readb(MCF_IPSBAR + 0x100047);
  194 + writeb(v | 0xf0, MCF_IPSBAR + 0x100047);
  195 +#else
192 196 par = readw(MCF_IPSBAR + 0x100082);
193 197 writew(par | 0xf00, MCF_IPSBAR + 0x100082);
194 198 v = readb(MCF_IPSBAR + 0x100078);
195 199 writeb(v | 0xc0, MCF_IPSBAR + 0x100078);
  200 +#endif
196 201  
197 202 #ifdef CONFIG_FEC2
198 203 m527x_fec_irq_init(1);