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Commit 5dfa9c1b4f5d399a2800d8486ca188988900db87

Authored by Yoichi Yuasa
Committed by Linus Torvalds
1 parent 4bfa437cf1
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

[PATCH] mips: update VR41xx CPU-PCI bridge support 

This patch updates NEC VR4100 series CPU-PCI bridge support.

Signed-off-by: Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

Showing 5 changed files with 181 additions and 142 deletions Side-by-side Diff

arch/mips/pci/ops-vr41xx.c
Diff comments   View file @ 5dfa9c1
... ... @@ -3,7 +3,7 @@
3 3 *
4 4 * Copyright (C) 2001-2003 MontaVista Software Inc.
5 5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6   - * Copyright (C) 2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
  6 + * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
7 7 *
8 8 * This program is free software; you can redistribute it and/or modify
9 9 * it under the terms of the GNU General Public License as published by
... ... @@ -29,8 +29,8 @@
29 29  
30 30 #include <asm/io.h>
31 31  
32   -#define PCICONFDREG KSEG1ADDR(0x0f000c14)
33   -#define PCICONFAREG KSEG1ADDR(0x0f000c18)
  32 +#define PCICONFDREG (void __iomem *)KSEG1ADDR(0x0f000c14)
  33 +#define PCICONFAREG (void __iomem *)KSEG1ADDR(0x0f000c18)
34 34  
35 35 static inline int set_pci_configuration_address(unsigned char number,
36 36 unsigned int devfn, int where)
arch/mips/pci/pci-vr41xx.c
Diff comments   View file @ 5dfa9c1
... ... @@ -3,8 +3,8 @@
3 3 *
4 4 * Copyright (C) 2001-2003 MontaVista Software Inc.
5 5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6   - * Copyright (C) 2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
7   - * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
  6 + * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
  7 + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
8 8 *
9 9 * This program is free software; you can redistribute it and/or modify
10 10 * it under the terms of the GNU General Public License as published by
11 11  
... ... @@ -31,12 +31,18 @@
31 31  
32 32 #include <asm/cpu.h>
33 33 #include <asm/io.h>
  34 +#include <asm/vr41xx/pci.h>
34 35 #include <asm/vr41xx/vr41xx.h>
35 36  
36 37 #include "pci-vr41xx.h"
37 38  
38 39 extern struct pci_ops vr41xx_pci_ops;
39 40  
  41 +static void __iomem *pciu_base;
  42 +
  43 +#define pciu_read(offset) readl(pciu_base + (offset))
  44 +#define pciu_write(offset, value) writel((value), pciu_base + (offset))
  45 +
40 46 static struct pci_master_address_conversion pci_master_memory1 = {
41 47 .bus_base_address = PCI_MASTER_MEM1_BUS_BASE_ADDRESS,
42 48 .address_mask = PCI_MASTER_MEM1_ADDRESS_MASK,
... ... @@ -113,6 +119,15 @@
113 119  
114 120 setup = &vr41xx_pci_controller_unit_setup;
115 121  
  122 + if (request_mem_region(PCIU_BASE, PCIU_SIZE, "PCIU") == NULL)
  123 + return -EBUSY;
  124 +
  125 + pciu_base = ioremap(PCIU_BASE, PCIU_SIZE);
  126 + if (pciu_base == NULL) {
  127 + release_mem_region(PCIU_BASE, PCIU_SIZE);
  128 + return -EBUSY;
  129 + }
  130 +
116 131 /* Disable PCI interrupt */
117 132 vr41xx_disable_pciint();
118 133  
119 134  
120 135  
121 136  
... ... @@ -129,14 +144,14 @@
129 144 pci_clock_max = PCI_CLOCK_MAX;
130 145 vtclock = vr41xx_get_vtclock_frequency();
131 146 if (vtclock < pci_clock_max)
132   - writel(EQUAL_VTCLOCK, PCICLKSELREG);
  147 + pciu_write(PCICLKSELREG, EQUAL_VTCLOCK);
133 148 else if ((vtclock / 2) < pci_clock_max)
134   - writel(HALF_VTCLOCK, PCICLKSELREG);
  149 + pciu_write(PCICLKSELREG, HALF_VTCLOCK);
135 150 else if (current_cpu_data.processor_id >= PRID_VR4131_REV2_1 &&
136 151 (vtclock / 3) < pci_clock_max)
137   - writel(ONE_THIRD_VTCLOCK, PCICLKSELREG);
  152 + pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);
138 153 else if ((vtclock / 4) < pci_clock_max)
139   - writel(QUARTER_VTCLOCK, PCICLKSELREG);
  154 + pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);
140 155 else {
141 156 printk(KERN_ERR "PCI Clock is over 33MHz.\n");
142 157 return -EINVAL;
143 158  
144 159  
... ... @@ -151,11 +166,11 @@
151 166 MASTER_MSK(master->address_mask) |
152 167 WINEN |
153 168 PCIA(master->pci_base_address);
154   - writel(val, PCIMMAW1REG);
  169 + pciu_write(PCIMMAW1REG, val);
155 170 } else {
156   - val = readl(PCIMMAW1REG);
  171 + val = pciu_read(PCIMMAW1REG);
157 172 val &= ~WINEN;
158   - writel(val, PCIMMAW1REG);
  173 + pciu_write(PCIMMAW1REG, val);
159 174 }
160 175  
161 176 if (setup->master_memory2 != NULL) {
162 177  
163 178  
... ... @@ -164,11 +179,11 @@
164 179 MASTER_MSK(master->address_mask) |
165 180 WINEN |
166 181 PCIA(master->pci_base_address);
167   - writel(val, PCIMMAW2REG);
  182 + pciu_write(PCIMMAW2REG, val);
168 183 } else {
169   - val = readl(PCIMMAW2REG);
  184 + val = pciu_read(PCIMMAW2REG);
170 185 val &= ~WINEN;
171   - writel(val, PCIMMAW2REG);
  186 + pciu_write(PCIMMAW2REG, val);
172 187 }
173 188  
174 189 if (setup->target_memory1 != NULL) {
175 190  
176 191  
... ... @@ -176,11 +191,11 @@
176 191 val = TARGET_MSK(target->address_mask) |
177 192 WINEN |
178 193 ITA(target->bus_base_address);
179   - writel(val, PCITAW1REG);
  194 + pciu_write(PCITAW1REG, val);
180 195 } else {
181   - val = readl(PCITAW1REG);
  196 + val = pciu_read(PCITAW1REG);
182 197 val &= ~WINEN;
183   - writel(val, PCITAW1REG);
  198 + pciu_write(PCITAW1REG, val);
184 199 }
185 200  
186 201 if (setup->target_memory2 != NULL) {
187 202  
188 203  
... ... @@ -188,11 +203,11 @@
188 203 val = TARGET_MSK(target->address_mask) |
189 204 WINEN |
190 205 ITA(target->bus_base_address);
191   - writel(val, PCITAW2REG);
  206 + pciu_write(PCITAW2REG, val);
192 207 } else {
193   - val = readl(PCITAW2REG);
  208 + val = pciu_read(PCITAW2REG);
194 209 val &= ~WINEN;
195   - writel(val, PCITAW2REG);
  210 + pciu_write(PCITAW2REG, val);
196 211 }
197 212  
198 213 if (setup->master_io != NULL) {
199 214  
200 215  
201 216  
202 217  
203 218  
204 219  
205 220  
206 221  
207 222  
208 223  
209 224  
210 225  
... ... @@ -201,50 +216,50 @@
201 216 MASTER_MSK(master->address_mask) |
202 217 WINEN |
203 218 PCIIA(master->pci_base_address);
204   - writel(val, PCIMIOAWREG);
  219 + pciu_write(PCIMIOAWREG, val);
205 220 } else {
206   - val = readl(PCIMIOAWREG);
  221 + val = pciu_read(PCIMIOAWREG);
207 222 val &= ~WINEN;
208   - writel(val, PCIMIOAWREG);
  223 + pciu_write(PCIMIOAWREG, val);
209 224 }
210 225  
211 226 if (setup->exclusive_access == CANNOT_LOCK_FROM_DEVICE)
212   - writel(UNLOCK, PCIEXACCREG);
  227 + pciu_write(PCIEXACCREG, UNLOCK);
213 228 else
214   - writel(0, PCIEXACCREG);
  229 + pciu_write(PCIEXACCREG, 0);
215 230  
216 231 if (current_cpu_data.cputype == CPU_VR4122)
217   - writel(TRDYV(setup->wait_time_limit_from_irdy_to_trdy), PCITRDYVREG);
  232 + pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy));
218 233  
219   - writel(MLTIM(setup->master_latency_timer), LATTIMEREG);
  234 + pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer));
220 235  
221 236 if (setup->mailbox != NULL) {
222 237 mailbox = setup->mailbox;
223 238 val = MBADD(mailbox->base_address) | TYPE_32BITSPACE |
224 239 MSI_MEMORY | PREF_APPROVAL;
225   - writel(val, MAILBAREG);
  240 + pciu_write(MAILBAREG, val);
226 241 }
227 242  
228 243 if (setup->target_window1) {
229 244 window = setup->target_window1;
230 245 val = PMBA(window->base_address) | TYPE_32BITSPACE |
231 246 MSI_MEMORY | PREF_APPROVAL;
232   - writel(val, PCIMBA1REG);
  247 + pciu_write(PCIMBA1REG, val);
233 248 }
234 249  
235 250 if (setup->target_window2) {
236 251 window = setup->target_window2;
237 252 val = PMBA(window->base_address) | TYPE_32BITSPACE |
238 253 MSI_MEMORY | PREF_APPROVAL;
239   - writel(val, PCIMBA2REG);
  254 + pciu_write(PCIMBA2REG, val);
240 255 }
241 256  
242   - val = readl(RETVALREG);
  257 + val = pciu_read(RETVALREG);
243 258 val &= ~RTYVAL_MASK;
244 259 val |= RTYVAL(setup->retry_limit);
245   - writel(val, RETVALREG);
  260 + pciu_write(RETVALREG, val);
246 261  
247   - val = readl(PCIAPCNTREG);
  262 + val = pciu_read(PCIAPCNTREG);
248 263 val &= ~(TKYGNT | PAPC);
249 264  
250 265 switch (setup->arbiter_priority_control) {
251 266  
252 267  
253 268  
... ... @@ -262,15 +277,16 @@
262 277 if (setup->take_away_gnt_mode == PCI_TAKE_AWAY_GNT_ENABLE)
263 278 val |= TKYGNT_ENABLE;
264 279  
265   - writel(val, PCIAPCNTREG);
  280 + pciu_write(PCIAPCNTREG, val);
266 281  
267   - writel(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
268   - PCI_COMMAND_PARITY | PCI_COMMAND_SERR, COMMANDREG);
  282 + pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
  283 + PCI_COMMAND_MASTER | PCI_COMMAND_PARITY |
  284 + PCI_COMMAND_SERR);
269 285  
270 286 /* Clear bus error */
271   - readl(BUSERRADREG);
  287 + pciu_read(BUSERRADREG);
272 288  
273   - writel(BLOODY_CONFIG_DONE, PCIENREG);
  289 + pciu_write(PCIENREG, PCIU_CONFIG_DONE);
274 290  
275 291 if (setup->mem_resource != NULL)
276 292 vr41xx_pci_controller.mem_resource = setup->mem_resource;
arch/mips/pci/pci-vr41xx.h
Diff comments   View file @ 5dfa9c1
... ... @@ -3,7 +3,7 @@
3 3 *
4 4 * Copyright (C) 2002 MontaVista Software Inc.
5 5 * Author: Yoichi Yuasa <yyuasa@mvista.com or source@mvista.com>
6   - * Copyright (C) 2004 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
  6 + * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
7 7 *
8 8 * This program is free software; you can redistribute it and/or modify
9 9 * it under the terms of the GNU General Public License as published by
... ... @@ -22,11 +22,14 @@
22 22 #ifndef __PCI_VR41XX_H
23 23 #define __PCI_VR41XX_H
24 24  
25   -#define PCIMMAW1REG KSEG1ADDR(0x0f000c00)
26   -#define PCIMMAW2REG KSEG1ADDR(0x0f000c04)
27   -#define PCITAW1REG KSEG1ADDR(0x0f000c08)
28   -#define PCITAW2REG KSEG1ADDR(0x0f000c0c)
29   -#define PCIMIOAWREG KSEG1ADDR(0x0f000c10)
  25 +#define PCIU_BASE 0x0f000c00UL
  26 +#define PCIU_SIZE 0x200UL
  27 +
  28 +#define PCIMMAW1REG 0x00
  29 +#define PCIMMAW2REG 0x04
  30 +#define PCITAW1REG 0x08
  31 +#define PCITAW2REG 0x0c
  32 +#define PCIMIOAWREG 0x10
30 33 #define IBA(addr) ((addr) & 0xff000000U)
31 34 #define MASTER_MSK(mask) (((mask) >> 11) & 0x000fe000U)
32 35 #define PCIA(addr) (((addr) >> 24) & 0x000000ffU)
33 36  
... ... @@ -34,13 +37,13 @@
34 37 #define ITA(addr) (((addr) >> 24) & 0x000000ffU)
35 38 #define PCIIA(addr) (((addr) >> 24) & 0x000000ffU)
36 39 #define WINEN 0x1000U
37   -#define PCICONFDREG KSEG1ADDR(0x0f000c14)
38   -#define PCICONFAREG KSEG1ADDR(0x0f000c18)
39   -#define PCIMAILREG KSEG1ADDR(0x0f000c1c)
40   -#define BUSERRADREG KSEG1ADDR(0x0f000c24)
  40 +#define PCICONFDREG 0x14
  41 +#define PCICONFAREG 0x18
  42 +#define PCIMAILREG 0x1c
  43 +#define BUSERRADREG 0x24
41 44 #define EA(reg) ((reg) &0xfffffffc)
42 45  
43   -#define INTCNTSTAREG KSEG1ADDR(0x0f000c28)
  46 +#define INTCNTSTAREG 0x28
44 47 #define MABTCLR 0x80000000U
45 48 #define TRDYCLR 0x40000000U
46 49 #define PARCLR 0x20000000U
47 50  
48 51  
49 52  
50 53  
51 54  
52 55  
... ... @@ -67,34 +70,34 @@
67 70 #define MABORT 0x00000002U
68 71 #define TABORT 0x00000001U
69 72  
70   -#define PCIEXACCREG KSEG1ADDR(0x0f000c2c)
  73 +#define PCIEXACCREG 0x2c
71 74 #define UNLOCK 0x2U
72 75 #define EAREQ 0x1U
73   -#define PCIRECONTREG KSEG1ADDR(0x0f000c30)
  76 +#define PCIRECONTREG 0x30
74 77 #define RTRYCNT(reg) ((reg) & 0x000000ffU)
75   -#define PCIENREG KSEG1ADDR(0x0f000c34)
76   - #define BLOODY_CONFIG_DONE 0x4U
77   -#define PCICLKSELREG KSEG1ADDR(0x0f000c38)
  78 +#define PCIENREG 0x34
  79 + #define PCIU_CONFIG_DONE 0x4U
  80 +#define PCICLKSELREG 0x38
78 81 #define EQUAL_VTCLOCK 0x2U
79 82 #define HALF_VTCLOCK 0x0U
80 83 #define ONE_THIRD_VTCLOCK 0x3U
81 84 #define QUARTER_VTCLOCK 0x1U
82   -#define PCITRDYVREG KSEG1ADDR(0x0f000c3c)
  85 +#define PCITRDYVREG 0x3c
83 86 #define TRDYV(val) ((uint32_t)(val) & 0xffU)
84   -#define PCICLKRUNREG KSEG1ADDR(0x0f000c60)
  87 +#define PCICLKRUNREG 0x60
85 88  
86   -#define VENDORIDREG KSEG1ADDR(0x0f000d00)
87   -#define DEVICEIDREG KSEG1ADDR(0x0f000d00)
88   -#define COMMANDREG KSEG1ADDR(0x0f000d04)
89   -#define STATUSREG KSEG1ADDR(0x0f000d04)
90   -#define REVIDREG KSEG1ADDR(0x0f000d08)
91   -#define CLASSREG KSEG1ADDR(0x0f000d08)
92   -#define CACHELSREG KSEG1ADDR(0x0f000d0c)
93   -#define LATTIMEREG KSEG1ADDR(0x0f000d0c)
  89 +#define VENDORIDREG 0x100
  90 +#define DEVICEIDREG 0x100
  91 +#define COMMANDREG 0x104
  92 +#define STATUSREG 0x104
  93 +#define REVIDREG 0x108
  94 +#define CLASSREG 0x108
  95 +#define CACHELSREG 0x10c
  96 +#define LATTIMEREG 0x10c
94 97 #define MLTIM(val) (((uint32_t)(val) << 7) & 0xff00U)
95   -#define MAILBAREG KSEG1ADDR(0x0f000d10)
96   -#define PCIMBA1REG KSEG1ADDR(0x0f000d14)
97   -#define PCIMBA2REG KSEG1ADDR(0x0f000d18)
  98 +#define MAILBAREG 0x110
  99 +#define PCIMBA1REG 0x114
  100 +#define PCIMBA2REG 0x118
98 101 #define MBADD(base) ((base) & 0xfffff800U)
99 102 #define PMBA(base) ((base) & 0xffe00000U)
100 103 #define PREF 0x8U
... ... @@ -104,10 +107,10 @@
104 107 #define TYPE_32BITSPACE 0x0U
105 108 #define MSI 0x1U
106 109 #define MSI_MEMORY 0x0U
107   -#define INTLINEREG KSEG1ADDR(0x0f000d3c)
108   -#define INTPINREG KSEG1ADDR(0x0f000d3c)
109   -#define RETVALREG KSEG1ADDR(0x0f000d40)
110   -#define PCIAPCNTREG KSEG1ADDR(0x0f000d40)
  110 +#define INTLINEREG 0x13c
  111 +#define INTPINREG 0x13c
  112 +#define RETVALREG 0x140
  113 +#define PCIAPCNTREG 0x140
111 114 #define TKYGNT 0x04000000U
112 115 #define TKYGNT_ENABLE 0x04000000U
113 116 #define TKYGNT_DISABLE 0x00000000U
include/asm-mips/vr41xx/pci.h
Diff comments   View file @ 5dfa9c1
  1 +/*
  2 + * Include file for NEC VR4100 series PCI Control Unit.
  3 + *
  4 + * Copyright (C) 2004-2005 Yoichi Yuasa <yuasa@hh.iij4u.or.jp>
  5 + *
  6 + * This program is free software; you can redistribute it and/or modify
  7 + * it under the terms of the GNU General Public License as published by
  8 + * the Free Software Foundation; either version 2 of the License, or
  9 + * (at your option) any later version.
  10 + *
  11 + * This program is distributed in the hope that it will be useful,
  12 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14 + * GNU General Public License for more details.
  15 + *
  16 + * You should have received a copy of the GNU General Public License
  17 + * along with this program; if not, write to the Free Software
  18 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  19 + */
  20 +#ifndef __NEC_VR41XX_PCI_H
  21 +#define __NEC_VR41XX_PCI_H
  22 +
  23 +#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
  24 +
  25 +struct pci_master_address_conversion {
  26 + uint32_t bus_base_address;
  27 + uint32_t address_mask;
  28 + uint32_t pci_base_address;
  29 +};
  30 +
  31 +struct pci_target_address_conversion {
  32 + uint32_t address_mask;
  33 + uint32_t bus_base_address;
  34 +};
  35 +
  36 +typedef enum {
  37 + CANNOT_LOCK_FROM_DEVICE,
  38 + CAN_LOCK_FROM_DEVICE,
  39 +} pci_exclusive_access_t;
  40 +
  41 +struct pci_mailbox_address {
  42 + uint32_t base_address;
  43 +};
  44 +
  45 +struct pci_target_address_window {
  46 + uint32_t base_address;
  47 +};
  48 +
  49 +typedef enum {
  50 + PCI_ARBITRATION_MODE_FAIR,
  51 + PCI_ARBITRATION_MODE_ALTERNATE_0,
  52 + PCI_ARBITRATION_MODE_ALTERNATE_B,
  53 +} pci_arbiter_priority_control_t;
  54 +
  55 +typedef enum {
  56 + PCI_TAKE_AWAY_GNT_DISABLE,
  57 + PCI_TAKE_AWAY_GNT_ENABLE,
  58 +} pci_take_away_gnt_mode_t;
  59 +
  60 +struct pci_controller_unit_setup {
  61 + struct pci_master_address_conversion *master_memory1;
  62 + struct pci_master_address_conversion *master_memory2;
  63 +
  64 + struct pci_target_address_conversion *target_memory1;
  65 + struct pci_target_address_conversion *target_memory2;
  66 +
  67 + struct pci_master_address_conversion *master_io;
  68 +
  69 + pci_exclusive_access_t exclusive_access;
  70 +
  71 + uint32_t pci_clock_max;
  72 + uint8_t wait_time_limit_from_irdy_to_trdy; /* Only VR4122 is supported */
  73 +
  74 + struct pci_mailbox_address *mailbox;
  75 + struct pci_target_address_window *target_window1;
  76 + struct pci_target_address_window *target_window2;
  77 +
  78 + uint8_t master_latency_timer;
  79 + uint8_t retry_limit;
  80 +
  81 + pci_arbiter_priority_control_t arbiter_priority_control;
  82 + pci_take_away_gnt_mode_t take_away_gnt_mode;
  83 +
  84 + struct resource *mem_resource;
  85 + struct resource *io_resource;
  86 +};
  87 +
  88 +extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
  89 +
  90 +#endif /* __NEC_VR41XX_PCI_H */
include/asm-mips/vr41xx/vr41xx.h
Diff comments   View file @ 5dfa9c1
... ... @@ -231,75 +231,5 @@
231 231 DATA_HIGH
232 232 };
233 233  
234   -/*
235   - * PCI Control Unit
236   - */
237   -#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
238   -
239   -struct pci_master_address_conversion {
240   - uint32_t bus_base_address;
241   - uint32_t address_mask;
242   - uint32_t pci_base_address;
243   -};
244   -
245   -struct pci_target_address_conversion {
246   - uint32_t address_mask;
247   - uint32_t bus_base_address;
248   -};
249   -
250   -typedef enum {
251   - CANNOT_LOCK_FROM_DEVICE,
252   - CAN_LOCK_FROM_DEVICE,
253   -} pci_exclusive_access_t;
254   -
255   -struct pci_mailbox_address {
256   - uint32_t base_address;
257   -};
258   -
259   -struct pci_target_address_window {
260   - uint32_t base_address;
261   -};
262   -
263   -typedef enum {
264   - PCI_ARBITRATION_MODE_FAIR,
265   - PCI_ARBITRATION_MODE_ALTERNATE_0,
266   - PCI_ARBITRATION_MODE_ALTERNATE_B,
267   -} pci_arbiter_priority_control_t;
268   -
269   -typedef enum {
270   - PCI_TAKE_AWAY_GNT_DISABLE,
271   - PCI_TAKE_AWAY_GNT_ENABLE,
272   -} pci_take_away_gnt_mode_t;
273   -
274   -struct pci_controller_unit_setup {
275   - struct pci_master_address_conversion *master_memory1;
276   - struct pci_master_address_conversion *master_memory2;
277   -
278   - struct pci_target_address_conversion *target_memory1;
279   - struct pci_target_address_conversion *target_memory2;
280   -
281   - struct pci_master_address_conversion *master_io;
282   -
283   - pci_exclusive_access_t exclusive_access;
284   -
285   - uint32_t pci_clock_max;
286   - uint8_t wait_time_limit_from_irdy_to_trdy; /* Only VR4122 is supported */
287   -
288   - struct pci_mailbox_address *mailbox;
289   - struct pci_target_address_window *target_window1;
290   - struct pci_target_address_window *target_window2;
291   -
292   - uint8_t master_latency_timer;
293   - uint8_t retry_limit;
294   -
295   - pci_arbiter_priority_control_t arbiter_priority_control;
296   - pci_take_away_gnt_mode_t take_away_gnt_mode;
297   -
298   - struct resource *mem_resource;
299   - struct resource *io_resource;
300   -};
301   -
302   -extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
303   -
304 234 #endif /* __NEC_VR41XX_H */