tile PCI RC: add comment about "PCI hole" problem

Explain the rationale of not overlapping the 64-bit DMA window with the PA range. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>

tile PCI RC: add comment about "PCI hole" problem
Explain the rationale of not overlapping the 64-bit DMA window with the PA range. Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Chris Metcalf
1 parent bdb8205455
Showing 1 changed file with 5 additions and 0 deletions Side-by-side Diff
arch/tile/include/asm/pci.h
@@ -122,6 +122,11 @@
  * the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit
  * devices, we create a separate map region that handles the low
  * 4GB.
+ *
+ * This design lets us avoid the "PCI hole" problem where the host bridge
+ * won't pass DMA traffic with target addresses that happen to fall within the
+ * BAR space. This enables us to use all the physical memory for DMA, instead
+ * of wasting the same amount of physical memory as the BAR window size.
  */
 #define	TILE_PCI_MEM_MAP_BASE_OFFSET	(1ULL << CHIP_PA_WIDTH())
...	...	@@ -122,6 +122,11 @@
122	122	* the CPA plus TILE_PCI_MEM_MAP_BASE_OFFSET. To support 32-bit
123	123	* devices, we create a separate map region that handles the low
124	124	* 4GB.
	125	+ *
	126	+ * This design lets us avoid the "PCI hole" problem where the host bridge
	127	+ * won't pass DMA traffic with target addresses that happen to fall within the
	128	+ * BAR space. This enables us to use all the physical memory for DMA, instead
	129	+ * of wasting the same amount of physical memory as the BAR window size.
125	130	*/
126	131	#define TILE_PCI_MEM_MAP_BASE_OFFSET (1ULL << CHIP_PA_WIDTH())
127	132