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Commit 5ed338778f917a035f0f0a52327fc4f72e36f7a1

Authored by Shengzhou Liu
Committed by Greg Kroah-Hartman
1 parent 54575b05af
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

powerpc/usb: remove checking PHY_CLK_VALID for UTMI PHY 

PHY_CLK_VALID bit doesn't work properly with UTMI PHY.
e.g. This bit is always zero on P5040, etc.
There is no need to check this bit for UTMI PHY, just keep
checking for ULPI PHY to prevent system hanging.

This patch should be squashed into previous commit 3735ba8db8e6e
"powerpc/usb: fix bug of CPU hang when missing USB PHY clock"

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Showing 2 changed files with 2 additions and 3 deletions Side-by-side Diff

drivers/usb/host/ehci-fsl.c
Diff comments   View file @ 5ed3387
... ... @@ -267,8 +267,7 @@
267 267 break;
268 268 }
269 269  
270   - if ((pdata->controller_ver) && ((phy_mode == FSL_USB2_PHY_ULPI) ||
271   - (phy_mode == FSL_USB2_PHY_UTMI))) {
  270 + if (pdata->controller_ver && (phy_mode == FSL_USB2_PHY_ULPI)) {
272 271 /* check PHY_CLK_VALID to get phy clk valid */
273 272 if (!spin_event_timeout(in_be32(non_ehci + FSL_SOC_USB_CTRL) &
274 273 PHY_CLK_VALID, FSL_USB_PHY_CLK_TIMEOUT, 0)) {
include/linux/fsl_devices.h
Diff comments   View file @ 5ed3387
... ... @@ -19,7 +19,7 @@
19 19  
20 20 #define FSL_UTMI_PHY_DLY 10 /*As per P1010RM, delay for UTMI
21 21 PHY CLK to become stable - 10ms*/
22   -#define FSL_USB_PHY_CLK_TIMEOUT 1000 /* uSec */
  22 +#define FSL_USB_PHY_CLK_TIMEOUT 10000 /* uSec */
23 23 #define FSL_USB_VER_OLD 0
24 24 #define FSL_USB_VER_1_6 1
25 25 #define FSL_USB_VER_2_2 2