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Commit 63c2b6812f1dc0beda4d6adad0365e048aa693e2

Authored by Florian Fainelli
Committed by Ralf Baechle
1 parent a4285b99e0
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

MIPS: Fix code generation for non-DSP capable CPUs 

Commit 32a7ede (MIPS: dsp: Add assembler support for DSP ASEs) has
enabled the use of DSP ASE specific instructions such as rddsp and wrdsp
under the idea that all code path that will make use of these two
instructions are properly checking for cpu_has_dsp to ensure that the
particular CPU we are running on *actually* supports DSP ASE.

This commit actually causes the following oops on QEMU Malta emulating a
MIPS 24Kc without the DSP ASE implemented:

[    7.960000] Reserved instruction in kernel
[    7.960000] Cpu 0
[    7.960000] $ 0   : 00000000 00000000 00000014 00000005
[    7.960000] $ 4   : 8fc2de48 00000001 00000000 8f59ddb0
[    7.960000] $ 8   : 8f5ceec4 00000018 00000c00 00800000
[    7.960000] $12   : 00000100 00000200 00000000 00457b84
[    7.960000] $16   : 00000000 8fc2ba78 8f4ec980 00000001
[    7.960000] $20   : 80418f90 00000000 00000000 000002dd
[    7.960000] $24   : 0000009c 7730d7b8
[    7.960000] $28   : 8f59c000 8f59dd38 00000001 80104248
[    7.960000] Hi    : 0000001d
[    7.960000] Lo    : 0000000b
[    7.960000] epc   : 801041ec thread_saved_pc+0x2c/0x38
[    7.960000]     Not tainted
[    7.960000] ra    : 80104248 get_wchan+0x48/0xac
[    7.960000] Status: 1000b703    KERNEL EXL IE
[    7.960000] Cause : 10800028
[    7.960000] PrId  : 00019300 (MIPS 24Kc)
[    7.960000] Modules linked in:
[    7.960000] Process killall (pid: 1574, threadinfo=8f59c000,
task=8fd14558, tls=773aa440)
[    7.960000] Stack : 8fc2ba78 8012b008 0000000c 0000001d 00000000
00000000 8f58a380
                  8f58a380 8fc2ba78 80202668 8f59de78 8f468600 8f59de28
801b2a3c 8f59df00 8f98ba20 74696e69
                  8f468600 8f59de28 801b7308 0081c007 00000000 00000000
00000000 00000000 00000000 00000000
                  00000000 8fc2bbb4 00000001 0000001d 0000000b 77f038cc
7fe80648 ffffffff ffffffff 00000000
                  00000001 0016e000 00000000 ...
[    7.960000] Call Trace:
[    7.960000] [<801041ec>] thread_saved_pc+0x2c/0x38
[    7.960000] [<80104248>] get_wchan+0x48/0xac

The disassembly of thread_saved_pc points to the following:
000006d0 <thread_saved_pc>:
 6d0:   8c820208        lw      v0,520(a0)
 6d4:   3c030000        lui     v1,0x0
 6d8:   24630000        addiu   v1,v1,0
 6dc:   10430008        beq     v0,v1,700 <thread_saved_pc+0x30>
 6e0:   00000000        nop
 6e4:   3c020000        lui     v0,0x0
 6e8:   8c43000c        lw      v1,12(v0)
 6ec:   04620004        bltzl   v1,700 <thread_saved_pc+0x30>
 6f0:   00001021        move    v0,zero
 6f4:   8c840200        lw      a0,512(a0)
 6f8:   00031080        sll     v0,v1,0x2
 6fc:   7c44100a        lwx     v0,a0(v0)   <------------
 700:   03e00008        jr      ra
 704:   00000000        nop

If we specifically disable -mdsp/-mdspr2 for arch/mips/kernel/process.o,
we get the following (non-crashing) assembly:

00000708 <thread_saved_pc>:
 708:   8c820208        lw      v0,520(a0)
 70c:   3c030000        lui     v1,0x0
 710:   24630000        addiu   v1,v1,0
 714:   10430009        beq     v0,v1,73c <thread_saved_pc+0x34>
 718:   00000000        nop
 71c:   3c020000        lui     v0,0x0
 720:   8c42000c        lw      v0,12(v0)
 724:   04420005        bltzl   v0,73c <thread_saved_pc+0x34>
 728:   00001021        move    v0,zero
 72c:   8c830200        lw      v1,512(a0)
 730:   00021080        sll     v0,v0,0x2
 734:   00431021        addu    v0,v0,v1
 738:   8c420000        lw      v0,0(v0)
 73c:   03e00008        jr      ra
 740:   00000000        nop

The specific line that leads a different assembly being produced is:

unsigned long thread_saved_pc(struct task_struct *tsk)
...
	return ((unsigned long *)t->reg29)[schedule_mfi.pc_offset]; <---

The problem here is that the compiler was given the right to use DSP
instructions with the -mdsp / -mdspr2 command-line switches and
performed some optimization for us and used DSP ASE instructions where
we are not checking that the running CPU actually supports DSP ASE.

This patch fixes the issue by partially reverting commit 32a7ede for
arch/mips/kernel/Makefile in order to remove the -mdsp / -mdspr2
compiler command-line switches such that we are now guaranteed that the
compiler will not optimize using DSP ASE reserved instructions. We also
need to fixup the rddsp/wrdsp and m{t,h}{hi,lo}{0,1,2,3} macros in
arch/mips/include/asm/mipsregs.h to tell the assembler that we are going
to explicitely use DSP ASE reserved instructions. The comment in
arch/mips/kernel/Makefile is also updated to reflect that.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
Acked-by: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: blogic@openwrt.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 2 changed files with 196 additions and 38 deletions Inline Diff

arch/mips/include/asm/mipsregs.h
Diff comments   View file @ 63c2b68
1 /* 1 /*
2 * This file is subject to the terms and conditions of the GNU General Public 2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle 6 * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
7 * Copyright (C) 2000 Silicon Graphics, Inc. 7 * Copyright (C) 2000 Silicon Graphics, Inc.
8 * Modified for further R[236]000 support by Paul M. Antoine, 1996. 8 * Modified for further R[236]000 support by Paul M. Antoine, 1996.
9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com 9 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
10 * Copyright (C) 2000, 07 MIPS Technologies, Inc. 10 * Copyright (C) 2000, 07 MIPS Technologies, Inc.
11 * Copyright (C) 2003, 2004 Maciej W. Rozycki 11 * Copyright (C) 2003, 2004 Maciej W. Rozycki
12 */ 12 */
13 #ifndef _ASM_MIPSREGS_H 13 #ifndef _ASM_MIPSREGS_H
14 #define _ASM_MIPSREGS_H 14 #define _ASM_MIPSREGS_H
15 15
16 #include <linux/linkage.h> 16 #include <linux/linkage.h>
17 #include <asm/hazards.h> 17 #include <asm/hazards.h>
18 #include <asm/war.h> 18 #include <asm/war.h>
19 19
20 /* 20 /*
21 * The following macros are especially useful for __asm__ 21 * The following macros are especially useful for __asm__
22 * inline assembler. 22 * inline assembler.
23 */ 23 */
24 #ifndef __STR 24 #ifndef __STR
25 #define __STR(x) #x 25 #define __STR(x) #x
26 #endif 26 #endif
27 #ifndef STR 27 #ifndef STR
28 #define STR(x) __STR(x) 28 #define STR(x) __STR(x)
29 #endif 29 #endif
30 30
31 /* 31 /*
32 * Configure language 32 * Configure language
33 */ 33 */
34 #ifdef __ASSEMBLY__ 34 #ifdef __ASSEMBLY__
35 #define _ULCAST_ 35 #define _ULCAST_
36 #else 36 #else
37 #define _ULCAST_ (unsigned long) 37 #define _ULCAST_ (unsigned long)
38 #endif 38 #endif
39 39
40 /* 40 /*
41 * Coprocessor 0 register names 41 * Coprocessor 0 register names
42 */ 42 */
43 #define CP0_INDEX $0 43 #define CP0_INDEX $0
44 #define CP0_RANDOM $1 44 #define CP0_RANDOM $1
45 #define CP0_ENTRYLO0 $2 45 #define CP0_ENTRYLO0 $2
46 #define CP0_ENTRYLO1 $3 46 #define CP0_ENTRYLO1 $3
47 #define CP0_CONF $3 47 #define CP0_CONF $3
48 #define CP0_CONTEXT $4 48 #define CP0_CONTEXT $4
49 #define CP0_PAGEMASK $5 49 #define CP0_PAGEMASK $5
50 #define CP0_WIRED $6 50 #define CP0_WIRED $6
51 #define CP0_INFO $7 51 #define CP0_INFO $7
52 #define CP0_BADVADDR $8 52 #define CP0_BADVADDR $8
53 #define CP0_COUNT $9 53 #define CP0_COUNT $9
54 #define CP0_ENTRYHI $10 54 #define CP0_ENTRYHI $10
55 #define CP0_COMPARE $11 55 #define CP0_COMPARE $11
56 #define CP0_STATUS $12 56 #define CP0_STATUS $12
57 #define CP0_CAUSE $13 57 #define CP0_CAUSE $13
58 #define CP0_EPC $14 58 #define CP0_EPC $14
59 #define CP0_PRID $15 59 #define CP0_PRID $15
60 #define CP0_CONFIG $16 60 #define CP0_CONFIG $16
61 #define CP0_LLADDR $17 61 #define CP0_LLADDR $17
62 #define CP0_WATCHLO $18 62 #define CP0_WATCHLO $18
63 #define CP0_WATCHHI $19 63 #define CP0_WATCHHI $19
64 #define CP0_XCONTEXT $20 64 #define CP0_XCONTEXT $20
65 #define CP0_FRAMEMASK $21 65 #define CP0_FRAMEMASK $21
66 #define CP0_DIAGNOSTIC $22 66 #define CP0_DIAGNOSTIC $22
67 #define CP0_DEBUG $23 67 #define CP0_DEBUG $23
68 #define CP0_DEPC $24 68 #define CP0_DEPC $24
69 #define CP0_PERFORMANCE $25 69 #define CP0_PERFORMANCE $25
70 #define CP0_ECC $26 70 #define CP0_ECC $26
71 #define CP0_CACHEERR $27 71 #define CP0_CACHEERR $27
72 #define CP0_TAGLO $28 72 #define CP0_TAGLO $28
73 #define CP0_TAGHI $29 73 #define CP0_TAGHI $29
74 #define CP0_ERROREPC $30 74 #define CP0_ERROREPC $30
75 #define CP0_DESAVE $31 75 #define CP0_DESAVE $31
76 76
77 /* 77 /*
78 * R4640/R4650 cp0 register names. These registers are listed 78 * R4640/R4650 cp0 register names. These registers are listed
79 * here only for completeness; without MMU these CPUs are not useable 79 * here only for completeness; without MMU these CPUs are not useable
80 * by Linux. A future ELKS port might take make Linux run on them 80 * by Linux. A future ELKS port might take make Linux run on them
81 * though ... 81 * though ...
82 */ 82 */
83 #define CP0_IBASE $0 83 #define CP0_IBASE $0
84 #define CP0_IBOUND $1 84 #define CP0_IBOUND $1
85 #define CP0_DBASE $2 85 #define CP0_DBASE $2
86 #define CP0_DBOUND $3 86 #define CP0_DBOUND $3
87 #define CP0_CALG $17 87 #define CP0_CALG $17
88 #define CP0_IWATCH $18 88 #define CP0_IWATCH $18
89 #define CP0_DWATCH $19 89 #define CP0_DWATCH $19
90 90
91 /* 91 /*
92 * Coprocessor 0 Set 1 register names 92 * Coprocessor 0 Set 1 register names
93 */ 93 */
94 #define CP0_S1_DERRADDR0 $26 94 #define CP0_S1_DERRADDR0 $26
95 #define CP0_S1_DERRADDR1 $27 95 #define CP0_S1_DERRADDR1 $27
96 #define CP0_S1_INTCONTROL $20 96 #define CP0_S1_INTCONTROL $20
97 97
98 /* 98 /*
99 * Coprocessor 0 Set 2 register names 99 * Coprocessor 0 Set 2 register names
100 */ 100 */
101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */ 101 #define CP0_S2_SRSCTL $12 /* MIPSR2 */
102 102
103 /* 103 /*
104 * Coprocessor 0 Set 3 register names 104 * Coprocessor 0 Set 3 register names
105 */ 105 */
106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */ 106 #define CP0_S3_SRSMAP $12 /* MIPSR2 */
107 107
108 /* 108 /*
109 * TX39 Series 109 * TX39 Series
110 */ 110 */
111 #define CP0_TX39_CACHE $7 111 #define CP0_TX39_CACHE $7
112 112
113 /* 113 /*
114 * Coprocessor 1 (FPU) register names 114 * Coprocessor 1 (FPU) register names
115 */ 115 */
116 #define CP1_REVISION $0 116 #define CP1_REVISION $0
117 #define CP1_STATUS $31 117 #define CP1_STATUS $31
118 118
119 /* 119 /*
120 * FPU Status Register Values 120 * FPU Status Register Values
121 */ 121 */
122 /* 122 /*
123 * Status Register Values 123 * Status Register Values
124 */ 124 */
125 125
126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */ 126 #define FPU_CSR_FLUSH 0x01000000 /* flush denormalised results to 0 */
127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */ 127 #define FPU_CSR_COND 0x00800000 /* $fcc0 */
128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */ 128 #define FPU_CSR_COND0 0x00800000 /* $fcc0 */
129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */ 129 #define FPU_CSR_COND1 0x02000000 /* $fcc1 */
130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */ 130 #define FPU_CSR_COND2 0x04000000 /* $fcc2 */
131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */ 131 #define FPU_CSR_COND3 0x08000000 /* $fcc3 */
132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */ 132 #define FPU_CSR_COND4 0x10000000 /* $fcc4 */
133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */ 133 #define FPU_CSR_COND5 0x20000000 /* $fcc5 */
134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */ 134 #define FPU_CSR_COND6 0x40000000 /* $fcc6 */
135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */ 135 #define FPU_CSR_COND7 0x80000000 /* $fcc7 */
136 136
137 /* 137 /*
138 * Bits 18 - 20 of the FPU Status Register will be read as 0, 138 * Bits 18 - 20 of the FPU Status Register will be read as 0,
139 * and should be written as zero. 139 * and should be written as zero.
140 */ 140 */
141 #define FPU_CSR_RSVD 0x001c0000 141 #define FPU_CSR_RSVD 0x001c0000
142 142
143 /* 143 /*
144 * X the exception cause indicator 144 * X the exception cause indicator
145 * E the exception enable 145 * E the exception enable
146 * S the sticky/flag bit 146 * S the sticky/flag bit
147 */ 147 */
148 #define FPU_CSR_ALL_X 0x0003f000 148 #define FPU_CSR_ALL_X 0x0003f000
149 #define FPU_CSR_UNI_X 0x00020000 149 #define FPU_CSR_UNI_X 0x00020000
150 #define FPU_CSR_INV_X 0x00010000 150 #define FPU_CSR_INV_X 0x00010000
151 #define FPU_CSR_DIV_X 0x00008000 151 #define FPU_CSR_DIV_X 0x00008000
152 #define FPU_CSR_OVF_X 0x00004000 152 #define FPU_CSR_OVF_X 0x00004000
153 #define FPU_CSR_UDF_X 0x00002000 153 #define FPU_CSR_UDF_X 0x00002000
154 #define FPU_CSR_INE_X 0x00001000 154 #define FPU_CSR_INE_X 0x00001000
155 155
156 #define FPU_CSR_ALL_E 0x00000f80 156 #define FPU_CSR_ALL_E 0x00000f80
157 #define FPU_CSR_INV_E 0x00000800 157 #define FPU_CSR_INV_E 0x00000800
158 #define FPU_CSR_DIV_E 0x00000400 158 #define FPU_CSR_DIV_E 0x00000400
159 #define FPU_CSR_OVF_E 0x00000200 159 #define FPU_CSR_OVF_E 0x00000200
160 #define FPU_CSR_UDF_E 0x00000100 160 #define FPU_CSR_UDF_E 0x00000100
161 #define FPU_CSR_INE_E 0x00000080 161 #define FPU_CSR_INE_E 0x00000080
162 162
163 #define FPU_CSR_ALL_S 0x0000007c 163 #define FPU_CSR_ALL_S 0x0000007c
164 #define FPU_CSR_INV_S 0x00000040 164 #define FPU_CSR_INV_S 0x00000040
165 #define FPU_CSR_DIV_S 0x00000020 165 #define FPU_CSR_DIV_S 0x00000020
166 #define FPU_CSR_OVF_S 0x00000010 166 #define FPU_CSR_OVF_S 0x00000010
167 #define FPU_CSR_UDF_S 0x00000008 167 #define FPU_CSR_UDF_S 0x00000008
168 #define FPU_CSR_INE_S 0x00000004 168 #define FPU_CSR_INE_S 0x00000004
169 169
170 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */ 170 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
171 #define FPU_CSR_RM 0x00000003 171 #define FPU_CSR_RM 0x00000003
172 #define FPU_CSR_RN 0x0 /* nearest */ 172 #define FPU_CSR_RN 0x0 /* nearest */
173 #define FPU_CSR_RZ 0x1 /* towards zero */ 173 #define FPU_CSR_RZ 0x1 /* towards zero */
174 #define FPU_CSR_RU 0x2 /* towards +Infinity */ 174 #define FPU_CSR_RU 0x2 /* towards +Infinity */
175 #define FPU_CSR_RD 0x3 /* towards -Infinity */ 175 #define FPU_CSR_RD 0x3 /* towards -Infinity */
176 176
177 177
178 /* 178 /*
179 * Values for PageMask register 179 * Values for PageMask register
180 */ 180 */
181 #ifdef CONFIG_CPU_VR41XX 181 #ifdef CONFIG_CPU_VR41XX
182 182
183 /* Why doesn't stupidity hurt ... */ 183 /* Why doesn't stupidity hurt ... */
184 184
185 #define PM_1K 0x00000000 185 #define PM_1K 0x00000000
186 #define PM_4K 0x00001800 186 #define PM_4K 0x00001800
187 #define PM_16K 0x00007800 187 #define PM_16K 0x00007800
188 #define PM_64K 0x0001f800 188 #define PM_64K 0x0001f800
189 #define PM_256K 0x0007f800 189 #define PM_256K 0x0007f800
190 190
191 #else 191 #else
192 192
193 #define PM_4K 0x00000000 193 #define PM_4K 0x00000000
194 #define PM_8K 0x00002000 194 #define PM_8K 0x00002000
195 #define PM_16K 0x00006000 195 #define PM_16K 0x00006000
196 #define PM_32K 0x0000e000 196 #define PM_32K 0x0000e000
197 #define PM_64K 0x0001e000 197 #define PM_64K 0x0001e000
198 #define PM_128K 0x0003e000 198 #define PM_128K 0x0003e000
199 #define PM_256K 0x0007e000 199 #define PM_256K 0x0007e000
200 #define PM_512K 0x000fe000 200 #define PM_512K 0x000fe000
201 #define PM_1M 0x001fe000 201 #define PM_1M 0x001fe000
202 #define PM_2M 0x003fe000 202 #define PM_2M 0x003fe000
203 #define PM_4M 0x007fe000 203 #define PM_4M 0x007fe000
204 #define PM_8M 0x00ffe000 204 #define PM_8M 0x00ffe000
205 #define PM_16M 0x01ffe000 205 #define PM_16M 0x01ffe000
206 #define PM_32M 0x03ffe000 206 #define PM_32M 0x03ffe000
207 #define PM_64M 0x07ffe000 207 #define PM_64M 0x07ffe000
208 #define PM_256M 0x1fffe000 208 #define PM_256M 0x1fffe000
209 #define PM_1G 0x7fffe000 209 #define PM_1G 0x7fffe000
210 210
211 #endif 211 #endif
212 212
213 /* 213 /*
214 * Default page size for a given kernel configuration 214 * Default page size for a given kernel configuration
215 */ 215 */
216 #ifdef CONFIG_PAGE_SIZE_4KB 216 #ifdef CONFIG_PAGE_SIZE_4KB
217 #define PM_DEFAULT_MASK PM_4K 217 #define PM_DEFAULT_MASK PM_4K
218 #elif defined(CONFIG_PAGE_SIZE_8KB) 218 #elif defined(CONFIG_PAGE_SIZE_8KB)
219 #define PM_DEFAULT_MASK PM_8K 219 #define PM_DEFAULT_MASK PM_8K
220 #elif defined(CONFIG_PAGE_SIZE_16KB) 220 #elif defined(CONFIG_PAGE_SIZE_16KB)
221 #define PM_DEFAULT_MASK PM_16K 221 #define PM_DEFAULT_MASK PM_16K
222 #elif defined(CONFIG_PAGE_SIZE_32KB) 222 #elif defined(CONFIG_PAGE_SIZE_32KB)
223 #define PM_DEFAULT_MASK PM_32K 223 #define PM_DEFAULT_MASK PM_32K
224 #elif defined(CONFIG_PAGE_SIZE_64KB) 224 #elif defined(CONFIG_PAGE_SIZE_64KB)
225 #define PM_DEFAULT_MASK PM_64K 225 #define PM_DEFAULT_MASK PM_64K
226 #else 226 #else
227 #error Bad page size configuration! 227 #error Bad page size configuration!
228 #endif 228 #endif
229 229
230 /* 230 /*
231 * Default huge tlb size for a given kernel configuration 231 * Default huge tlb size for a given kernel configuration
232 */ 232 */
233 #ifdef CONFIG_PAGE_SIZE_4KB 233 #ifdef CONFIG_PAGE_SIZE_4KB
234 #define PM_HUGE_MASK PM_1M 234 #define PM_HUGE_MASK PM_1M
235 #elif defined(CONFIG_PAGE_SIZE_8KB) 235 #elif defined(CONFIG_PAGE_SIZE_8KB)
236 #define PM_HUGE_MASK PM_4M 236 #define PM_HUGE_MASK PM_4M
237 #elif defined(CONFIG_PAGE_SIZE_16KB) 237 #elif defined(CONFIG_PAGE_SIZE_16KB)
238 #define PM_HUGE_MASK PM_16M 238 #define PM_HUGE_MASK PM_16M
239 #elif defined(CONFIG_PAGE_SIZE_32KB) 239 #elif defined(CONFIG_PAGE_SIZE_32KB)
240 #define PM_HUGE_MASK PM_64M 240 #define PM_HUGE_MASK PM_64M
241 #elif defined(CONFIG_PAGE_SIZE_64KB) 241 #elif defined(CONFIG_PAGE_SIZE_64KB)
242 #define PM_HUGE_MASK PM_256M 242 #define PM_HUGE_MASK PM_256M
243 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) 243 #elif defined(CONFIG_MIPS_HUGE_TLB_SUPPORT)
244 #error Bad page size configuration for hugetlbfs! 244 #error Bad page size configuration for hugetlbfs!
245 #endif 245 #endif
246 246
247 /* 247 /*
248 * Values used for computation of new tlb entries 248 * Values used for computation of new tlb entries
249 */ 249 */
250 #define PL_4K 12 250 #define PL_4K 12
251 #define PL_16K 14 251 #define PL_16K 14
252 #define PL_64K 16 252 #define PL_64K 16
253 #define PL_256K 18 253 #define PL_256K 18
254 #define PL_1M 20 254 #define PL_1M 20
255 #define PL_4M 22 255 #define PL_4M 22
256 #define PL_16M 24 256 #define PL_16M 24
257 #define PL_64M 26 257 #define PL_64M 26
258 #define PL_256M 28 258 #define PL_256M 28
259 259
260 /* 260 /*
261 * PageGrain bits 261 * PageGrain bits
262 */ 262 */
263 #define PG_RIE (_ULCAST_(1) << 31) 263 #define PG_RIE (_ULCAST_(1) << 31)
264 #define PG_XIE (_ULCAST_(1) << 30) 264 #define PG_XIE (_ULCAST_(1) << 30)
265 #define PG_ELPA (_ULCAST_(1) << 29) 265 #define PG_ELPA (_ULCAST_(1) << 29)
266 #define PG_ESP (_ULCAST_(1) << 28) 266 #define PG_ESP (_ULCAST_(1) << 28)
267 267
268 /* 268 /*
269 * R4x00 interrupt enable / cause bits 269 * R4x00 interrupt enable / cause bits
270 */ 270 */
271 #define IE_SW0 (_ULCAST_(1) << 8) 271 #define IE_SW0 (_ULCAST_(1) << 8)
272 #define IE_SW1 (_ULCAST_(1) << 9) 272 #define IE_SW1 (_ULCAST_(1) << 9)
273 #define IE_IRQ0 (_ULCAST_(1) << 10) 273 #define IE_IRQ0 (_ULCAST_(1) << 10)
274 #define IE_IRQ1 (_ULCAST_(1) << 11) 274 #define IE_IRQ1 (_ULCAST_(1) << 11)
275 #define IE_IRQ2 (_ULCAST_(1) << 12) 275 #define IE_IRQ2 (_ULCAST_(1) << 12)
276 #define IE_IRQ3 (_ULCAST_(1) << 13) 276 #define IE_IRQ3 (_ULCAST_(1) << 13)
277 #define IE_IRQ4 (_ULCAST_(1) << 14) 277 #define IE_IRQ4 (_ULCAST_(1) << 14)
278 #define IE_IRQ5 (_ULCAST_(1) << 15) 278 #define IE_IRQ5 (_ULCAST_(1) << 15)
279 279
280 /* 280 /*
281 * R4x00 interrupt cause bits 281 * R4x00 interrupt cause bits
282 */ 282 */
283 #define C_SW0 (_ULCAST_(1) << 8) 283 #define C_SW0 (_ULCAST_(1) << 8)
284 #define C_SW1 (_ULCAST_(1) << 9) 284 #define C_SW1 (_ULCAST_(1) << 9)
285 #define C_IRQ0 (_ULCAST_(1) << 10) 285 #define C_IRQ0 (_ULCAST_(1) << 10)
286 #define C_IRQ1 (_ULCAST_(1) << 11) 286 #define C_IRQ1 (_ULCAST_(1) << 11)
287 #define C_IRQ2 (_ULCAST_(1) << 12) 287 #define C_IRQ2 (_ULCAST_(1) << 12)
288 #define C_IRQ3 (_ULCAST_(1) << 13) 288 #define C_IRQ3 (_ULCAST_(1) << 13)
289 #define C_IRQ4 (_ULCAST_(1) << 14) 289 #define C_IRQ4 (_ULCAST_(1) << 14)
290 #define C_IRQ5 (_ULCAST_(1) << 15) 290 #define C_IRQ5 (_ULCAST_(1) << 15)
291 291
292 /* 292 /*
293 * Bitfields in the R4xx0 cp0 status register 293 * Bitfields in the R4xx0 cp0 status register
294 */ 294 */
295 #define ST0_IE 0x00000001 295 #define ST0_IE 0x00000001
296 #define ST0_EXL 0x00000002 296 #define ST0_EXL 0x00000002
297 #define ST0_ERL 0x00000004 297 #define ST0_ERL 0x00000004
298 #define ST0_KSU 0x00000018 298 #define ST0_KSU 0x00000018
299 # define KSU_USER 0x00000010 299 # define KSU_USER 0x00000010
300 # define KSU_SUPERVISOR 0x00000008 300 # define KSU_SUPERVISOR 0x00000008
301 # define KSU_KERNEL 0x00000000 301 # define KSU_KERNEL 0x00000000
302 #define ST0_UX 0x00000020 302 #define ST0_UX 0x00000020
303 #define ST0_SX 0x00000040 303 #define ST0_SX 0x00000040
304 #define ST0_KX 0x00000080 304 #define ST0_KX 0x00000080
305 #define ST0_DE 0x00010000 305 #define ST0_DE 0x00010000
306 #define ST0_CE 0x00020000 306 #define ST0_CE 0x00020000
307 307
308 /* 308 /*
309 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate 309 * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
310 * cacheops in userspace. This bit exists only on RM7000 and RM9000 310 * cacheops in userspace. This bit exists only on RM7000 and RM9000
311 * processors. 311 * processors.
312 */ 312 */
313 #define ST0_CO 0x08000000 313 #define ST0_CO 0x08000000
314 314
315 /* 315 /*
316 * Bitfields in the R[23]000 cp0 status register. 316 * Bitfields in the R[23]000 cp0 status register.
317 */ 317 */
318 #define ST0_IEC 0x00000001 318 #define ST0_IEC 0x00000001
319 #define ST0_KUC 0x00000002 319 #define ST0_KUC 0x00000002
320 #define ST0_IEP 0x00000004 320 #define ST0_IEP 0x00000004
321 #define ST0_KUP 0x00000008 321 #define ST0_KUP 0x00000008
322 #define ST0_IEO 0x00000010 322 #define ST0_IEO 0x00000010
323 #define ST0_KUO 0x00000020 323 #define ST0_KUO 0x00000020
324 /* bits 6 & 7 are reserved on R[23]000 */ 324 /* bits 6 & 7 are reserved on R[23]000 */
325 #define ST0_ISC 0x00010000 325 #define ST0_ISC 0x00010000
326 #define ST0_SWC 0x00020000 326 #define ST0_SWC 0x00020000
327 #define ST0_CM 0x00080000 327 #define ST0_CM 0x00080000
328 328
329 /* 329 /*
330 * Bits specific to the R4640/R4650 330 * Bits specific to the R4640/R4650
331 */ 331 */
332 #define ST0_UM (_ULCAST_(1) << 4) 332 #define ST0_UM (_ULCAST_(1) << 4)
333 #define ST0_IL (_ULCAST_(1) << 23) 333 #define ST0_IL (_ULCAST_(1) << 23)
334 #define ST0_DL (_ULCAST_(1) << 24) 334 #define ST0_DL (_ULCAST_(1) << 24)
335 335
336 /* 336 /*
337 * Enable the MIPS MDMX and DSP ASEs 337 * Enable the MIPS MDMX and DSP ASEs
338 */ 338 */
339 #define ST0_MX 0x01000000 339 #define ST0_MX 0x01000000
340 340
341 /* 341 /*
342 * Bitfields in the TX39 family CP0 Configuration Register 3 342 * Bitfields in the TX39 family CP0 Configuration Register 3
343 */ 343 */
344 #define TX39_CONF_ICS_SHIFT 19 344 #define TX39_CONF_ICS_SHIFT 19
345 #define TX39_CONF_ICS_MASK 0x00380000 345 #define TX39_CONF_ICS_MASK 0x00380000
346 #define TX39_CONF_ICS_1KB 0x00000000 346 #define TX39_CONF_ICS_1KB 0x00000000
347 #define TX39_CONF_ICS_2KB 0x00080000 347 #define TX39_CONF_ICS_2KB 0x00080000
348 #define TX39_CONF_ICS_4KB 0x00100000 348 #define TX39_CONF_ICS_4KB 0x00100000
349 #define TX39_CONF_ICS_8KB 0x00180000 349 #define TX39_CONF_ICS_8KB 0x00180000
350 #define TX39_CONF_ICS_16KB 0x00200000 350 #define TX39_CONF_ICS_16KB 0x00200000
351 351
352 #define TX39_CONF_DCS_SHIFT 16 352 #define TX39_CONF_DCS_SHIFT 16
353 #define TX39_CONF_DCS_MASK 0x00070000 353 #define TX39_CONF_DCS_MASK 0x00070000
354 #define TX39_CONF_DCS_1KB 0x00000000 354 #define TX39_CONF_DCS_1KB 0x00000000
355 #define TX39_CONF_DCS_2KB 0x00010000 355 #define TX39_CONF_DCS_2KB 0x00010000
356 #define TX39_CONF_DCS_4KB 0x00020000 356 #define TX39_CONF_DCS_4KB 0x00020000
357 #define TX39_CONF_DCS_8KB 0x00030000 357 #define TX39_CONF_DCS_8KB 0x00030000
358 #define TX39_CONF_DCS_16KB 0x00040000 358 #define TX39_CONF_DCS_16KB 0x00040000
359 359
360 #define TX39_CONF_CWFON 0x00004000 360 #define TX39_CONF_CWFON 0x00004000
361 #define TX39_CONF_WBON 0x00002000 361 #define TX39_CONF_WBON 0x00002000
362 #define TX39_CONF_RF_SHIFT 10 362 #define TX39_CONF_RF_SHIFT 10
363 #define TX39_CONF_RF_MASK 0x00000c00 363 #define TX39_CONF_RF_MASK 0x00000c00
364 #define TX39_CONF_DOZE 0x00000200 364 #define TX39_CONF_DOZE 0x00000200
365 #define TX39_CONF_HALT 0x00000100 365 #define TX39_CONF_HALT 0x00000100
366 #define TX39_CONF_LOCK 0x00000080 366 #define TX39_CONF_LOCK 0x00000080
367 #define TX39_CONF_ICE 0x00000020 367 #define TX39_CONF_ICE 0x00000020
368 #define TX39_CONF_DCE 0x00000010 368 #define TX39_CONF_DCE 0x00000010
369 #define TX39_CONF_IRSIZE_SHIFT 2 369 #define TX39_CONF_IRSIZE_SHIFT 2
370 #define TX39_CONF_IRSIZE_MASK 0x0000000c 370 #define TX39_CONF_IRSIZE_MASK 0x0000000c
371 #define TX39_CONF_DRSIZE_SHIFT 0 371 #define TX39_CONF_DRSIZE_SHIFT 0
372 #define TX39_CONF_DRSIZE_MASK 0x00000003 372 #define TX39_CONF_DRSIZE_MASK 0x00000003
373 373
374 /* 374 /*
375 * Status register bits available in all MIPS CPUs. 375 * Status register bits available in all MIPS CPUs.
376 */ 376 */
377 #define ST0_IM 0x0000ff00 377 #define ST0_IM 0x0000ff00
378 #define STATUSB_IP0 8 378 #define STATUSB_IP0 8
379 #define STATUSF_IP0 (_ULCAST_(1) << 8) 379 #define STATUSF_IP0 (_ULCAST_(1) << 8)
380 #define STATUSB_IP1 9 380 #define STATUSB_IP1 9
381 #define STATUSF_IP1 (_ULCAST_(1) << 9) 381 #define STATUSF_IP1 (_ULCAST_(1) << 9)
382 #define STATUSB_IP2 10 382 #define STATUSB_IP2 10
383 #define STATUSF_IP2 (_ULCAST_(1) << 10) 383 #define STATUSF_IP2 (_ULCAST_(1) << 10)
384 #define STATUSB_IP3 11 384 #define STATUSB_IP3 11
385 #define STATUSF_IP3 (_ULCAST_(1) << 11) 385 #define STATUSF_IP3 (_ULCAST_(1) << 11)
386 #define STATUSB_IP4 12 386 #define STATUSB_IP4 12
387 #define STATUSF_IP4 (_ULCAST_(1) << 12) 387 #define STATUSF_IP4 (_ULCAST_(1) << 12)
388 #define STATUSB_IP5 13 388 #define STATUSB_IP5 13
389 #define STATUSF_IP5 (_ULCAST_(1) << 13) 389 #define STATUSF_IP5 (_ULCAST_(1) << 13)
390 #define STATUSB_IP6 14 390 #define STATUSB_IP6 14
391 #define STATUSF_IP6 (_ULCAST_(1) << 14) 391 #define STATUSF_IP6 (_ULCAST_(1) << 14)
392 #define STATUSB_IP7 15 392 #define STATUSB_IP7 15
393 #define STATUSF_IP7 (_ULCAST_(1) << 15) 393 #define STATUSF_IP7 (_ULCAST_(1) << 15)
394 #define STATUSB_IP8 0 394 #define STATUSB_IP8 0
395 #define STATUSF_IP8 (_ULCAST_(1) << 0) 395 #define STATUSF_IP8 (_ULCAST_(1) << 0)
396 #define STATUSB_IP9 1 396 #define STATUSB_IP9 1
397 #define STATUSF_IP9 (_ULCAST_(1) << 1) 397 #define STATUSF_IP9 (_ULCAST_(1) << 1)
398 #define STATUSB_IP10 2 398 #define STATUSB_IP10 2
399 #define STATUSF_IP10 (_ULCAST_(1) << 2) 399 #define STATUSF_IP10 (_ULCAST_(1) << 2)
400 #define STATUSB_IP11 3 400 #define STATUSB_IP11 3
401 #define STATUSF_IP11 (_ULCAST_(1) << 3) 401 #define STATUSF_IP11 (_ULCAST_(1) << 3)
402 #define STATUSB_IP12 4 402 #define STATUSB_IP12 4
403 #define STATUSF_IP12 (_ULCAST_(1) << 4) 403 #define STATUSF_IP12 (_ULCAST_(1) << 4)
404 #define STATUSB_IP13 5 404 #define STATUSB_IP13 5
405 #define STATUSF_IP13 (_ULCAST_(1) << 5) 405 #define STATUSF_IP13 (_ULCAST_(1) << 5)
406 #define STATUSB_IP14 6 406 #define STATUSB_IP14 6
407 #define STATUSF_IP14 (_ULCAST_(1) << 6) 407 #define STATUSF_IP14 (_ULCAST_(1) << 6)
408 #define STATUSB_IP15 7 408 #define STATUSB_IP15 7
409 #define STATUSF_IP15 (_ULCAST_(1) << 7) 409 #define STATUSF_IP15 (_ULCAST_(1) << 7)
410 #define ST0_CH 0x00040000 410 #define ST0_CH 0x00040000
411 #define ST0_NMI 0x00080000 411 #define ST0_NMI 0x00080000
412 #define ST0_SR 0x00100000 412 #define ST0_SR 0x00100000
413 #define ST0_TS 0x00200000 413 #define ST0_TS 0x00200000
414 #define ST0_BEV 0x00400000 414 #define ST0_BEV 0x00400000
415 #define ST0_RE 0x02000000 415 #define ST0_RE 0x02000000
416 #define ST0_FR 0x04000000 416 #define ST0_FR 0x04000000
417 #define ST0_CU 0xf0000000 417 #define ST0_CU 0xf0000000
418 #define ST0_CU0 0x10000000 418 #define ST0_CU0 0x10000000
419 #define ST0_CU1 0x20000000 419 #define ST0_CU1 0x20000000
420 #define ST0_CU2 0x40000000 420 #define ST0_CU2 0x40000000
421 #define ST0_CU3 0x80000000 421 #define ST0_CU3 0x80000000
422 #define ST0_XX 0x80000000 /* MIPS IV naming */ 422 #define ST0_XX 0x80000000 /* MIPS IV naming */
423 423
424 /* 424 /*
425 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2) 425 * Bitfields and bit numbers in the coprocessor 0 IntCtl register. (MIPSR2)
426 * 426 *
427 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 427 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
428 */ 428 */
429 #define INTCTLB_IPPCI 26 429 #define INTCTLB_IPPCI 26
430 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI) 430 #define INTCTLF_IPPCI (_ULCAST_(7) << INTCTLB_IPPCI)
431 #define INTCTLB_IPTI 29 431 #define INTCTLB_IPTI 29
432 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI) 432 #define INTCTLF_IPTI (_ULCAST_(7) << INTCTLB_IPTI)
433 433
434 /* 434 /*
435 * Bitfields and bit numbers in the coprocessor 0 cause register. 435 * Bitfields and bit numbers in the coprocessor 0 cause register.
436 * 436 *
437 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation. 437 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
438 */ 438 */
439 #define CAUSEB_EXCCODE 2 439 #define CAUSEB_EXCCODE 2
440 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2) 440 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
441 #define CAUSEB_IP 8 441 #define CAUSEB_IP 8
442 #define CAUSEF_IP (_ULCAST_(255) << 8) 442 #define CAUSEF_IP (_ULCAST_(255) << 8)
443 #define CAUSEB_IP0 8 443 #define CAUSEB_IP0 8
444 #define CAUSEF_IP0 (_ULCAST_(1) << 8) 444 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
445 #define CAUSEB_IP1 9 445 #define CAUSEB_IP1 9
446 #define CAUSEF_IP1 (_ULCAST_(1) << 9) 446 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
447 #define CAUSEB_IP2 10 447 #define CAUSEB_IP2 10
448 #define CAUSEF_IP2 (_ULCAST_(1) << 10) 448 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
449 #define CAUSEB_IP3 11 449 #define CAUSEB_IP3 11
450 #define CAUSEF_IP3 (_ULCAST_(1) << 11) 450 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
451 #define CAUSEB_IP4 12 451 #define CAUSEB_IP4 12
452 #define CAUSEF_IP4 (_ULCAST_(1) << 12) 452 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
453 #define CAUSEB_IP5 13 453 #define CAUSEB_IP5 13
454 #define CAUSEF_IP5 (_ULCAST_(1) << 13) 454 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
455 #define CAUSEB_IP6 14 455 #define CAUSEB_IP6 14
456 #define CAUSEF_IP6 (_ULCAST_(1) << 14) 456 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
457 #define CAUSEB_IP7 15 457 #define CAUSEB_IP7 15
458 #define CAUSEF_IP7 (_ULCAST_(1) << 15) 458 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
459 #define CAUSEB_IV 23 459 #define CAUSEB_IV 23
460 #define CAUSEF_IV (_ULCAST_(1) << 23) 460 #define CAUSEF_IV (_ULCAST_(1) << 23)
461 #define CAUSEB_PCI 26 461 #define CAUSEB_PCI 26
462 #define CAUSEF_PCI (_ULCAST_(1) << 26) 462 #define CAUSEF_PCI (_ULCAST_(1) << 26)
463 #define CAUSEB_CE 28 463 #define CAUSEB_CE 28
464 #define CAUSEF_CE (_ULCAST_(3) << 28) 464 #define CAUSEF_CE (_ULCAST_(3) << 28)
465 #define CAUSEB_TI 30 465 #define CAUSEB_TI 30
466 #define CAUSEF_TI (_ULCAST_(1) << 30) 466 #define CAUSEF_TI (_ULCAST_(1) << 30)
467 #define CAUSEB_BD 31 467 #define CAUSEB_BD 31
468 #define CAUSEF_BD (_ULCAST_(1) << 31) 468 #define CAUSEF_BD (_ULCAST_(1) << 31)
469 469
470 /* 470 /*
471 * Bits in the coprocessor 0 config register. 471 * Bits in the coprocessor 0 config register.
472 */ 472 */
473 /* Generic bits. */ 473 /* Generic bits. */
474 #define CONF_CM_CACHABLE_NO_WA 0 474 #define CONF_CM_CACHABLE_NO_WA 0
475 #define CONF_CM_CACHABLE_WA 1 475 #define CONF_CM_CACHABLE_WA 1
476 #define CONF_CM_UNCACHED 2 476 #define CONF_CM_UNCACHED 2
477 #define CONF_CM_CACHABLE_NONCOHERENT 3 477 #define CONF_CM_CACHABLE_NONCOHERENT 3
478 #define CONF_CM_CACHABLE_CE 4 478 #define CONF_CM_CACHABLE_CE 4
479 #define CONF_CM_CACHABLE_COW 5 479 #define CONF_CM_CACHABLE_COW 5
480 #define CONF_CM_CACHABLE_CUW 6 480 #define CONF_CM_CACHABLE_CUW 6
481 #define CONF_CM_CACHABLE_ACCELERATED 7 481 #define CONF_CM_CACHABLE_ACCELERATED 7
482 #define CONF_CM_CMASK 7 482 #define CONF_CM_CMASK 7
483 #define CONF_BE (_ULCAST_(1) << 15) 483 #define CONF_BE (_ULCAST_(1) << 15)
484 484
485 /* Bits common to various processors. */ 485 /* Bits common to various processors. */
486 #define CONF_CU (_ULCAST_(1) << 3) 486 #define CONF_CU (_ULCAST_(1) << 3)
487 #define CONF_DB (_ULCAST_(1) << 4) 487 #define CONF_DB (_ULCAST_(1) << 4)
488 #define CONF_IB (_ULCAST_(1) << 5) 488 #define CONF_IB (_ULCAST_(1) << 5)
489 #define CONF_DC (_ULCAST_(7) << 6) 489 #define CONF_DC (_ULCAST_(7) << 6)
490 #define CONF_IC (_ULCAST_(7) << 9) 490 #define CONF_IC (_ULCAST_(7) << 9)
491 #define CONF_EB (_ULCAST_(1) << 13) 491 #define CONF_EB (_ULCAST_(1) << 13)
492 #define CONF_EM (_ULCAST_(1) << 14) 492 #define CONF_EM (_ULCAST_(1) << 14)
493 #define CONF_SM (_ULCAST_(1) << 16) 493 #define CONF_SM (_ULCAST_(1) << 16)
494 #define CONF_SC (_ULCAST_(1) << 17) 494 #define CONF_SC (_ULCAST_(1) << 17)
495 #define CONF_EW (_ULCAST_(3) << 18) 495 #define CONF_EW (_ULCAST_(3) << 18)
496 #define CONF_EP (_ULCAST_(15)<< 24) 496 #define CONF_EP (_ULCAST_(15)<< 24)
497 #define CONF_EC (_ULCAST_(7) << 28) 497 #define CONF_EC (_ULCAST_(7) << 28)
498 #define CONF_CM (_ULCAST_(1) << 31) 498 #define CONF_CM (_ULCAST_(1) << 31)
499 499
500 /* Bits specific to the R4xx0. */ 500 /* Bits specific to the R4xx0. */
501 #define R4K_CONF_SW (_ULCAST_(1) << 20) 501 #define R4K_CONF_SW (_ULCAST_(1) << 20)
502 #define R4K_CONF_SS (_ULCAST_(1) << 21) 502 #define R4K_CONF_SS (_ULCAST_(1) << 21)
503 #define R4K_CONF_SB (_ULCAST_(3) << 22) 503 #define R4K_CONF_SB (_ULCAST_(3) << 22)
504 504
505 /* Bits specific to the R5000. */ 505 /* Bits specific to the R5000. */
506 #define R5K_CONF_SE (_ULCAST_(1) << 12) 506 #define R5K_CONF_SE (_ULCAST_(1) << 12)
507 #define R5K_CONF_SS (_ULCAST_(3) << 20) 507 #define R5K_CONF_SS (_ULCAST_(3) << 20)
508 508
509 /* Bits specific to the RM7000. */ 509 /* Bits specific to the RM7000. */
510 #define RM7K_CONF_SE (_ULCAST_(1) << 3) 510 #define RM7K_CONF_SE (_ULCAST_(1) << 3)
511 #define RM7K_CONF_TE (_ULCAST_(1) << 12) 511 #define RM7K_CONF_TE (_ULCAST_(1) << 12)
512 #define RM7K_CONF_CLK (_ULCAST_(1) << 16) 512 #define RM7K_CONF_CLK (_ULCAST_(1) << 16)
513 #define RM7K_CONF_TC (_ULCAST_(1) << 17) 513 #define RM7K_CONF_TC (_ULCAST_(1) << 17)
514 #define RM7K_CONF_SI (_ULCAST_(3) << 20) 514 #define RM7K_CONF_SI (_ULCAST_(3) << 20)
515 #define RM7K_CONF_SC (_ULCAST_(1) << 31) 515 #define RM7K_CONF_SC (_ULCAST_(1) << 31)
516 516
517 /* Bits specific to the R10000. */ 517 /* Bits specific to the R10000. */
518 #define R10K_CONF_DN (_ULCAST_(3) << 3) 518 #define R10K_CONF_DN (_ULCAST_(3) << 3)
519 #define R10K_CONF_CT (_ULCAST_(1) << 5) 519 #define R10K_CONF_CT (_ULCAST_(1) << 5)
520 #define R10K_CONF_PE (_ULCAST_(1) << 6) 520 #define R10K_CONF_PE (_ULCAST_(1) << 6)
521 #define R10K_CONF_PM (_ULCAST_(3) << 7) 521 #define R10K_CONF_PM (_ULCAST_(3) << 7)
522 #define R10K_CONF_EC (_ULCAST_(15)<< 9) 522 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
523 #define R10K_CONF_SB (_ULCAST_(1) << 13) 523 #define R10K_CONF_SB (_ULCAST_(1) << 13)
524 #define R10K_CONF_SK (_ULCAST_(1) << 14) 524 #define R10K_CONF_SK (_ULCAST_(1) << 14)
525 #define R10K_CONF_SS (_ULCAST_(7) << 16) 525 #define R10K_CONF_SS (_ULCAST_(7) << 16)
526 #define R10K_CONF_SC (_ULCAST_(7) << 19) 526 #define R10K_CONF_SC (_ULCAST_(7) << 19)
527 #define R10K_CONF_DC (_ULCAST_(7) << 26) 527 #define R10K_CONF_DC (_ULCAST_(7) << 26)
528 #define R10K_CONF_IC (_ULCAST_(7) << 29) 528 #define R10K_CONF_IC (_ULCAST_(7) << 29)
529 529
530 /* Bits specific to the VR41xx. */ 530 /* Bits specific to the VR41xx. */
531 #define VR41_CONF_CS (_ULCAST_(1) << 12) 531 #define VR41_CONF_CS (_ULCAST_(1) << 12)
532 #define VR41_CONF_P4K (_ULCAST_(1) << 13) 532 #define VR41_CONF_P4K (_ULCAST_(1) << 13)
533 #define VR41_CONF_BP (_ULCAST_(1) << 16) 533 #define VR41_CONF_BP (_ULCAST_(1) << 16)
534 #define VR41_CONF_M16 (_ULCAST_(1) << 20) 534 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
535 #define VR41_CONF_AD (_ULCAST_(1) << 23) 535 #define VR41_CONF_AD (_ULCAST_(1) << 23)
536 536
537 /* Bits specific to the R30xx. */ 537 /* Bits specific to the R30xx. */
538 #define R30XX_CONF_FDM (_ULCAST_(1) << 19) 538 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
539 #define R30XX_CONF_REV (_ULCAST_(1) << 22) 539 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
540 #define R30XX_CONF_AC (_ULCAST_(1) << 23) 540 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
541 #define R30XX_CONF_RF (_ULCAST_(1) << 24) 541 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
542 #define R30XX_CONF_HALT (_ULCAST_(1) << 25) 542 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
543 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26) 543 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
544 #define R30XX_CONF_DBR (_ULCAST_(1) << 29) 544 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
545 #define R30XX_CONF_SB (_ULCAST_(1) << 30) 545 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
546 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31) 546 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
547 547
548 /* Bits specific to the TX49. */ 548 /* Bits specific to the TX49. */
549 #define TX49_CONF_DC (_ULCAST_(1) << 16) 549 #define TX49_CONF_DC (_ULCAST_(1) << 16)
550 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */ 550 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
551 #define TX49_CONF_HALT (_ULCAST_(1) << 18) 551 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
552 #define TX49_CONF_CWFON (_ULCAST_(1) << 27) 552 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
553 553
554 /* Bits specific to the MIPS32/64 PRA. */ 554 /* Bits specific to the MIPS32/64 PRA. */
555 #define MIPS_CONF_MT (_ULCAST_(7) << 7) 555 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
556 #define MIPS_CONF_AR (_ULCAST_(7) << 10) 556 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
557 #define MIPS_CONF_AT (_ULCAST_(3) << 13) 557 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
558 #define MIPS_CONF_M (_ULCAST_(1) << 31) 558 #define MIPS_CONF_M (_ULCAST_(1) << 31)
559 559
560 /* 560 /*
561 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above. 561 * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
562 */ 562 */
563 #define MIPS_CONF1_FP (_ULCAST_(1) << 0) 563 #define MIPS_CONF1_FP (_ULCAST_(1) << 0)
564 #define MIPS_CONF1_EP (_ULCAST_(1) << 1) 564 #define MIPS_CONF1_EP (_ULCAST_(1) << 1)
565 #define MIPS_CONF1_CA (_ULCAST_(1) << 2) 565 #define MIPS_CONF1_CA (_ULCAST_(1) << 2)
566 #define MIPS_CONF1_WR (_ULCAST_(1) << 3) 566 #define MIPS_CONF1_WR (_ULCAST_(1) << 3)
567 #define MIPS_CONF1_PC (_ULCAST_(1) << 4) 567 #define MIPS_CONF1_PC (_ULCAST_(1) << 4)
568 #define MIPS_CONF1_MD (_ULCAST_(1) << 5) 568 #define MIPS_CONF1_MD (_ULCAST_(1) << 5)
569 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6) 569 #define MIPS_CONF1_C2 (_ULCAST_(1) << 6)
570 #define MIPS_CONF1_DA (_ULCAST_(7) << 7) 570 #define MIPS_CONF1_DA (_ULCAST_(7) << 7)
571 #define MIPS_CONF1_DL (_ULCAST_(7) << 10) 571 #define MIPS_CONF1_DL (_ULCAST_(7) << 10)
572 #define MIPS_CONF1_DS (_ULCAST_(7) << 13) 572 #define MIPS_CONF1_DS (_ULCAST_(7) << 13)
573 #define MIPS_CONF1_IA (_ULCAST_(7) << 16) 573 #define MIPS_CONF1_IA (_ULCAST_(7) << 16)
574 #define MIPS_CONF1_IL (_ULCAST_(7) << 19) 574 #define MIPS_CONF1_IL (_ULCAST_(7) << 19)
575 #define MIPS_CONF1_IS (_ULCAST_(7) << 22) 575 #define MIPS_CONF1_IS (_ULCAST_(7) << 22)
576 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25) 576 #define MIPS_CONF1_TLBS (_ULCAST_(63)<< 25)
577 577
578 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0) 578 #define MIPS_CONF2_SA (_ULCAST_(15)<< 0)
579 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4) 579 #define MIPS_CONF2_SL (_ULCAST_(15)<< 4)
580 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8) 580 #define MIPS_CONF2_SS (_ULCAST_(15)<< 8)
581 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12) 581 #define MIPS_CONF2_SU (_ULCAST_(15)<< 12)
582 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16) 582 #define MIPS_CONF2_TA (_ULCAST_(15)<< 16)
583 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20) 583 #define MIPS_CONF2_TL (_ULCAST_(15)<< 20)
584 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24) 584 #define MIPS_CONF2_TS (_ULCAST_(15)<< 24)
585 #define MIPS_CONF2_TU (_ULCAST_(7) << 28) 585 #define MIPS_CONF2_TU (_ULCAST_(7) << 28)
586 586
587 #define MIPS_CONF3_TL (_ULCAST_(1) << 0) 587 #define MIPS_CONF3_TL (_ULCAST_(1) << 0)
588 #define MIPS_CONF3_SM (_ULCAST_(1) << 1) 588 #define MIPS_CONF3_SM (_ULCAST_(1) << 1)
589 #define MIPS_CONF3_MT (_ULCAST_(1) << 2) 589 #define MIPS_CONF3_MT (_ULCAST_(1) << 2)
590 #define MIPS_CONF3_SP (_ULCAST_(1) << 4) 590 #define MIPS_CONF3_SP (_ULCAST_(1) << 4)
591 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5) 591 #define MIPS_CONF3_VINT (_ULCAST_(1) << 5)
592 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6) 592 #define MIPS_CONF3_VEIC (_ULCAST_(1) << 6)
593 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7) 593 #define MIPS_CONF3_LPA (_ULCAST_(1) << 7)
594 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10) 594 #define MIPS_CONF3_DSP (_ULCAST_(1) << 10)
595 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11) 595 #define MIPS_CONF3_DSP2P (_ULCAST_(1) << 11)
596 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12) 596 #define MIPS_CONF3_RXI (_ULCAST_(1) << 12)
597 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13) 597 #define MIPS_CONF3_ULRI (_ULCAST_(1) << 13)
598 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14) 598 #define MIPS_CONF3_ISA (_ULCAST_(3) << 14)
599 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23) 599 #define MIPS_CONF3_VZ (_ULCAST_(1) << 23)
600 600
601 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0) 601 #define MIPS_CONF4_MMUSIZEEXT (_ULCAST_(255) << 0)
602 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14) 602 #define MIPS_CONF4_MMUEXTDEF (_ULCAST_(3) << 14)
603 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14) 603 #define MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT (_ULCAST_(1) << 14)
604 604
605 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13) 605 #define MIPS_CONF6_SYND (_ULCAST_(1) << 13)
606 606
607 #define MIPS_CONF7_WII (_ULCAST_(1) << 31) 607 #define MIPS_CONF7_WII (_ULCAST_(1) << 31)
608 608
609 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) 609 #define MIPS_CONF7_RPS (_ULCAST_(1) << 2)
610 610
611 611
612 /* 612 /*
613 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register. 613 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
614 */ 614 */
615 #define MIPS_FPIR_S (_ULCAST_(1) << 16) 615 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
616 #define MIPS_FPIR_D (_ULCAST_(1) << 17) 616 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
617 #define MIPS_FPIR_PS (_ULCAST_(1) << 18) 617 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
618 #define MIPS_FPIR_3D (_ULCAST_(1) << 19) 618 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
619 #define MIPS_FPIR_W (_ULCAST_(1) << 20) 619 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
620 #define MIPS_FPIR_L (_ULCAST_(1) << 21) 620 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
621 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22) 621 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
622 622
623 #ifndef __ASSEMBLY__ 623 #ifndef __ASSEMBLY__
624 624
625 /* 625 /*
626 * Functions to access the R10000 performance counters. These are basically 626 * Functions to access the R10000 performance counters. These are basically
627 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit 627 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
628 * performance counter number encoded into bits 1 ... 5 of the instruction. 628 * performance counter number encoded into bits 1 ... 5 of the instruction.
629 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware 629 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
630 * disassembler these will look like an access to sel 0 or 1. 630 * disassembler these will look like an access to sel 0 or 1.
631 */ 631 */
632 #define read_r10k_perf_cntr(counter) \ 632 #define read_r10k_perf_cntr(counter) \
633 ({ \ 633 ({ \
634 unsigned int __res; \ 634 unsigned int __res; \
635 __asm__ __volatile__( \ 635 __asm__ __volatile__( \
636 "mfpc\t%0, %1" \ 636 "mfpc\t%0, %1" \
637 : "=r" (__res) \ 637 : "=r" (__res) \
638 : "i" (counter)); \ 638 : "i" (counter)); \
639 \ 639 \
640 __res; \ 640 __res; \
641 }) 641 })
642 642
643 #define write_r10k_perf_cntr(counter,val) \ 643 #define write_r10k_perf_cntr(counter,val) \
644 do { \ 644 do { \
645 __asm__ __volatile__( \ 645 __asm__ __volatile__( \
646 "mtpc\t%0, %1" \ 646 "mtpc\t%0, %1" \
647 : \ 647 : \
648 : "r" (val), "i" (counter)); \ 648 : "r" (val), "i" (counter)); \
649 } while (0) 649 } while (0)
650 650
651 #define read_r10k_perf_event(counter) \ 651 #define read_r10k_perf_event(counter) \
652 ({ \ 652 ({ \
653 unsigned int __res; \ 653 unsigned int __res; \
654 __asm__ __volatile__( \ 654 __asm__ __volatile__( \
655 "mfps\t%0, %1" \ 655 "mfps\t%0, %1" \
656 : "=r" (__res) \ 656 : "=r" (__res) \
657 : "i" (counter)); \ 657 : "i" (counter)); \
658 \ 658 \
659 __res; \ 659 __res; \
660 }) 660 })
661 661
662 #define write_r10k_perf_cntl(counter,val) \ 662 #define write_r10k_perf_cntl(counter,val) \
663 do { \ 663 do { \
664 __asm__ __volatile__( \ 664 __asm__ __volatile__( \
665 "mtps\t%0, %1" \ 665 "mtps\t%0, %1" \
666 : \ 666 : \
667 : "r" (val), "i" (counter)); \ 667 : "r" (val), "i" (counter)); \
668 } while (0) 668 } while (0)
669 669
670 670
671 /* 671 /*
672 * Macros to access the system control coprocessor 672 * Macros to access the system control coprocessor
673 */ 673 */
674 674
675 #define __read_32bit_c0_register(source, sel) \ 675 #define __read_32bit_c0_register(source, sel) \
676 ({ int __res; \ 676 ({ int __res; \
677 if (sel == 0) \ 677 if (sel == 0) \
678 __asm__ __volatile__( \ 678 __asm__ __volatile__( \
679 "mfc0\t%0, " #source "\n\t" \ 679 "mfc0\t%0, " #source "\n\t" \
680 : "=r" (__res)); \ 680 : "=r" (__res)); \
681 else \ 681 else \
682 __asm__ __volatile__( \ 682 __asm__ __volatile__( \
683 ".set\tmips32\n\t" \ 683 ".set\tmips32\n\t" \
684 "mfc0\t%0, " #source ", " #sel "\n\t" \ 684 "mfc0\t%0, " #source ", " #sel "\n\t" \
685 ".set\tmips0\n\t" \ 685 ".set\tmips0\n\t" \
686 : "=r" (__res)); \ 686 : "=r" (__res)); \
687 __res; \ 687 __res; \
688 }) 688 })
689 689
690 #define __read_64bit_c0_register(source, sel) \ 690 #define __read_64bit_c0_register(source, sel) \
691 ({ unsigned long long __res; \ 691 ({ unsigned long long __res; \
692 if (sizeof(unsigned long) == 4) \ 692 if (sizeof(unsigned long) == 4) \
693 __res = __read_64bit_c0_split(source, sel); \ 693 __res = __read_64bit_c0_split(source, sel); \
694 else if (sel == 0) \ 694 else if (sel == 0) \
695 __asm__ __volatile__( \ 695 __asm__ __volatile__( \
696 ".set\tmips3\n\t" \ 696 ".set\tmips3\n\t" \
697 "dmfc0\t%0, " #source "\n\t" \ 697 "dmfc0\t%0, " #source "\n\t" \
698 ".set\tmips0" \ 698 ".set\tmips0" \
699 : "=r" (__res)); \ 699 : "=r" (__res)); \
700 else \ 700 else \
701 __asm__ __volatile__( \ 701 __asm__ __volatile__( \
702 ".set\tmips64\n\t" \ 702 ".set\tmips64\n\t" \
703 "dmfc0\t%0, " #source ", " #sel "\n\t" \ 703 "dmfc0\t%0, " #source ", " #sel "\n\t" \
704 ".set\tmips0" \ 704 ".set\tmips0" \
705 : "=r" (__res)); \ 705 : "=r" (__res)); \
706 __res; \ 706 __res; \
707 }) 707 })
708 708
709 #define __write_32bit_c0_register(register, sel, value) \ 709 #define __write_32bit_c0_register(register, sel, value) \
710 do { \ 710 do { \
711 if (sel == 0) \ 711 if (sel == 0) \
712 __asm__ __volatile__( \ 712 __asm__ __volatile__( \
713 "mtc0\t%z0, " #register "\n\t" \ 713 "mtc0\t%z0, " #register "\n\t" \
714 : : "Jr" ((unsigned int)(value))); \ 714 : : "Jr" ((unsigned int)(value))); \
715 else \ 715 else \
716 __asm__ __volatile__( \ 716 __asm__ __volatile__( \
717 ".set\tmips32\n\t" \ 717 ".set\tmips32\n\t" \
718 "mtc0\t%z0, " #register ", " #sel "\n\t" \ 718 "mtc0\t%z0, " #register ", " #sel "\n\t" \
719 ".set\tmips0" \ 719 ".set\tmips0" \
720 : : "Jr" ((unsigned int)(value))); \ 720 : : "Jr" ((unsigned int)(value))); \
721 } while (0) 721 } while (0)
722 722
723 #define __write_64bit_c0_register(register, sel, value) \ 723 #define __write_64bit_c0_register(register, sel, value) \
724 do { \ 724 do { \
725 if (sizeof(unsigned long) == 4) \ 725 if (sizeof(unsigned long) == 4) \
726 __write_64bit_c0_split(register, sel, value); \ 726 __write_64bit_c0_split(register, sel, value); \
727 else if (sel == 0) \ 727 else if (sel == 0) \
728 __asm__ __volatile__( \ 728 __asm__ __volatile__( \
729 ".set\tmips3\n\t" \ 729 ".set\tmips3\n\t" \
730 "dmtc0\t%z0, " #register "\n\t" \ 730 "dmtc0\t%z0, " #register "\n\t" \
731 ".set\tmips0" \ 731 ".set\tmips0" \
732 : : "Jr" (value)); \ 732 : : "Jr" (value)); \
733 else \ 733 else \
734 __asm__ __volatile__( \ 734 __asm__ __volatile__( \
735 ".set\tmips64\n\t" \ 735 ".set\tmips64\n\t" \
736 "dmtc0\t%z0, " #register ", " #sel "\n\t" \ 736 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
737 ".set\tmips0" \ 737 ".set\tmips0" \
738 : : "Jr" (value)); \ 738 : : "Jr" (value)); \
739 } while (0) 739 } while (0)
740 740
741 #define __read_ulong_c0_register(reg, sel) \ 741 #define __read_ulong_c0_register(reg, sel) \
742 ((sizeof(unsigned long) == 4) ? \ 742 ((sizeof(unsigned long) == 4) ? \
743 (unsigned long) __read_32bit_c0_register(reg, sel) : \ 743 (unsigned long) __read_32bit_c0_register(reg, sel) : \
744 (unsigned long) __read_64bit_c0_register(reg, sel)) 744 (unsigned long) __read_64bit_c0_register(reg, sel))
745 745
746 #define __write_ulong_c0_register(reg, sel, val) \ 746 #define __write_ulong_c0_register(reg, sel, val) \
747 do { \ 747 do { \
748 if (sizeof(unsigned long) == 4) \ 748 if (sizeof(unsigned long) == 4) \
749 __write_32bit_c0_register(reg, sel, val); \ 749 __write_32bit_c0_register(reg, sel, val); \
750 else \ 750 else \
751 __write_64bit_c0_register(reg, sel, val); \ 751 __write_64bit_c0_register(reg, sel, val); \
752 } while (0) 752 } while (0)
753 753
754 /* 754 /*
755 * On RM7000/RM9000 these are uses to access cop0 set 1 registers 755 * On RM7000/RM9000 these are uses to access cop0 set 1 registers
756 */ 756 */
757 #define __read_32bit_c0_ctrl_register(source) \ 757 #define __read_32bit_c0_ctrl_register(source) \
758 ({ int __res; \ 758 ({ int __res; \
759 __asm__ __volatile__( \ 759 __asm__ __volatile__( \
760 "cfc0\t%0, " #source "\n\t" \ 760 "cfc0\t%0, " #source "\n\t" \
761 : "=r" (__res)); \ 761 : "=r" (__res)); \
762 __res; \ 762 __res; \
763 }) 763 })
764 764
765 #define __write_32bit_c0_ctrl_register(register, value) \ 765 #define __write_32bit_c0_ctrl_register(register, value) \
766 do { \ 766 do { \
767 __asm__ __volatile__( \ 767 __asm__ __volatile__( \
768 "ctc0\t%z0, " #register "\n\t" \ 768 "ctc0\t%z0, " #register "\n\t" \
769 : : "Jr" ((unsigned int)(value))); \ 769 : : "Jr" ((unsigned int)(value))); \
770 } while (0) 770 } while (0)
771 771
772 /* 772 /*
773 * These versions are only needed for systems with more than 38 bits of 773 * These versions are only needed for systems with more than 38 bits of
774 * physical address space running the 32-bit kernel. That's none atm :-) 774 * physical address space running the 32-bit kernel. That's none atm :-)
775 */ 775 */
776 #define __read_64bit_c0_split(source, sel) \ 776 #define __read_64bit_c0_split(source, sel) \
777 ({ \ 777 ({ \
778 unsigned long long __val; \ 778 unsigned long long __val; \
779 unsigned long __flags; \ 779 unsigned long __flags; \
780 \ 780 \
781 local_irq_save(__flags); \ 781 local_irq_save(__flags); \
782 if (sel == 0) \ 782 if (sel == 0) \
783 __asm__ __volatile__( \ 783 __asm__ __volatile__( \
784 ".set\tmips64\n\t" \ 784 ".set\tmips64\n\t" \
785 "dmfc0\t%M0, " #source "\n\t" \ 785 "dmfc0\t%M0, " #source "\n\t" \
786 "dsll\t%L0, %M0, 32\n\t" \ 786 "dsll\t%L0, %M0, 32\n\t" \
787 "dsra\t%M0, %M0, 32\n\t" \ 787 "dsra\t%M0, %M0, 32\n\t" \
788 "dsra\t%L0, %L0, 32\n\t" \ 788 "dsra\t%L0, %L0, 32\n\t" \
789 ".set\tmips0" \ 789 ".set\tmips0" \
790 : "=r" (__val)); \ 790 : "=r" (__val)); \
791 else \ 791 else \
792 __asm__ __volatile__( \ 792 __asm__ __volatile__( \
793 ".set\tmips64\n\t" \ 793 ".set\tmips64\n\t" \
794 "dmfc0\t%M0, " #source ", " #sel "\n\t" \ 794 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
795 "dsll\t%L0, %M0, 32\n\t" \ 795 "dsll\t%L0, %M0, 32\n\t" \
796 "dsra\t%M0, %M0, 32\n\t" \ 796 "dsra\t%M0, %M0, 32\n\t" \
797 "dsra\t%L0, %L0, 32\n\t" \ 797 "dsra\t%L0, %L0, 32\n\t" \
798 ".set\tmips0" \ 798 ".set\tmips0" \
799 : "=r" (__val)); \ 799 : "=r" (__val)); \
800 local_irq_restore(__flags); \ 800 local_irq_restore(__flags); \
801 \ 801 \
802 __val; \ 802 __val; \
803 }) 803 })
804 804
805 #define __write_64bit_c0_split(source, sel, val) \ 805 #define __write_64bit_c0_split(source, sel, val) \
806 do { \ 806 do { \
807 unsigned long __flags; \ 807 unsigned long __flags; \
808 \ 808 \
809 local_irq_save(__flags); \ 809 local_irq_save(__flags); \
810 if (sel == 0) \ 810 if (sel == 0) \
811 __asm__ __volatile__( \ 811 __asm__ __volatile__( \
812 ".set\tmips64\n\t" \ 812 ".set\tmips64\n\t" \
813 "dsll\t%L0, %L0, 32\n\t" \ 813 "dsll\t%L0, %L0, 32\n\t" \
814 "dsrl\t%L0, %L0, 32\n\t" \ 814 "dsrl\t%L0, %L0, 32\n\t" \
815 "dsll\t%M0, %M0, 32\n\t" \ 815 "dsll\t%M0, %M0, 32\n\t" \
816 "or\t%L0, %L0, %M0\n\t" \ 816 "or\t%L0, %L0, %M0\n\t" \
817 "dmtc0\t%L0, " #source "\n\t" \ 817 "dmtc0\t%L0, " #source "\n\t" \
818 ".set\tmips0" \ 818 ".set\tmips0" \
819 : : "r" (val)); \ 819 : : "r" (val)); \
820 else \ 820 else \
821 __asm__ __volatile__( \ 821 __asm__ __volatile__( \
822 ".set\tmips64\n\t" \ 822 ".set\tmips64\n\t" \
823 "dsll\t%L0, %L0, 32\n\t" \ 823 "dsll\t%L0, %L0, 32\n\t" \
824 "dsrl\t%L0, %L0, 32\n\t" \ 824 "dsrl\t%L0, %L0, 32\n\t" \
825 "dsll\t%M0, %M0, 32\n\t" \ 825 "dsll\t%M0, %M0, 32\n\t" \
826 "or\t%L0, %L0, %M0\n\t" \ 826 "or\t%L0, %L0, %M0\n\t" \
827 "dmtc0\t%L0, " #source ", " #sel "\n\t" \ 827 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
828 ".set\tmips0" \ 828 ".set\tmips0" \
829 : : "r" (val)); \ 829 : : "r" (val)); \
830 local_irq_restore(__flags); \ 830 local_irq_restore(__flags); \
831 } while (0) 831 } while (0)
832 832
833 #define read_c0_index() __read_32bit_c0_register($0, 0) 833 #define read_c0_index() __read_32bit_c0_register($0, 0)
834 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val) 834 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
835 835
836 #define read_c0_random() __read_32bit_c0_register($1, 0) 836 #define read_c0_random() __read_32bit_c0_register($1, 0)
837 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val) 837 #define write_c0_random(val) __write_32bit_c0_register($1, 0, val)
838 838
839 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0) 839 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
840 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val) 840 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
841 841
842 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0) 842 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
843 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val) 843 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
844 844
845 #define read_c0_conf() __read_32bit_c0_register($3, 0) 845 #define read_c0_conf() __read_32bit_c0_register($3, 0)
846 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val) 846 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
847 847
848 #define read_c0_context() __read_ulong_c0_register($4, 0) 848 #define read_c0_context() __read_ulong_c0_register($4, 0)
849 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val) 849 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
850 850
851 #define read_c0_userlocal() __read_ulong_c0_register($4, 2) 851 #define read_c0_userlocal() __read_ulong_c0_register($4, 2)
852 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val) 852 #define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
853 853
854 #define read_c0_pagemask() __read_32bit_c0_register($5, 0) 854 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
855 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) 855 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
856 856
857 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1) 857 #define read_c0_pagegrain() __read_32bit_c0_register($5, 1)
858 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) 858 #define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val)
859 859
860 #define read_c0_wired() __read_32bit_c0_register($6, 0) 860 #define read_c0_wired() __read_32bit_c0_register($6, 0)
861 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) 861 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
862 862
863 #define read_c0_info() __read_32bit_c0_register($7, 0) 863 #define read_c0_info() __read_32bit_c0_register($7, 0)
864 864
865 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */ 865 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
866 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val) 866 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
867 867
868 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0) 868 #define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
869 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val) 869 #define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
870 870
871 #define read_c0_count() __read_32bit_c0_register($9, 0) 871 #define read_c0_count() __read_32bit_c0_register($9, 0)
872 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val) 872 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
873 873
874 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */ 874 #define read_c0_count2() __read_32bit_c0_register($9, 6) /* pnx8550 */
875 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val) 875 #define write_c0_count2(val) __write_32bit_c0_register($9, 6, val)
876 876
877 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */ 877 #define read_c0_count3() __read_32bit_c0_register($9, 7) /* pnx8550 */
878 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val) 878 #define write_c0_count3(val) __write_32bit_c0_register($9, 7, val)
879 879
880 #define read_c0_entryhi() __read_ulong_c0_register($10, 0) 880 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
881 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val) 881 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
882 882
883 #define read_c0_compare() __read_32bit_c0_register($11, 0) 883 #define read_c0_compare() __read_32bit_c0_register($11, 0)
884 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val) 884 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
885 885
886 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */ 886 #define read_c0_compare2() __read_32bit_c0_register($11, 6) /* pnx8550 */
887 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val) 887 #define write_c0_compare2(val) __write_32bit_c0_register($11, 6, val)
888 888
889 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */ 889 #define read_c0_compare3() __read_32bit_c0_register($11, 7) /* pnx8550 */
890 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val) 890 #define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
891 891
892 #define read_c0_status() __read_32bit_c0_register($12, 0) 892 #define read_c0_status() __read_32bit_c0_register($12, 0)
893 #ifdef CONFIG_MIPS_MT_SMTC 893 #ifdef CONFIG_MIPS_MT_SMTC
894 #define write_c0_status(val) \ 894 #define write_c0_status(val) \
895 do { \ 895 do { \
896 __write_32bit_c0_register($12, 0, val); \ 896 __write_32bit_c0_register($12, 0, val); \
897 __ehb(); \ 897 __ehb(); \
898 } while (0) 898 } while (0)
899 #else 899 #else
900 /* 900 /*
901 * Legacy non-SMTC code, which may be hazardous 901 * Legacy non-SMTC code, which may be hazardous
902 * but which might not support EHB 902 * but which might not support EHB
903 */ 903 */
904 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val) 904 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
905 #endif /* CONFIG_MIPS_MT_SMTC */ 905 #endif /* CONFIG_MIPS_MT_SMTC */
906 906
907 #define read_c0_cause() __read_32bit_c0_register($13, 0) 907 #define read_c0_cause() __read_32bit_c0_register($13, 0)
908 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val) 908 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
909 909
910 #define read_c0_epc() __read_ulong_c0_register($14, 0) 910 #define read_c0_epc() __read_ulong_c0_register($14, 0)
911 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val) 911 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
912 912
913 #define read_c0_prid() __read_32bit_c0_register($15, 0) 913 #define read_c0_prid() __read_32bit_c0_register($15, 0)
914 914
915 #define read_c0_config() __read_32bit_c0_register($16, 0) 915 #define read_c0_config() __read_32bit_c0_register($16, 0)
916 #define read_c0_config1() __read_32bit_c0_register($16, 1) 916 #define read_c0_config1() __read_32bit_c0_register($16, 1)
917 #define read_c0_config2() __read_32bit_c0_register($16, 2) 917 #define read_c0_config2() __read_32bit_c0_register($16, 2)
918 #define read_c0_config3() __read_32bit_c0_register($16, 3) 918 #define read_c0_config3() __read_32bit_c0_register($16, 3)
919 #define read_c0_config4() __read_32bit_c0_register($16, 4) 919 #define read_c0_config4() __read_32bit_c0_register($16, 4)
920 #define read_c0_config5() __read_32bit_c0_register($16, 5) 920 #define read_c0_config5() __read_32bit_c0_register($16, 5)
921 #define read_c0_config6() __read_32bit_c0_register($16, 6) 921 #define read_c0_config6() __read_32bit_c0_register($16, 6)
922 #define read_c0_config7() __read_32bit_c0_register($16, 7) 922 #define read_c0_config7() __read_32bit_c0_register($16, 7)
923 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val) 923 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
924 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val) 924 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
925 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val) 925 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
926 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val) 926 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
927 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val) 927 #define write_c0_config4(val) __write_32bit_c0_register($16, 4, val)
928 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val) 928 #define write_c0_config5(val) __write_32bit_c0_register($16, 5, val)
929 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val) 929 #define write_c0_config6(val) __write_32bit_c0_register($16, 6, val)
930 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val) 930 #define write_c0_config7(val) __write_32bit_c0_register($16, 7, val)
931 931
932 /* 932 /*
933 * The WatchLo register. There may be up to 8 of them. 933 * The WatchLo register. There may be up to 8 of them.
934 */ 934 */
935 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0) 935 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
936 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1) 936 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
937 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2) 937 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
938 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3) 938 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
939 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4) 939 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
940 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5) 940 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
941 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6) 941 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
942 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7) 942 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
943 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val) 943 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
944 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val) 944 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
945 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val) 945 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
946 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val) 946 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
947 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val) 947 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
948 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val) 948 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
949 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val) 949 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
950 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val) 950 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
951 951
952 /* 952 /*
953 * The WatchHi register. There may be up to 8 of them. 953 * The WatchHi register. There may be up to 8 of them.
954 */ 954 */
955 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0) 955 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
956 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1) 956 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
957 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2) 957 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
958 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3) 958 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
959 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4) 959 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
960 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5) 960 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
961 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6) 961 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
962 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7) 962 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
963 963
964 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val) 964 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
965 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val) 965 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
966 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val) 966 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
967 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val) 967 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
968 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val) 968 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
969 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val) 969 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
970 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val) 970 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
971 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val) 971 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
972 972
973 #define read_c0_xcontext() __read_ulong_c0_register($20, 0) 973 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
974 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val) 974 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
975 975
976 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20) 976 #define read_c0_intcontrol() __read_32bit_c0_ctrl_register($20)
977 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val) 977 #define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
978 978
979 #define read_c0_framemask() __read_32bit_c0_register($21, 0) 979 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
980 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val) 980 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
981 981
982 #define read_c0_diag() __read_32bit_c0_register($22, 0) 982 #define read_c0_diag() __read_32bit_c0_register($22, 0)
983 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val) 983 #define write_c0_diag(val) __write_32bit_c0_register($22, 0, val)
984 984
985 #define read_c0_diag1() __read_32bit_c0_register($22, 1) 985 #define read_c0_diag1() __read_32bit_c0_register($22, 1)
986 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val) 986 #define write_c0_diag1(val) __write_32bit_c0_register($22, 1, val)
987 987
988 #define read_c0_diag2() __read_32bit_c0_register($22, 2) 988 #define read_c0_diag2() __read_32bit_c0_register($22, 2)
989 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val) 989 #define write_c0_diag2(val) __write_32bit_c0_register($22, 2, val)
990 990
991 #define read_c0_diag3() __read_32bit_c0_register($22, 3) 991 #define read_c0_diag3() __read_32bit_c0_register($22, 3)
992 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val) 992 #define write_c0_diag3(val) __write_32bit_c0_register($22, 3, val)
993 993
994 #define read_c0_diag4() __read_32bit_c0_register($22, 4) 994 #define read_c0_diag4() __read_32bit_c0_register($22, 4)
995 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val) 995 #define write_c0_diag4(val) __write_32bit_c0_register($22, 4, val)
996 996
997 #define read_c0_diag5() __read_32bit_c0_register($22, 5) 997 #define read_c0_diag5() __read_32bit_c0_register($22, 5)
998 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val) 998 #define write_c0_diag5(val) __write_32bit_c0_register($22, 5, val)
999 999
1000 #define read_c0_debug() __read_32bit_c0_register($23, 0) 1000 #define read_c0_debug() __read_32bit_c0_register($23, 0)
1001 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val) 1001 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
1002 1002
1003 #define read_c0_depc() __read_ulong_c0_register($24, 0) 1003 #define read_c0_depc() __read_ulong_c0_register($24, 0)
1004 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val) 1004 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
1005 1005
1006 /* 1006 /*
1007 * MIPS32 / MIPS64 performance counters 1007 * MIPS32 / MIPS64 performance counters
1008 */ 1008 */
1009 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0) 1009 #define read_c0_perfctrl0() __read_32bit_c0_register($25, 0)
1010 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val) 1010 #define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
1011 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1) 1011 #define read_c0_perfcntr0() __read_32bit_c0_register($25, 1)
1012 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val) 1012 #define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
1013 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1) 1013 #define read_c0_perfcntr0_64() __read_64bit_c0_register($25, 1)
1014 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val) 1014 #define write_c0_perfcntr0_64(val) __write_64bit_c0_register($25, 1, val)
1015 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2) 1015 #define read_c0_perfctrl1() __read_32bit_c0_register($25, 2)
1016 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val) 1016 #define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
1017 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3) 1017 #define read_c0_perfcntr1() __read_32bit_c0_register($25, 3)
1018 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val) 1018 #define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
1019 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3) 1019 #define read_c0_perfcntr1_64() __read_64bit_c0_register($25, 3)
1020 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val) 1020 #define write_c0_perfcntr1_64(val) __write_64bit_c0_register($25, 3, val)
1021 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4) 1021 #define read_c0_perfctrl2() __read_32bit_c0_register($25, 4)
1022 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val) 1022 #define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
1023 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5) 1023 #define read_c0_perfcntr2() __read_32bit_c0_register($25, 5)
1024 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val) 1024 #define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
1025 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5) 1025 #define read_c0_perfcntr2_64() __read_64bit_c0_register($25, 5)
1026 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val) 1026 #define write_c0_perfcntr2_64(val) __write_64bit_c0_register($25, 5, val)
1027 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6) 1027 #define read_c0_perfctrl3() __read_32bit_c0_register($25, 6)
1028 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val) 1028 #define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
1029 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7) 1029 #define read_c0_perfcntr3() __read_32bit_c0_register($25, 7)
1030 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val) 1030 #define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
1031 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7) 1031 #define read_c0_perfcntr3_64() __read_64bit_c0_register($25, 7)
1032 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val) 1032 #define write_c0_perfcntr3_64(val) __write_64bit_c0_register($25, 7, val)
1033 1033
1034 #define read_c0_ecc() __read_32bit_c0_register($26, 0) 1034 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
1035 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val) 1035 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
1036 1036
1037 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1) 1037 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
1038 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val) 1038 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
1039 1039
1040 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0) 1040 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
1041 1041
1042 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1) 1042 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
1043 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val) 1043 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
1044 1044
1045 #define read_c0_taglo() __read_32bit_c0_register($28, 0) 1045 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
1046 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val) 1046 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
1047 1047
1048 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2) 1048 #define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
1049 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val) 1049 #define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
1050 1050
1051 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3) 1051 #define read_c0_ddatalo() __read_32bit_c0_register($28, 3)
1052 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val) 1052 #define write_c0_ddatalo(val) __write_32bit_c0_register($28, 3, val)
1053 1053
1054 #define read_c0_staglo() __read_32bit_c0_register($28, 4) 1054 #define read_c0_staglo() __read_32bit_c0_register($28, 4)
1055 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val) 1055 #define write_c0_staglo(val) __write_32bit_c0_register($28, 4, val)
1056 1056
1057 #define read_c0_taghi() __read_32bit_c0_register($29, 0) 1057 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
1058 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val) 1058 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
1059 1059
1060 #define read_c0_errorepc() __read_ulong_c0_register($30, 0) 1060 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
1061 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val) 1061 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
1062 1062
1063 /* MIPSR2 */ 1063 /* MIPSR2 */
1064 #define read_c0_hwrena() __read_32bit_c0_register($7, 0) 1064 #define read_c0_hwrena() __read_32bit_c0_register($7, 0)
1065 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val) 1065 #define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
1066 1066
1067 #define read_c0_intctl() __read_32bit_c0_register($12, 1) 1067 #define read_c0_intctl() __read_32bit_c0_register($12, 1)
1068 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val) 1068 #define write_c0_intctl(val) __write_32bit_c0_register($12, 1, val)
1069 1069
1070 #define read_c0_srsctl() __read_32bit_c0_register($12, 2) 1070 #define read_c0_srsctl() __read_32bit_c0_register($12, 2)
1071 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val) 1071 #define write_c0_srsctl(val) __write_32bit_c0_register($12, 2, val)
1072 1072
1073 #define read_c0_srsmap() __read_32bit_c0_register($12, 3) 1073 #define read_c0_srsmap() __read_32bit_c0_register($12, 3)
1074 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val) 1074 #define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
1075 1075
1076 #define read_c0_ebase() __read_32bit_c0_register($15, 1) 1076 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
1077 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val) 1077 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
1078 1078
1079 1079
1080 /* Cavium OCTEON (cnMIPS) */ 1080 /* Cavium OCTEON (cnMIPS) */
1081 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6) 1081 #define read_c0_cvmcount() __read_ulong_c0_register($9, 6)
1082 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val) 1082 #define write_c0_cvmcount(val) __write_ulong_c0_register($9, 6, val)
1083 1083
1084 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7) 1084 #define read_c0_cvmctl() __read_64bit_c0_register($9, 7)
1085 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val) 1085 #define write_c0_cvmctl(val) __write_64bit_c0_register($9, 7, val)
1086 1086
1087 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7) 1087 #define read_c0_cvmmemctl() __read_64bit_c0_register($11, 7)
1088 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val) 1088 #define write_c0_cvmmemctl(val) __write_64bit_c0_register($11, 7, val)
1089 /* 1089 /*
1090 * The cacheerr registers are not standardized. On OCTEON, they are 1090 * The cacheerr registers are not standardized. On OCTEON, they are
1091 * 64 bits wide. 1091 * 64 bits wide.
1092 */ 1092 */
1093 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0) 1093 #define read_octeon_c0_icacheerr() __read_64bit_c0_register($27, 0)
1094 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val) 1094 #define write_octeon_c0_icacheerr(val) __write_64bit_c0_register($27, 0, val)
1095 1095
1096 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1) 1096 #define read_octeon_c0_dcacheerr() __read_64bit_c0_register($27, 1)
1097 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val) 1097 #define write_octeon_c0_dcacheerr(val) __write_64bit_c0_register($27, 1, val)
1098 1098
1099 /* BMIPS3300 */ 1099 /* BMIPS3300 */
1100 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0) 1100 #define read_c0_brcm_config_0() __read_32bit_c0_register($22, 0)
1101 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val) 1101 #define write_c0_brcm_config_0(val) __write_32bit_c0_register($22, 0, val)
1102 1102
1103 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4) 1103 #define read_c0_brcm_bus_pll() __read_32bit_c0_register($22, 4)
1104 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val) 1104 #define write_c0_brcm_bus_pll(val) __write_32bit_c0_register($22, 4, val)
1105 1105
1106 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5) 1106 #define read_c0_brcm_reset() __read_32bit_c0_register($22, 5)
1107 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val) 1107 #define write_c0_brcm_reset(val) __write_32bit_c0_register($22, 5, val)
1108 1108
1109 /* BMIPS43xx */ 1109 /* BMIPS43xx */
1110 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1) 1110 #define read_c0_brcm_cmt_intr() __read_32bit_c0_register($22, 1)
1111 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val) 1111 #define write_c0_brcm_cmt_intr(val) __write_32bit_c0_register($22, 1, val)
1112 1112
1113 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2) 1113 #define read_c0_brcm_cmt_ctrl() __read_32bit_c0_register($22, 2)
1114 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val) 1114 #define write_c0_brcm_cmt_ctrl(val) __write_32bit_c0_register($22, 2, val)
1115 1115
1116 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3) 1116 #define read_c0_brcm_cmt_local() __read_32bit_c0_register($22, 3)
1117 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val) 1117 #define write_c0_brcm_cmt_local(val) __write_32bit_c0_register($22, 3, val)
1118 1118
1119 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5) 1119 #define read_c0_brcm_config_1() __read_32bit_c0_register($22, 5)
1120 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val) 1120 #define write_c0_brcm_config_1(val) __write_32bit_c0_register($22, 5, val)
1121 1121
1122 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6) 1122 #define read_c0_brcm_cbr() __read_32bit_c0_register($22, 6)
1123 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val) 1123 #define write_c0_brcm_cbr(val) __write_32bit_c0_register($22, 6, val)
1124 1124
1125 /* BMIPS5000 */ 1125 /* BMIPS5000 */
1126 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0) 1126 #define read_c0_brcm_config() __read_32bit_c0_register($22, 0)
1127 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val) 1127 #define write_c0_brcm_config(val) __write_32bit_c0_register($22, 0, val)
1128 1128
1129 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1) 1129 #define read_c0_brcm_mode() __read_32bit_c0_register($22, 1)
1130 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val) 1130 #define write_c0_brcm_mode(val) __write_32bit_c0_register($22, 1, val)
1131 1131
1132 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2) 1132 #define read_c0_brcm_action() __read_32bit_c0_register($22, 2)
1133 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val) 1133 #define write_c0_brcm_action(val) __write_32bit_c0_register($22, 2, val)
1134 1134
1135 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3) 1135 #define read_c0_brcm_edsp() __read_32bit_c0_register($22, 3)
1136 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val) 1136 #define write_c0_brcm_edsp(val) __write_32bit_c0_register($22, 3, val)
1137 1137
1138 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4) 1138 #define read_c0_brcm_bootvec() __read_32bit_c0_register($22, 4)
1139 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val) 1139 #define write_c0_brcm_bootvec(val) __write_32bit_c0_register($22, 4, val)
1140 1140
1141 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7) 1141 #define read_c0_brcm_sleepcount() __read_32bit_c0_register($22, 7)
1142 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val) 1142 #define write_c0_brcm_sleepcount(val) __write_32bit_c0_register($22, 7, val)
1143 1143
1144 /* 1144 /*
1145 * Macros to access the floating point coprocessor control registers 1145 * Macros to access the floating point coprocessor control registers
1146 */ 1146 */
1147 #define read_32bit_cp1_register(source) \ 1147 #define read_32bit_cp1_register(source) \
1148 ({ \ 1148 ({ \
1149 int __res; \ 1149 int __res; \
1150 \ 1150 \
1151 __asm__ __volatile__( \ 1151 __asm__ __volatile__( \
1152 " .set push \n" \ 1152 " .set push \n" \
1153 " .set reorder \n" \ 1153 " .set reorder \n" \
1154 " # gas fails to assemble cfc1 for some archs, \n" \ 1154 " # gas fails to assemble cfc1 for some archs, \n" \
1155 " # like Octeon. \n" \ 1155 " # like Octeon. \n" \
1156 " .set mips1 \n" \ 1156 " .set mips1 \n" \
1157 " cfc1 %0,"STR(source)" \n" \ 1157 " cfc1 %0,"STR(source)" \n" \
1158 " .set pop \n" \ 1158 " .set pop \n" \
1159 : "=r" (__res)); \ 1159 : "=r" (__res)); \
1160 __res; \ 1160 __res; \
1161 }) 1161 })
1162 1162
1163 #ifdef HAVE_AS_DSP 1163 #ifdef HAVE_AS_DSP
1164 #define rddsp(mask) \ 1164 #define rddsp(mask) \
1165 ({ \ 1165 ({ \
1166 unsigned int __dspctl; \ 1166 unsigned int __dspctl; \
1167 \ 1167 \
1168 __asm__ __volatile__( \ 1168 __asm__ __volatile__( \
1169 " .set push \n" \
1170 " .set dsp \n" \
1169 " rddsp %0, %x1 \n" \ 1171 " rddsp %0, %x1 \n" \
1172 " .set pop \n" \
1170 : "=r" (__dspctl) \ 1173 : "=r" (__dspctl) \
1171 : "i" (mask)); \ 1174 : "i" (mask)); \
1172 __dspctl; \ 1175 __dspctl; \
1173 }) 1176 })
1174 1177
1175 #define wrdsp(val, mask) \ 1178 #define wrdsp(val, mask) \
1176 do { \ 1179 do { \
1177 __asm__ __volatile__( \ 1180 __asm__ __volatile__( \
1181 " .set push \n" \
1182 " .set dsp \n" \
1178 " wrdsp %0, %x1 \n" \ 1183 " wrdsp %0, %x1 \n" \
1184 " .set pop \n" \
1179 : \ 1185 : \
1180 : "r" (val), "i" (mask)); \ 1186 : "r" (val), "i" (mask)); \
1181 } while (0) 1187 } while (0)
1182 1188
1183 #define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;}) 1189 #define mflo0() \
1184 #define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;}) 1190 ({ \
1185 #define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;}) 1191 long mflo0; \
1186 #define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;}) 1192 __asm__( \
1193 " .set push \n" \
1194 " .set dsp \n" \
1195 " mflo %0, $ac0 \n" \
1196 " .set pop \n" \
1197 : "=r" (mflo0)); \
1198 mflo0; \
1199 })
1187 1200
1188 #define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;}) 1201 #define mflo1() \
1189 #define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;}) 1202 ({ \
1190 #define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;}) 1203 long mflo1; \
1191 #define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;}) 1204 __asm__( \
1205 " .set push \n" \
1206 " .set dsp \n" \
1207 " mflo %0, $ac1 \n" \
1208 " .set pop \n" \
1209 : "=r" (mflo1)); \
1210 mflo1; \
1211 })
1192 1212
1193 #define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x)) 1213 #define mflo2() \
1194 #define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x)) 1214 ({ \
1195 #define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x)) 1215 long mflo2; \
1196 #define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x)) 1216 __asm__( \
1217 " .set push \n" \
1218 " .set dsp \n" \
1219 " mflo %0, $ac2 \n" \
1220 " .set pop \n" \
1221 : "=r" (mflo2)); \
1222 mflo2; \
1223 })
1197 1224
1198 #define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x)) 1225 #define mflo3() \
1199 #define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x)) 1226 ({ \
1200 #define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x)) 1227 long mflo3; \
1201 #define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x)) 1228 __asm__( \
1229 " .set push \n" \
1230 " .set dsp \n" \
1231 " mflo %0, $ac3 \n" \
1232 " .set pop \n" \
1233 : "=r" (mflo3)); \
1234 mflo3; \
1235 })
1236
1237 #define mfhi0() \
1238 ({ \
1239 long mfhi0; \
1240 __asm__( \
1241 " .set push \n" \
1242 " .set dsp \n" \
1243 " mfhi %0, $ac0 \n" \
1244 " .set pop \n" \
1245 : "=r" (mfhi0)); \
1246 mfhi0; \
1247 })
1248
1249 #define mfhi1() \
1250 ({ \
1251 long mfhi1; \
1252 __asm__( \
1253 " .set push \n" \
1254 " .set dsp \n" \
1255 " mfhi %0, $ac1 \n" \
1256 " .set pop \n" \
1257 : "=r" (mfhi1)); \
1258 mfhi1; \
1259 })
1260
1261 #define mfhi2() \
1262 ({ \
1263 long mfhi2; \
1264 __asm__( \
1265 " .set push \n" \
1266 " .set dsp \n" \
1267 " mfhi %0, $ac2 \n" \
1268 " .set pop \n" \
1269 : "=r" (mfhi2)); \
1270 mfhi2; \
1271 })
1272
1273 #define mfhi3() \
1274 ({ \
1275 long mfhi3; \
1276 __asm__( \
1277 " .set push \n" \
1278 " .set dsp \n" \
1279 " mfhi %0, $ac3 \n" \
1280 " .set pop \n" \
1281 : "=r" (mfhi3)); \
1282 mfhi3; \
1283 })
1284
1285
1286 #define mtlo0(x) \
1287 ({ \
1288 __asm__( \
1289 " .set push \n" \
1290 " .set dsp \n" \
1291 " mtlo %0, $ac0 \n" \
1292 " .set pop \n" \
1293 : \
1294 : "r" (x)); \
1295 })
1296
1297 #define mtlo1(x) \
1298 ({ \
1299 __asm__( \
1300 " .set push \n" \
1301 " .set dsp \n" \
1302 " mtlo %0, $ac1 \n" \
1303 " .set pop \n" \
1304 : \
1305 : "r" (x)); \
1306 })
1307
1308 #define mtlo2(x) \
1309 ({ \
1310 __asm__( \
1311 " .set push \n" \
1312 " .set dsp \n" \
1313 " mtlo %0, $ac2 \n" \
1314 " .set pop \n" \
1315 : \
1316 : "r" (x)); \
1317 })
1318
1319 #define mtlo3(x) \
1320 ({ \
1321 __asm__( \
1322 " .set push \n" \
1323 " .set dsp \n" \
1324 " mtlo %0, $ac3 \n" \
1325 " .set pop \n" \
1326 : \
1327 : "r" (x)); \
1328 })
1329
1330 #define mthi0(x) \
1331 ({ \
1332 __asm__( \
1333 " .set push \n" \
1334 " .set dsp \n" \
1335 " mthi %0, $ac0 \n" \
1336 " .set pop \n" \
1337 : \
1338 : "r" (x)); \
1339 })
1340
1341 #define mthi1(x) \
1342 ({ \
1343 __asm__( \
1344 " .set push \n" \
1345 " .set dsp \n" \
1346 " mthi %0, $ac1 \n" \
1347 " .set pop \n" \
1348 : \
1349 : "r" (x)); \
1350 })
1351
1352 #define mthi2(x) \
1353 ({ \
1354 __asm__( \
1355 " .set push \n" \
1356 " .set dsp \n" \
1357 " mthi %0, $ac2 \n" \
1358 " .set pop \n" \
1359 : \
1360 : "r" (x)); \
1361 })
1362
1363 #define mthi3(x) \
1364 ({ \
1365 __asm__( \
1366 " .set push \n" \
1367 " .set dsp \n" \
1368 " mthi %0, $ac3 \n" \
1369 " .set pop \n" \
1370 : \
1371 : "r" (x)); \
1372 })
1202 1373
1203 #else 1374 #else
1204 1375
1205 #ifdef CONFIG_CPU_MICROMIPS 1376 #ifdef CONFIG_CPU_MICROMIPS
1206 #define rddsp(mask) \ 1377 #define rddsp(mask) \
1207 ({ \ 1378 ({ \
1208 unsigned int __res; \ 1379 unsigned int __res; \
1209 \ 1380 \
1210 __asm__ __volatile__( \ 1381 __asm__ __volatile__( \
1211 " .set push \n" \ 1382 " .set push \n" \
1212 " .set noat \n" \ 1383 " .set noat \n" \
1213 " # rddsp $1, %x1 \n" \ 1384 " # rddsp $1, %x1 \n" \
1214 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \ 1385 " .hword ((0x0020067c | (%x1 << 14)) >> 16) \n" \
1215 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \ 1386 " .hword ((0x0020067c | (%x1 << 14)) & 0xffff) \n" \
1216 " move %0, $1 \n" \ 1387 " move %0, $1 \n" \
1217 " .set pop \n" \ 1388 " .set pop \n" \
1218 : "=r" (__res) \ 1389 : "=r" (__res) \
1219 : "i" (mask)); \ 1390 : "i" (mask)); \
1220 __res; \ 1391 __res; \
1221 }) 1392 })
1222 1393
1223 #define wrdsp(val, mask) \ 1394 #define wrdsp(val, mask) \
1224 do { \ 1395 do { \
1225 __asm__ __volatile__( \ 1396 __asm__ __volatile__( \
1226 " .set push \n" \ 1397 " .set push \n" \
1227 " .set noat \n" \ 1398 " .set noat \n" \
1228 " move $1, %0 \n" \ 1399 " move $1, %0 \n" \
1229 " # wrdsp $1, %x1 \n" \ 1400 " # wrdsp $1, %x1 \n" \
1230 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \ 1401 " .hword ((0x0020167c | (%x1 << 14)) >> 16) \n" \
1231 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \ 1402 " .hword ((0x0020167c | (%x1 << 14)) & 0xffff) \n" \
1232 " .set pop \n" \ 1403 " .set pop \n" \
1233 : \ 1404 : \
1234 : "r" (val), "i" (mask)); \ 1405 : "r" (val), "i" (mask)); \
1235 } while (0) 1406 } while (0)
1236 1407
1237 #define _umips_dsp_mfxxx(ins) \ 1408 #define _umips_dsp_mfxxx(ins) \
1238 ({ \ 1409 ({ \
1239 unsigned long __treg; \ 1410 unsigned long __treg; \
1240 \ 1411 \
1241 __asm__ __volatile__( \ 1412 __asm__ __volatile__( \
1242 " .set push \n" \ 1413 " .set push \n" \
1243 " .set noat \n" \ 1414 " .set noat \n" \
1244 " .hword 0x0001 \n" \ 1415 " .hword 0x0001 \n" \
1245 " .hword %x1 \n" \ 1416 " .hword %x1 \n" \
1246 " move %0, $1 \n" \ 1417 " move %0, $1 \n" \
1247 " .set pop \n" \ 1418 " .set pop \n" \
1248 : "=r" (__treg) \ 1419 : "=r" (__treg) \
1249 : "i" (ins)); \ 1420 : "i" (ins)); \
1250 __treg; \ 1421 __treg; \
1251 }) 1422 })
1252 1423
1253 #define _umips_dsp_mtxxx(val, ins) \ 1424 #define _umips_dsp_mtxxx(val, ins) \
1254 do { \ 1425 do { \
1255 __asm__ __volatile__( \ 1426 __asm__ __volatile__( \
1256 " .set push \n" \ 1427 " .set push \n" \
1257 " .set noat \n" \ 1428 " .set noat \n" \
1258 " move $1, %0 \n" \ 1429 " move $1, %0 \n" \
1259 " .hword 0x0001 \n" \ 1430 " .hword 0x0001 \n" \
1260 " .hword %x1 \n" \ 1431 " .hword %x1 \n" \
1261 " .set pop \n" \ 1432 " .set pop \n" \
1262 : \ 1433 : \
1263 : "r" (val), "i" (ins)); \ 1434 : "r" (val), "i" (ins)); \
1264 } while (0) 1435 } while (0)
1265 1436
1266 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c) 1437 #define _umips_dsp_mflo(reg) _umips_dsp_mfxxx((reg << 14) | 0x107c)
1267 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c) 1438 #define _umips_dsp_mfhi(reg) _umips_dsp_mfxxx((reg << 14) | 0x007c)
1268 1439
1269 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c)) 1440 #define _umips_dsp_mtlo(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x307c))
1270 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c)) 1441 #define _umips_dsp_mthi(val, reg) _umips_dsp_mtxxx(val, ((reg << 14) | 0x207c))
1271 1442
1272 #define mflo0() _umips_dsp_mflo(0) 1443 #define mflo0() _umips_dsp_mflo(0)
1273 #define mflo1() _umips_dsp_mflo(1) 1444 #define mflo1() _umips_dsp_mflo(1)
1274 #define mflo2() _umips_dsp_mflo(2) 1445 #define mflo2() _umips_dsp_mflo(2)
1275 #define mflo3() _umips_dsp_mflo(3) 1446 #define mflo3() _umips_dsp_mflo(3)
1276 1447
1277 #define mfhi0() _umips_dsp_mfhi(0) 1448 #define mfhi0() _umips_dsp_mfhi(0)
1278 #define mfhi1() _umips_dsp_mfhi(1) 1449 #define mfhi1() _umips_dsp_mfhi(1)
1279 #define mfhi2() _umips_dsp_mfhi(2) 1450 #define mfhi2() _umips_dsp_mfhi(2)
1280 #define mfhi3() _umips_dsp_mfhi(3) 1451 #define mfhi3() _umips_dsp_mfhi(3)
1281 1452
1282 #define mtlo0(x) _umips_dsp_mtlo(x, 0) 1453 #define mtlo0(x) _umips_dsp_mtlo(x, 0)
1283 #define mtlo1(x) _umips_dsp_mtlo(x, 1) 1454 #define mtlo1(x) _umips_dsp_mtlo(x, 1)
1284 #define mtlo2(x) _umips_dsp_mtlo(x, 2) 1455 #define mtlo2(x) _umips_dsp_mtlo(x, 2)
1285 #define mtlo3(x) _umips_dsp_mtlo(x, 3) 1456 #define mtlo3(x) _umips_dsp_mtlo(x, 3)
1286 1457
1287 #define mthi0(x) _umips_dsp_mthi(x, 0) 1458 #define mthi0(x) _umips_dsp_mthi(x, 0)
1288 #define mthi1(x) _umips_dsp_mthi(x, 1) 1459 #define mthi1(x) _umips_dsp_mthi(x, 1)
1289 #define mthi2(x) _umips_dsp_mthi(x, 2) 1460 #define mthi2(x) _umips_dsp_mthi(x, 2)
1290 #define mthi3(x) _umips_dsp_mthi(x, 3) 1461 #define mthi3(x) _umips_dsp_mthi(x, 3)
1291 1462
1292 #else /* !CONFIG_CPU_MICROMIPS */ 1463 #else /* !CONFIG_CPU_MICROMIPS */
1293 #define rddsp(mask) \ 1464 #define rddsp(mask) \
1294 ({ \ 1465 ({ \
1295 unsigned int __res; \ 1466 unsigned int __res; \
1296 \ 1467 \
1297 __asm__ __volatile__( \ 1468 __asm__ __volatile__( \
1298 " .set push \n" \ 1469 " .set push \n" \
1299 " .set noat \n" \ 1470 " .set noat \n" \
1300 " # rddsp $1, %x1 \n" \ 1471 " # rddsp $1, %x1 \n" \
1301 " .word 0x7c000cb8 | (%x1 << 16) \n" \ 1472 " .word 0x7c000cb8 | (%x1 << 16) \n" \
1302 " move %0, $1 \n" \ 1473 " move %0, $1 \n" \
1303 " .set pop \n" \ 1474 " .set pop \n" \
1304 : "=r" (__res) \ 1475 : "=r" (__res) \
1305 : "i" (mask)); \ 1476 : "i" (mask)); \
1306 __res; \ 1477 __res; \
1307 }) 1478 })
1308 1479
1309 #define wrdsp(val, mask) \ 1480 #define wrdsp(val, mask) \
1310 do { \ 1481 do { \
1311 __asm__ __volatile__( \ 1482 __asm__ __volatile__( \
1312 " .set push \n" \ 1483 " .set push \n" \
1313 " .set noat \n" \ 1484 " .set noat \n" \
1314 " move $1, %0 \n" \ 1485 " move $1, %0 \n" \
1315 " # wrdsp $1, %x1 \n" \ 1486 " # wrdsp $1, %x1 \n" \
1316 " .word 0x7c2004f8 | (%x1 << 11) \n" \ 1487 " .word 0x7c2004f8 | (%x1 << 11) \n" \
1317 " .set pop \n" \ 1488 " .set pop \n" \
1318 : \ 1489 : \
1319 : "r" (val), "i" (mask)); \ 1490 : "r" (val), "i" (mask)); \
1320 } while (0) 1491 } while (0)
1321 1492
1322 #define _dsp_mfxxx(ins) \ 1493 #define _dsp_mfxxx(ins) \
1323 ({ \ 1494 ({ \
1324 unsigned long __treg; \ 1495 unsigned long __treg; \
1325 \ 1496 \
1326 __asm__ __volatile__( \ 1497 __asm__ __volatile__( \
1327 " .set push \n" \ 1498 " .set push \n" \
1328 " .set noat \n" \ 1499 " .set noat \n" \
1329 " .word (0x00000810 | %1) \n" \ 1500 " .word (0x00000810 | %1) \n" \
1330 " move %0, $1 \n" \ 1501 " move %0, $1 \n" \
1331 " .set pop \n" \ 1502 " .set pop \n" \
1332 : "=r" (__treg) \ 1503 : "=r" (__treg) \
1333 : "i" (ins)); \ 1504 : "i" (ins)); \
1334 __treg; \ 1505 __treg; \
1335 }) 1506 })
1336 1507
1337 #define _dsp_mtxxx(val, ins) \ 1508 #define _dsp_mtxxx(val, ins) \
1338 do { \ 1509 do { \
1339 __asm__ __volatile__( \ 1510 __asm__ __volatile__( \
1340 " .set push \n" \ 1511 " .set push \n" \
1341 " .set noat \n" \ 1512 " .set noat \n" \
1342 " move $1, %0 \n" \ 1513 " move $1, %0 \n" \
1343 " .word (0x00200011 | %1) \n" \ 1514 " .word (0x00200011 | %1) \n" \
1344 " .set pop \n" \ 1515 " .set pop \n" \
1345 : \ 1516 : \
1346 : "r" (val), "i" (ins)); \ 1517 : "r" (val), "i" (ins)); \
1347 } while (0) 1518 } while (0)
1348 1519
1349 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002) 1520 #define _dsp_mflo(reg) _dsp_mfxxx((reg << 21) | 0x0002)
1350 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000) 1521 #define _dsp_mfhi(reg) _dsp_mfxxx((reg << 21) | 0x0000)
1351 1522
1352 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002)) 1523 #define _dsp_mtlo(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0002))
1353 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000)) 1524 #define _dsp_mthi(val, reg) _dsp_mtxxx(val, ((reg << 11) | 0x0000))
1354 1525
1355 #define mflo0() _dsp_mflo(0) 1526 #define mflo0() _dsp_mflo(0)
1356 #define mflo1() _dsp_mflo(1) 1527 #define mflo1() _dsp_mflo(1)
1357 #define mflo2() _dsp_mflo(2) 1528 #define mflo2() _dsp_mflo(2)
1358 #define mflo3() _dsp_mflo(3) 1529 #define mflo3() _dsp_mflo(3)
1359 1530
1360 #define mfhi0() _dsp_mfhi(0) 1531 #define mfhi0() _dsp_mfhi(0)
1361 #define mfhi1() _dsp_mfhi(1) 1532 #define mfhi1() _dsp_mfhi(1)
1362 #define mfhi2() _dsp_mfhi(2) 1533 #define mfhi2() _dsp_mfhi(2)
1363 #define mfhi3() _dsp_mfhi(3) 1534 #define mfhi3() _dsp_mfhi(3)
1364 1535
1365 #define mtlo0(x) _dsp_mtlo(x, 0) 1536 #define mtlo0(x) _dsp_mtlo(x, 0)
1366 #define mtlo1(x) _dsp_mtlo(x, 1) 1537 #define mtlo1(x) _dsp_mtlo(x, 1)
1367 #define mtlo2(x) _dsp_mtlo(x, 2) 1538 #define mtlo2(x) _dsp_mtlo(x, 2)
1368 #define mtlo3(x) _dsp_mtlo(x, 3) 1539 #define mtlo3(x) _dsp_mtlo(x, 3)
1369 1540
1370 #define mthi0(x) _dsp_mthi(x, 0) 1541 #define mthi0(x) _dsp_mthi(x, 0)
1371 #define mthi1(x) _dsp_mthi(x, 1) 1542 #define mthi1(x) _dsp_mthi(x, 1)
1372 #define mthi2(x) _dsp_mthi(x, 2) 1543 #define mthi2(x) _dsp_mthi(x, 2)
1373 #define mthi3(x) _dsp_mthi(x, 3) 1544 #define mthi3(x) _dsp_mthi(x, 3)
1374 1545
1375 #endif /* CONFIG_CPU_MICROMIPS */ 1546 #endif /* CONFIG_CPU_MICROMIPS */
1376 #endif 1547 #endif
1377 1548
1378 /* 1549 /*
1379 * TLB operations. 1550 * TLB operations.
1380 * 1551 *
1381 * It is responsibility of the caller to take care of any TLB hazards. 1552 * It is responsibility of the caller to take care of any TLB hazards.
1382 */ 1553 */
1383 static inline void tlb_probe(void) 1554 static inline void tlb_probe(void)
1384 { 1555 {
1385 __asm__ __volatile__( 1556 __asm__ __volatile__(
1386 ".set noreorder\n\t" 1557 ".set noreorder\n\t"
1387 "tlbp\n\t" 1558 "tlbp\n\t"
1388 ".set reorder"); 1559 ".set reorder");
1389 } 1560 }
1390 1561
1391 static inline void tlb_read(void) 1562 static inline void tlb_read(void)
1392 { 1563 {
1393 #if MIPS34K_MISSED_ITLB_WAR 1564 #if MIPS34K_MISSED_ITLB_WAR
1394 int res = 0; 1565 int res = 0;
1395 1566
1396 __asm__ __volatile__( 1567 __asm__ __volatile__(
1397 " .set push \n" 1568 " .set push \n"
1398 " .set noreorder \n" 1569 " .set noreorder \n"
1399 " .set noat \n" 1570 " .set noat \n"
1400 " .set mips32r2 \n" 1571 " .set mips32r2 \n"
1401 " .word 0x41610001 # dvpe $1 \n" 1572 " .word 0x41610001 # dvpe $1 \n"
1402 " move %0, $1 \n" 1573 " move %0, $1 \n"
1403 " ehb \n" 1574 " ehb \n"
1404 " .set pop \n" 1575 " .set pop \n"
1405 : "=r" (res)); 1576 : "=r" (res));
1406 1577
1407 instruction_hazard(); 1578 instruction_hazard();
1408 #endif 1579 #endif
1409 1580
1410 __asm__ __volatile__( 1581 __asm__ __volatile__(
1411 ".set noreorder\n\t" 1582 ".set noreorder\n\t"
1412 "tlbr\n\t" 1583 "tlbr\n\t"
1413 ".set reorder"); 1584 ".set reorder");
1414 1585
1415 #if MIPS34K_MISSED_ITLB_WAR 1586 #if MIPS34K_MISSED_ITLB_WAR
1416 if ((res & _ULCAST_(1))) 1587 if ((res & _ULCAST_(1)))
1417 __asm__ __volatile__( 1588 __asm__ __volatile__(
1418 " .set push \n" 1589 " .set push \n"
1419 " .set noreorder \n" 1590 " .set noreorder \n"
1420 " .set noat \n" 1591 " .set noat \n"
1421 " .set mips32r2 \n" 1592 " .set mips32r2 \n"
1422 " .word 0x41600021 # evpe \n" 1593 " .word 0x41600021 # evpe \n"
1423 " ehb \n" 1594 " ehb \n"
1424 " .set pop \n"); 1595 " .set pop \n");
1425 #endif 1596 #endif
1426 } 1597 }
1427 1598
1428 static inline void tlb_write_indexed(void) 1599 static inline void tlb_write_indexed(void)
1429 { 1600 {
1430 __asm__ __volatile__( 1601 __asm__ __volatile__(
1431 ".set noreorder\n\t" 1602 ".set noreorder\n\t"
1432 "tlbwi\n\t" 1603 "tlbwi\n\t"
1433 ".set reorder"); 1604 ".set reorder");
1434 } 1605 }
1435 1606
1436 static inline void tlb_write_random(void) 1607 static inline void tlb_write_random(void)
1437 { 1608 {
1438 __asm__ __volatile__( 1609 __asm__ __volatile__(
1439 ".set noreorder\n\t" 1610 ".set noreorder\n\t"
1440 "tlbwr\n\t" 1611 "tlbwr\n\t"
1441 ".set reorder"); 1612 ".set reorder");
1442 } 1613 }
1443 1614
1444 /* 1615 /*
1445 * Manipulate bits in a c0 register. 1616 * Manipulate bits in a c0 register.
1446 */ 1617 */
1447 #ifndef CONFIG_MIPS_MT_SMTC 1618 #ifndef CONFIG_MIPS_MT_SMTC
1448 /* 1619 /*
1449 * SMTC Linux requires shutting-down microthread scheduling 1620 * SMTC Linux requires shutting-down microthread scheduling
1450 * during CP0 register read-modify-write sequences. 1621 * during CP0 register read-modify-write sequences.
1451 */ 1622 */
1452 #define __BUILD_SET_C0(name) \ 1623 #define __BUILD_SET_C0(name) \
1453 static inline unsigned int \ 1624 static inline unsigned int \
1454 set_c0_##name(unsigned int set) \ 1625 set_c0_##name(unsigned int set) \
1455 { \ 1626 { \
1456 unsigned int res, new; \ 1627 unsigned int res, new; \
1457 \ 1628 \
1458 res = read_c0_##name(); \ 1629 res = read_c0_##name(); \
1459 new = res | set; \ 1630 new = res | set; \
1460 write_c0_##name(new); \ 1631 write_c0_##name(new); \
1461 \ 1632 \
1462 return res; \ 1633 return res; \
1463 } \ 1634 } \
1464 \ 1635 \
1465 static inline unsigned int \ 1636 static inline unsigned int \
1466 clear_c0_##name(unsigned int clear) \ 1637 clear_c0_##name(unsigned int clear) \
1467 { \ 1638 { \
1468 unsigned int res, new; \ 1639 unsigned int res, new; \
1469 \ 1640 \
1470 res = read_c0_##name(); \ 1641 res = read_c0_##name(); \
1471 new = res & ~clear; \ 1642 new = res & ~clear; \
1472 write_c0_##name(new); \ 1643 write_c0_##name(new); \
1473 \ 1644 \
1474 return res; \ 1645 return res; \
1475 } \ 1646 } \
1476 \ 1647 \
1477 static inline unsigned int \ 1648 static inline unsigned int \
1478 change_c0_##name(unsigned int change, unsigned int val) \ 1649 change_c0_##name(unsigned int change, unsigned int val) \
1479 { \ 1650 { \
1480 unsigned int res, new; \ 1651 unsigned int res, new; \
1481 \ 1652 \
1482 res = read_c0_##name(); \ 1653 res = read_c0_##name(); \
1483 new = res & ~change; \ 1654 new = res & ~change; \
1484 new |= (val & change); \ 1655 new |= (val & change); \
1485 write_c0_##name(new); \ 1656 write_c0_##name(new); \
1486 \ 1657 \
1487 return res; \ 1658 return res; \
1488 } 1659 }
1489 1660
1490 #else /* SMTC versions that manage MT scheduling */ 1661 #else /* SMTC versions that manage MT scheduling */
1491 1662
1492 #include <linux/irqflags.h> 1663 #include <linux/irqflags.h>
1493 1664
1494 /* 1665 /*
1495 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with 1666 * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
1496 * header file recursion. 1667 * header file recursion.
1497 */ 1668 */
1498 static inline unsigned int __dmt(void) 1669 static inline unsigned int __dmt(void)
1499 { 1670 {
1500 int res; 1671 int res;
1501 1672
1502 __asm__ __volatile__( 1673 __asm__ __volatile__(
1503 " .set push \n" 1674 " .set push \n"
1504 " .set mips32r2 \n" 1675 " .set mips32r2 \n"
1505 " .set noat \n" 1676 " .set noat \n"
1506 " .word 0x41610BC1 # dmt $1 \n" 1677 " .word 0x41610BC1 # dmt $1 \n"
1507 " ehb \n" 1678 " ehb \n"
1508 " move %0, $1 \n" 1679 " move %0, $1 \n"
1509 " .set pop \n" 1680 " .set pop \n"
1510 : "=r" (res)); 1681 : "=r" (res));
1511 1682
1512 instruction_hazard(); 1683 instruction_hazard();
1513 1684
1514 return res; 1685 return res;
1515 } 1686 }
1516 1687
1517 #define __VPECONTROL_TE_SHIFT 15 1688 #define __VPECONTROL_TE_SHIFT 15
1518 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT) 1689 #define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT)
1519 1690
1520 #define __EMT_ENABLE __VPECONTROL_TE 1691 #define __EMT_ENABLE __VPECONTROL_TE
1521 1692
1522 static inline void __emt(unsigned int previous) 1693 static inline void __emt(unsigned int previous)
1523 { 1694 {
1524 if ((previous & __EMT_ENABLE)) 1695 if ((previous & __EMT_ENABLE))
1525 __asm__ __volatile__( 1696 __asm__ __volatile__(
1526 " .set mips32r2 \n" 1697 " .set mips32r2 \n"
1527 " .word 0x41600be1 # emt \n" 1698 " .word 0x41600be1 # emt \n"
1528 " ehb \n" 1699 " ehb \n"
1529 " .set mips0 \n"); 1700 " .set mips0 \n");
1530 } 1701 }
1531 1702
1532 static inline void __ehb(void) 1703 static inline void __ehb(void)
1533 { 1704 {
1534 __asm__ __volatile__( 1705 __asm__ __volatile__(
1535 " .set mips32r2 \n" 1706 " .set mips32r2 \n"
1536 " ehb \n" " .set mips0 \n"); 1707 " ehb \n" " .set mips0 \n");
1537 } 1708 }
1538 1709
1539 /* 1710 /*
1540 * Note that local_irq_save/restore affect TC-specific IXMT state, 1711 * Note that local_irq_save/restore affect TC-specific IXMT state,
1541 * not Status.IE as in non-SMTC kernel. 1712 * not Status.IE as in non-SMTC kernel.
1542 */ 1713 */
1543 1714
1544 #define __BUILD_SET_C0(name) \ 1715 #define __BUILD_SET_C0(name) \
1545 static inline unsigned int \ 1716 static inline unsigned int \
1546 set_c0_##name(unsigned int set) \ 1717 set_c0_##name(unsigned int set) \
1547 { \ 1718 { \
1548 unsigned int res; \ 1719 unsigned int res; \
1549 unsigned int new; \ 1720 unsigned int new; \
1550 unsigned int omt; \ 1721 unsigned int omt; \
1551 unsigned long flags; \ 1722 unsigned long flags; \
1552 \ 1723 \
1553 local_irq_save(flags); \ 1724 local_irq_save(flags); \
1554 omt = __dmt(); \ 1725 omt = __dmt(); \
1555 res = read_c0_##name(); \ 1726 res = read_c0_##name(); \
1556 new = res | set; \ 1727 new = res | set; \
1557 write_c0_##name(new); \ 1728 write_c0_##name(new); \
1558 __emt(omt); \ 1729 __emt(omt); \
1559 local_irq_restore(flags); \ 1730 local_irq_restore(flags); \
1560 \ 1731 \
1561 return res; \ 1732 return res; \
1562 } \ 1733 } \
1563 \ 1734 \
1564 static inline unsigned int \ 1735 static inline unsigned int \
1565 clear_c0_##name(unsigned int clear) \ 1736 clear_c0_##name(unsigned int clear) \
1566 { \ 1737 { \
1567 unsigned int res; \ 1738 unsigned int res; \
1568 unsigned int new; \ 1739 unsigned int new; \
1569 unsigned int omt; \ 1740 unsigned int omt; \
1570 unsigned long flags; \ 1741 unsigned long flags; \
1571 \ 1742 \
1572 local_irq_save(flags); \ 1743 local_irq_save(flags); \
1573 omt = __dmt(); \ 1744 omt = __dmt(); \
1574 res = read_c0_##name(); \ 1745 res = read_c0_##name(); \
1575 new = res & ~clear; \ 1746 new = res & ~clear; \
1576 write_c0_##name(new); \ 1747 write_c0_##name(new); \
1577 __emt(omt); \ 1748 __emt(omt); \
1578 local_irq_restore(flags); \ 1749 local_irq_restore(flags); \
1579 \ 1750 \
1580 return res; \ 1751 return res; \
1581 } \ 1752 } \
1582 \ 1753 \
1583 static inline unsigned int \ 1754 static inline unsigned int \
1584 change_c0_##name(unsigned int change, unsigned int newbits) \ 1755 change_c0_##name(unsigned int change, unsigned int newbits) \
1585 { \ 1756 { \
1586 unsigned int res; \ 1757 unsigned int res; \
1587 unsigned int new; \ 1758 unsigned int new; \
1588 unsigned int omt; \ 1759 unsigned int omt; \
1589 unsigned long flags; \ 1760 unsigned long flags; \
1590 \ 1761 \
1591 local_irq_save(flags); \ 1762 local_irq_save(flags); \
1592 \ 1763 \
1593 omt = __dmt(); \ 1764 omt = __dmt(); \
1594 res = read_c0_##name(); \ 1765 res = read_c0_##name(); \
1595 new = res & ~change; \ 1766 new = res & ~change; \
1596 new |= (newbits & change); \ 1767 new |= (newbits & change); \
1597 write_c0_##name(new); \ 1768 write_c0_##name(new); \
1598 __emt(omt); \ 1769 __emt(omt); \
1599 local_irq_restore(flags); \ 1770 local_irq_restore(flags); \
1600 \ 1771 \
1601 return res; \ 1772 return res; \
1602 } 1773 }
1603 #endif 1774 #endif
1604 1775
1605 __BUILD_SET_C0(status) 1776 __BUILD_SET_C0(status)
1606 __BUILD_SET_C0(cause) 1777 __BUILD_SET_C0(cause)
1607 __BUILD_SET_C0(config) 1778 __BUILD_SET_C0(config)
1608 __BUILD_SET_C0(intcontrol) 1779 __BUILD_SET_C0(intcontrol)
1609 __BUILD_SET_C0(intctl) 1780 __BUILD_SET_C0(intctl)
1610 __BUILD_SET_C0(srsmap) 1781 __BUILD_SET_C0(srsmap)
1611 __BUILD_SET_C0(brcm_config_0) 1782 __BUILD_SET_C0(brcm_config_0)
1612 __BUILD_SET_C0(brcm_bus_pll) 1783 __BUILD_SET_C0(brcm_bus_pll)
1613 __BUILD_SET_C0(brcm_reset) 1784 __BUILD_SET_C0(brcm_reset)
1614 __BUILD_SET_C0(brcm_cmt_intr) 1785 __BUILD_SET_C0(brcm_cmt_intr)
1615 __BUILD_SET_C0(brcm_cmt_ctrl) 1786 __BUILD_SET_C0(brcm_cmt_ctrl)
1616 __BUILD_SET_C0(brcm_config) 1787 __BUILD_SET_C0(brcm_config)
1617 __BUILD_SET_C0(brcm_mode) 1788 __BUILD_SET_C0(brcm_mode)
1618 1789
1619 #endif /* !__ASSEMBLY__ */ 1790 #endif /* !__ASSEMBLY__ */
1620 1791
1621 #endif /* _ASM_MIPSREGS_H */ 1792 #endif /* _ASM_MIPSREGS_H */
1622 1793
arch/mips/kernel/Makefile
Diff comments   View file @ 63c2b68
1 # 1 #
2 # Makefile for the Linux/MIPS kernel. 2 # Makefile for the Linux/MIPS kernel.
3 # 3 #
4 4
5 extra-y := head.o vmlinux.lds 5 extra-y := head.o vmlinux.lds
6 6
7 obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ 7 obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \
8 ptrace.o reset.o setup.o signal.o syscall.o \ 8 ptrace.o reset.o setup.o signal.o syscall.o \
9 time.o topology.o traps.o unaligned.o watch.o vdso.o 9 time.o topology.o traps.o unaligned.o watch.o vdso.o
10 10
11 ifdef CONFIG_FUNCTION_TRACER 11 ifdef CONFIG_FUNCTION_TRACER
12 CFLAGS_REMOVE_ftrace.o = -pg 12 CFLAGS_REMOVE_ftrace.o = -pg
13 CFLAGS_REMOVE_early_printk.o = -pg 13 CFLAGS_REMOVE_early_printk.o = -pg
14 CFLAGS_REMOVE_perf_event.o = -pg 14 CFLAGS_REMOVE_perf_event.o = -pg
15 CFLAGS_REMOVE_perf_event_mipsxx.o = -pg 15 CFLAGS_REMOVE_perf_event_mipsxx.o = -pg
16 endif 16 endif
17 17
18 obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o 18 obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o
19 obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o 19 obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o
20 obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o 20 obj-$(CONFIG_MIPS_MT_SMTC) += cevt-smtc.o
21 obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o 21 obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o
22 obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o 22 obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o
23 obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o 23 obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o
24 obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o 24 obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o
25 obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o 25 obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o
26 obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o 26 obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o
27 obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o 27 obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o
28 obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o 28 obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o
29 obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o 29 obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o
30 obj-$(CONFIG_CSRC_GIC) += csrc-gic.o 30 obj-$(CONFIG_CSRC_GIC) += csrc-gic.o
31 obj-$(CONFIG_SYNC_R4K) += sync-r4k.o 31 obj-$(CONFIG_SYNC_R4K) += sync-r4k.o
32 32
33 obj-$(CONFIG_STACKTRACE) += stacktrace.o 33 obj-$(CONFIG_STACKTRACE) += stacktrace.o
34 obj-$(CONFIG_MODULES) += mips_ksyms.o module.o 34 obj-$(CONFIG_MODULES) += mips_ksyms.o module.o
35 obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o 35 obj-$(CONFIG_MODULES_USE_ELF_RELA) += module-rela.o
36 36
37 obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o 37 obj-$(CONFIG_FUNCTION_TRACER) += mcount.o ftrace.o
38 38
39 obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o 39 obj-$(CONFIG_CPU_R4K_FPU) += r4k_fpu.o r4k_switch.o
40 obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o 40 obj-$(CONFIG_CPU_R3000) += r2300_fpu.o r2300_switch.o
41 obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o 41 obj-$(CONFIG_CPU_R6000) += r6000_fpu.o r4k_switch.o
42 obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o 42 obj-$(CONFIG_CPU_TX39XX) += r2300_fpu.o r2300_switch.o
43 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o 43 obj-$(CONFIG_CPU_CAVIUM_OCTEON) += octeon_switch.o
44 44
45 obj-$(CONFIG_SMP) += smp.o 45 obj-$(CONFIG_SMP) += smp.o
46 obj-$(CONFIG_SMP_UP) += smp-up.o 46 obj-$(CONFIG_SMP_UP) += smp-up.o
47 obj-$(CONFIG_CPU_BMIPS) += smp-bmips.o bmips_vec.o 47 obj-$(CONFIG_CPU_BMIPS) += smp-bmips.o bmips_vec.o
48 48
49 obj-$(CONFIG_MIPS_MT) += mips-mt.o 49 obj-$(CONFIG_MIPS_MT) += mips-mt.o
50 obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o 50 obj-$(CONFIG_MIPS_MT_FPAFF) += mips-mt-fpaff.o
51 obj-$(CONFIG_MIPS_MT_SMTC) += smtc.o smtc-asm.o smtc-proc.o 51 obj-$(CONFIG_MIPS_MT_SMTC) += smtc.o smtc-asm.o smtc-proc.o
52 obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o 52 obj-$(CONFIG_MIPS_MT_SMP) += smp-mt.o
53 obj-$(CONFIG_MIPS_CMP) += smp-cmp.o 53 obj-$(CONFIG_MIPS_CMP) += smp-cmp.o
54 obj-$(CONFIG_CPU_MIPSR2) += spram.o 54 obj-$(CONFIG_CPU_MIPSR2) += spram.o
55 55
56 obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o 56 obj-$(CONFIG_MIPS_VPE_LOADER) += vpe.o
57 obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o 57 obj-$(CONFIG_MIPS_VPE_APSP_API) += rtlx.o
58 58
59 obj-$(CONFIG_I8259) += i8259.o 59 obj-$(CONFIG_I8259) += i8259.o
60 obj-$(CONFIG_IRQ_CPU) += irq_cpu.o 60 obj-$(CONFIG_IRQ_CPU) += irq_cpu.o
61 obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o 61 obj-$(CONFIG_IRQ_CPU_RM7K) += irq-rm7000.o
62 obj-$(CONFIG_MIPS_MSC) += irq-msc01.o 62 obj-$(CONFIG_MIPS_MSC) += irq-msc01.o
63 obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o 63 obj-$(CONFIG_IRQ_TXX9) += irq_txx9.o
64 obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o 64 obj-$(CONFIG_IRQ_GT641XX) += irq-gt641xx.o
65 obj-$(CONFIG_IRQ_GIC) += irq-gic.o 65 obj-$(CONFIG_IRQ_GIC) += irq-gic.o
66 66
67 obj-$(CONFIG_KPROBES) += kprobes.o 67 obj-$(CONFIG_KPROBES) += kprobes.o
68 obj-$(CONFIG_32BIT) += scall32-o32.o 68 obj-$(CONFIG_32BIT) += scall32-o32.o
69 obj-$(CONFIG_64BIT) += scall64-64.o 69 obj-$(CONFIG_64BIT) += scall64-64.o
70 obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o 70 obj-$(CONFIG_MIPS32_COMPAT) += linux32.o ptrace32.o signal32.o
71 obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o 71 obj-$(CONFIG_MIPS32_N32) += binfmt_elfn32.o scall64-n32.o signal_n32.o
72 obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o 72 obj-$(CONFIG_MIPS32_O32) += binfmt_elfo32.o scall64-o32.o
73 73
74 obj-$(CONFIG_KGDB) += kgdb.o 74 obj-$(CONFIG_KGDB) += kgdb.o
75 obj-$(CONFIG_PROC_FS) += proc.o 75 obj-$(CONFIG_PROC_FS) += proc.o
76 76
77 obj-$(CONFIG_64BIT) += cpu-bugs64.o 77 obj-$(CONFIG_64BIT) += cpu-bugs64.o
78 78
79 obj-$(CONFIG_I8253) += i8253.o 79 obj-$(CONFIG_I8253) += i8253.o
80 80
81 obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o 81 obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o
82 82
83 obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o crash.o 83 obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o crash.o
84 obj-$(CONFIG_CRASH_DUMP) += crash_dump.o 84 obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
85 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o 85 obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
86 obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o 86 obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o
87 obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o 87 obj-$(CONFIG_MIPS_MACHINE) += mips_machine.o
88 88
89 obj-$(CONFIG_OF) += prom.o 89 obj-$(CONFIG_OF) += prom.o
90 90
91 CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -x c /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) 91 CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -x c /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi)
92 92
93 obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o 93 obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT) += 8250-platform.o
94 94
95 obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/ 95 obj-$(CONFIG_MIPS_CPUFREQ) += cpufreq/
96 96
97 obj-$(CONFIG_PERF_EVENTS) += perf_event.o 97 obj-$(CONFIG_PERF_EVENTS) += perf_event.o
98 obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o 98 obj-$(CONFIG_HW_PERF_EVENTS) += perf_event_mipsxx.o
99 99
100 obj-$(CONFIG_JUMP_LABEL) += jump_label.o 100 obj-$(CONFIG_JUMP_LABEL) += jump_label.o
101 101
102 # 102 #
103 # DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is safe 103 # DSP ASE supported for MIPS32 or MIPS64 Release 2 cores only. It is not
104 # to enable DSP assembler support here even if the MIPS Release 2 CPU we 104 # safe to unconditionnaly use the assembler -mdsp / -mdspr2 switches
105 # are targetting does not support DSP because all code-paths making use of 105 # here because the compiler may use DSP ASE instructions (such as lwx) in
106 # it properly check that the running CPU *actually does* support these 106 # code paths where we cannot check that the CPU we are running on supports it.
107 # instructions. 107 # Proper abstraction using HAVE_AS_DSP and macros is done in
108 # arch/mips/include/asm/mipsregs.h.
108 # 109 #
109 ifeq ($(CONFIG_CPU_MIPSR2), y) 110 ifeq ($(CONFIG_CPU_MIPSR2), y)
110 CFLAGS_DSP = -DHAVE_AS_DSP 111 CFLAGS_DSP = -DHAVE_AS_DSP
111
112 #
113 # Check if assembler supports DSP ASE
114 #
115 ifeq ($(call cc-option-yn,-mdsp), y)
116 CFLAGS_DSP += -mdsp
117 endif
118
119 #
120 # Check if assembler supports DSP ASE Rev2
121 #
122 ifeq ($(call cc-option-yn,-mdspr2), y)
123 CFLAGS_DSP += -mdspr2
124 endif
125 112
126 CFLAGS_signal.o = $(CFLAGS_DSP) 113 CFLAGS_signal.o = $(CFLAGS_DSP)
127 CFLAGS_signal32.o = $(CFLAGS_DSP) 114 CFLAGS_signal32.o = $(CFLAGS_DSP)
128 CFLAGS_process.o = $(CFLAGS_DSP) 115 CFLAGS_process.o = $(CFLAGS_DSP)
129 CFLAGS_branch.o = $(CFLAGS_DSP) 116 CFLAGS_branch.o = $(CFLAGS_DSP)
130 CFLAGS_ptrace.o = $(CFLAGS_DSP) 117 CFLAGS_ptrace.o = $(CFLAGS_DSP)
131 endif 118 endif
132 119
133 CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS) 120 CPPFLAGS_vmlinux.lds := $(KBUILD_CFLAGS)