Commit 6688a4dd20bf774d654203a0629d454447b80502
1 parent
4c5df493eb
Exists in
master
and in
6 other branches
drm/nvc0/gr: fixup the mmio list register writes for 0xc1
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Showing 1 changed file with 32 additions and 9 deletions Side-by-side Diff
drivers/gpu/drm/nouveau/nvc0_graph.c
| ... | ... | @@ -157,8 +157,8 @@ |
| 157 | 157 | struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR); |
| 158 | 158 | struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR]; |
| 159 | 159 | struct drm_device *dev = chan->dev; |
| 160 | + struct drm_nouveau_private *dev_priv = dev->dev_private; | |
| 160 | 161 | int i = 0, gpc, tp, ret; |
| 161 | - u32 magic; | |
| 162 | 162 | |
| 163 | 163 | ret = nouveau_gpuobj_new(dev, chan, 0x2000, 256, NVOBJ_FLAG_VM, |
| 164 | 164 | &grch->unk408004); |
| ... | ... | @@ -207,14 +207,37 @@ |
| 207 | 207 | nv_wo32(grch->mmio, i++ * 4, 0x0041880c); |
| 208 | 208 | nv_wo32(grch->mmio, i++ * 4, 0x80000018); |
| 209 | 209 | |
| 210 | - magic = 0x02180000; | |
| 211 | - nv_wo32(grch->mmio, i++ * 4, 0x00405830); | |
| 212 | - nv_wo32(grch->mmio, i++ * 4, magic); | |
| 213 | - for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
| 214 | - for (tp = 0; tp < priv->tp_nr[gpc]; tp++, magic += 0x0324) { | |
| 215 | - u32 reg = 0x504520 + (gpc * 0x8000) + (tp * 0x0800); | |
| 216 | - nv_wo32(grch->mmio, i++ * 4, reg); | |
| 217 | - nv_wo32(grch->mmio, i++ * 4, magic); | |
| 210 | + if (dev_priv->chipset != 0xc1) { | |
| 211 | + u32 magic = 0x02180000; | |
| 212 | + nv_wo32(grch->mmio, i++ * 4, 0x00405830); | |
| 213 | + nv_wo32(grch->mmio, i++ * 4, magic); | |
| 214 | + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
| 215 | + for (tp = 0; tp < priv->tp_nr[gpc]; tp++) { | |
| 216 | + u32 reg = TP_UNIT(gpc, tp, 0x520); | |
| 217 | + nv_wo32(grch->mmio, i++ * 4, reg); | |
| 218 | + nv_wo32(grch->mmio, i++ * 4, magic); | |
| 219 | + magic += 0x0324; | |
| 220 | + } | |
| 221 | + } | |
| 222 | + } else { | |
| 223 | + u32 magic = 0x02180000; | |
| 224 | + nv_wo32(grch->mmio, i++ * 4, 0x00405830); | |
| 225 | + nv_wo32(grch->mmio, i++ * 4, magic | 0x0000218); | |
| 226 | + nv_wo32(grch->mmio, i++ * 4, 0x004064c4); | |
| 227 | + nv_wo32(grch->mmio, i++ * 4, 0x0086ffff); | |
| 228 | + for (gpc = 0; gpc < priv->gpc_nr; gpc++) { | |
| 229 | + for (tp = 0; tp < priv->tp_nr[gpc]; tp++) { | |
| 230 | + u32 reg = TP_UNIT(gpc, tp, 0x520); | |
| 231 | + nv_wo32(grch->mmio, i++ * 4, reg); | |
| 232 | + nv_wo32(grch->mmio, i++ * 4, (1 << 28) | magic); | |
| 233 | + magic += 0x0324; | |
| 234 | + } | |
| 235 | + for (tp = 0; tp < priv->tp_nr[gpc]; tp++) { | |
| 236 | + u32 reg = TP_UNIT(gpc, tp, 0x544); | |
| 237 | + nv_wo32(grch->mmio, i++ * 4, reg); | |
| 238 | + nv_wo32(grch->mmio, i++ * 4, magic); | |
| 239 | + magic += 0x0324; | |
| 240 | + } | |
| 218 | 241 | } |
| 219 | 242 | } |
| 220 | 243 |