Commit 691269f0d918cd72454c254f97722f194c07b9a8

Authored by Jan Beulich
Committed by Ingo Molnar
1 parent cabb5bd7ff

x86: Adjust section placement in AMD northbridge related code

amd_nb_misc_ids[] can live in .rodata, and enable_pci_io_ecs()
can be moved into .cpuinit.text.

Signed-off-by: Jan Beulich <jbeulich@novell.com>
Cc: Hans Rosenfeld <hans.rosenfeld@amd.com>
Cc: Andreas Herrmann <Andreas.Herrmann3@amd.com>
Cc: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <4D525DDD0200007800030F07@vpn.id2.novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

Showing 3 changed files with 6 additions and 5 deletions Side-by-side Diff

arch/x86/include/asm/amd_nb.h
... ... @@ -9,7 +9,7 @@
9 9 u8 dev_limit;
10 10 };
11 11  
12   -extern struct pci_device_id amd_nb_misc_ids[];
  12 +extern const struct pci_device_id amd_nb_misc_ids[];
13 13 extern const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[];
14 14 struct bootnode;
15 15  
arch/x86/kernel/amd_nb.c
... ... @@ -12,7 +12,7 @@
12 12  
13 13 static u32 *flush_words;
14 14  
15   -struct pci_device_id amd_nb_misc_ids[] = {
  15 +const struct pci_device_id amd_nb_misc_ids[] = {
16 16 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
17 17 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
18 18 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_MISC) },
... ... @@ -36,7 +36,7 @@
36 36 EXPORT_SYMBOL(amd_northbridges);
37 37  
38 38 static struct pci_dev *next_northbridge(struct pci_dev *dev,
39   - struct pci_device_id *ids)
  39 + const struct pci_device_id *ids)
40 40 {
41 41 do {
42 42 dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
43 43  
... ... @@ -107,8 +107,9 @@
107 107 they're useless anyways */
108 108 int __init early_is_amd_nb(u32 device)
109 109 {
110   - struct pci_device_id *id;
  110 + const struct pci_device_id *id;
111 111 u32 vendor = device & 0xffff;
  112 +
112 113 device >>= 16;
113 114 for (id = amd_nb_misc_ids; id->vendor; id++)
114 115 if (vendor == id->vendor && device == id->device)
arch/x86/pci/amd_bus.c
... ... @@ -350,7 +350,7 @@
350 350  
351 351 #define ENABLE_CF8_EXT_CFG (1ULL << 46)
352 352  
353   -static void enable_pci_io_ecs(void *unused)
  353 +static void __cpuinit enable_pci_io_ecs(void *unused)
354 354 {
355 355 u64 reg;
356 356 rdmsrl(MSR_AMD64_NB_CFG, reg);