Commit 6ae8ec27868bfdbb815287bee8146acbefaee867
Committed by
John W. Linville
John W. Linville
1 parent
35cbcbc6f3
Exists in
master
and in
7 other branches
ssb: fix init regression of hostmode PCI core
Our workarounds seem to be clientmode PCI specific. Using SPROM workaround on SoC resulted in Oops: Data bus error, epc == 8017ed58, ra == 80225838 Oops[#1]: Cpu 0 $ 0 : 00000000 10008000 b8000000 00000001 $ 4 : 80293b5c 00000caa ffffffff 00000000 $ 8 : 0000000a 00000003 00000001 696d6d20 $12 : ffffffff 00000000 00000000 ffffffff $16 : 802d0140 b8004800 802c0000 00000000 $20 : 00000000 802c0000 00000000 802d04d4 $24 : 00000018 80151a00 $28 : 81816000 81817df8 8029bda0 80225838 Hi : 00000000 Lo : 00000000 epc : 8017ed58 ssb_ssb_read16+0x48/0x60 Not tainted ra : 80225838 ssb_pcicore_init+0x54/0x3b4 Reported-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Tested-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
Showing 1 changed file with 9 additions and 9 deletions Side-by-side Diff
drivers/ssb/driver_pcicore.c
| ... | ... | @@ -516,8 +516,17 @@ |
| 516 | 516 | |
| 517 | 517 | static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) |
| 518 | 518 | { |
| 519 | + ssb_pcicore_fix_sprom_core_index(pc); | |
| 520 | + | |
| 519 | 521 | /* Disable PCI interrupts. */ |
| 520 | 522 | ssb_write32(pc->dev, SSB_INTVEC, 0); |
| 523 | + | |
| 524 | + /* Additional PCIe always once-executed workarounds */ | |
| 525 | + if (pc->dev->id.coreid == SSB_DEV_PCIE) { | |
| 526 | + ssb_pcicore_serdes_workaround(pc); | |
| 527 | + /* TODO: ASPM */ | |
| 528 | + /* TODO: Clock Request Update */ | |
| 529 | + } | |
| 521 | 530 | } |
| 522 | 531 | |
| 523 | 532 | void ssb_pcicore_init(struct ssb_pcicore *pc) |
| ... | ... | @@ -529,8 +538,6 @@ |
| 529 | 538 | if (!ssb_device_is_enabled(dev)) |
| 530 | 539 | ssb_device_enable(dev, 0); |
| 531 | 540 | |
| 532 | - ssb_pcicore_fix_sprom_core_index(pc); | |
| 533 | - | |
| 534 | 541 | #ifdef CONFIG_SSB_PCICORE_HOSTMODE |
| 535 | 542 | pc->hostmode = pcicore_is_in_hostmode(pc); |
| 536 | 543 | if (pc->hostmode) |
| ... | ... | @@ -538,13 +545,6 @@ |
| 538 | 545 | #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ |
| 539 | 546 | if (!pc->hostmode) |
| 540 | 547 | ssb_pcicore_init_clientmode(pc); |
| 541 | - | |
| 542 | - /* Additional PCIe always once-executed workarounds */ | |
| 543 | - if (dev->id.coreid == SSB_DEV_PCIE) { | |
| 544 | - ssb_pcicore_serdes_workaround(pc); | |
| 545 | - /* TODO: ASPM */ | |
| 546 | - /* TODO: Clock Request Update */ | |
| 547 | - } | |
| 548 | 548 | } |
| 549 | 549 | |
| 550 | 550 | static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address) |