Commit 7173e59e6b5f9cbde3ece66ae664454edcac6382
Committed by
Simon Horman
1 parent
2437b27c3a
Exists in
smarc-imx_3.14.28_1.0.0_ga
and in
1 other branch
phy-rcar-usb: handle platform data
Set the USBPCTRL0 register from the passed platform data in rcar_usb_phy_init(); don't reset it to 0 in rcar_usb_phy_shutdown() anymore as that does not make sense. Also, don't allow the driver's probe to succeed when the platform data are not supplied with a device. The patch has been tested on the Marzen and BOCK-W boards. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Showing 1 changed file with 45 additions and 6 deletions Side-by-side Diff
drivers/usb/phy/phy-rcar-usb.c
1 | 1 | /* |
2 | 2 | * Renesas R-Car USB phy driver |
3 | 3 | * |
4 | - * Copyright (C) 2012 Renesas Solutions Corp. | |
4 | + * Copyright (C) 2012-2013 Renesas Solutions Corp. | |
5 | 5 | * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
6 | + * Copyright (C) 2013 Cogent Embedded, Inc. | |
6 | 7 | * |
7 | 8 | * This program is free software; you can redistribute it and/or modify |
8 | 9 | * it under the terms of the GNU General Public License version 2 as |
... | ... | @@ -15,6 +16,7 @@ |
15 | 16 | #include <linux/platform_device.h> |
16 | 17 | #include <linux/spinlock.h> |
17 | 18 | #include <linux/module.h> |
19 | +#include <linux/platform_data/usb-rcar-phy.h> | |
18 | 20 | |
19 | 21 | /* REGS block */ |
20 | 22 | #define USBPCTRL0 0x00 |
... | ... | @@ -24,6 +26,25 @@ |
24 | 26 | #define USBOH0 0x1C |
25 | 27 | #define USBCTL0 0x58 |
26 | 28 | |
29 | +/* USBPCTRL0 */ | |
30 | +#define OVC2 (1 << 10) /* Switches the OVC input pin for port 2: */ | |
31 | + /* 1: USB_OVC2, 0: OVC2 */ | |
32 | +#define OVC1_VBUS1 (1 << 9) /* Switches the OVC input pin for port 1: */ | |
33 | + /* 1: USB_OVC1, 0: OVC1/VBUS1 */ | |
34 | + /* Function mode: set to 0 */ | |
35 | +#define OVC0 (1 << 8) /* Switches the OVC input pin for port 0: */ | |
36 | + /* 1: USB_OVC0 pin, 0: OVC0 */ | |
37 | +#define OVC2_ACT (1 << 6) /* Host mode: OVC2 polarity: */ | |
38 | + /* 1: active-high, 0: active-low */ | |
39 | +#define PENC (1 << 4) /* Function mode: output level of PENC1 pin: */ | |
40 | + /* 1: high, 0: low */ | |
41 | +#define OVC0_ACT (1 << 3) /* Host mode: OVC0 polarity: */ | |
42 | + /* 1: active-high, 0: active-low */ | |
43 | +#define OVC1_ACT (1 << 1) /* Host mode: OVC1 polarity: */ | |
44 | + /* 1: active-high, 0: active-low */ | |
45 | + /* Function mode: be sure to set to 1 */ | |
46 | +#define PORT1 (1 << 0) /* Selects port 1 mode: */ | |
47 | + /* 1: function, 0: host */ | |
27 | 48 | /* USBPCTRL1 */ |
28 | 49 | #define PHY_RST (1 << 2) |
29 | 50 | #define PLL_ENB (1 << 1) |
30 | 51 | |
... | ... | @@ -55,7 +76,9 @@ |
55 | 76 | { |
56 | 77 | struct rcar_usb_phy_priv *priv = usb_phy_to_priv(phy); |
57 | 78 | struct device *dev = phy->dev; |
79 | + struct rcar_phy_platform_data *pdata = dev->platform_data; | |
58 | 80 | void __iomem *reg0 = priv->reg0; |
81 | + static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT }; | |
59 | 82 | int i; |
60 | 83 | u32 val; |
61 | 84 | unsigned long flags; |
... | ... | @@ -89,8 +112,21 @@ |
89 | 112 | /* (4) USB-PHY reset clear */ |
90 | 113 | iowrite32(PHY_ENB | PLL_ENB | PHY_RST, (reg0 + USBPCTRL1)); |
91 | 114 | |
92 | - /* set platform specific port settings */ | |
93 | - iowrite32(0x00000000, (reg0 + USBPCTRL0)); | |
115 | + /* Board specific port settings */ | |
116 | + val = 0; | |
117 | + if (pdata->port1_func) | |
118 | + val |= PORT1; | |
119 | + if (pdata->penc1) | |
120 | + val |= PENC; | |
121 | + for (i = 0; i < 3; i++) { | |
122 | + /* OVCn bits follow each other in the right order */ | |
123 | + if (pdata->ovc_pin[i].select_3_3v) | |
124 | + val |= OVC0 << i; | |
125 | + /* OVCn_ACT bits are spaced by irregular intervals */ | |
126 | + if (pdata->ovc_pin[i].active_high) | |
127 | + val |= ovcn_act[i]; | |
128 | + } | |
129 | + iowrite32(val, (reg0 + USBPCTRL0)); | |
94 | 130 | |
95 | 131 | /* |
96 | 132 | * Bus alignment settings |
97 | 133 | |
... | ... | @@ -117,10 +153,8 @@ |
117 | 153 | |
118 | 154 | spin_lock_irqsave(&priv->lock, flags); |
119 | 155 | |
120 | - if (priv->counter-- == 1) { /* last user */ | |
121 | - iowrite32(0x00000000, (reg0 + USBPCTRL0)); | |
156 | + if (priv->counter-- == 1) /* last user */ | |
122 | 157 | iowrite32(0x00000000, (reg0 + USBPCTRL1)); |
123 | - } | |
124 | 158 | |
125 | 159 | spin_unlock_irqrestore(&priv->lock, flags); |
126 | 160 | } |
... | ... | @@ -132,6 +166,11 @@ |
132 | 166 | struct device *dev = &pdev->dev; |
133 | 167 | void __iomem *reg0; |
134 | 168 | int ret; |
169 | + | |
170 | + if (!pdev->dev.platform_data) { | |
171 | + dev_err(dev, "No platform data\n"); | |
172 | + return -EINVAL; | |
173 | + } | |
135 | 174 | |
136 | 175 | res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
137 | 176 | if (!res0) { |