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Commit 72bcb2690927f04c0479cd0d83825f09f3bf4d4f

Authored by Chris Wilson
Committed by Eric Anholt
1 parent d5dd96cb28
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

drm/i915/suspend: Flush register writes before busy-waiting. 

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>

Showing 1 changed file with 18 additions and 9 deletions Side-by-side Diff

drivers/gpu/drm/i915/i915_suspend.c
Diff comments   View file @ 72bcb26
... ... @@ -395,16 +395,20 @@
395 395 if (dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) {
396 396 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A &
397 397 ~DPLL_VCO_ENABLE);
398   - DRM_UDELAY(150);
  398 + POSTING_READ(dpll_a_reg);
  399 + udelay(150);
399 400 }
400 401 I915_WRITE(fpa0_reg, dev_priv->saveFPA0);
401 402 I915_WRITE(fpa1_reg, dev_priv->saveFPA1);
402 403 /* Actually enable it */
403 404 I915_WRITE(dpll_a_reg, dev_priv->saveDPLL_A);
404   - DRM_UDELAY(150);
405   - if (IS_I965G(dev) && !IS_IRONLAKE(dev))
  405 + POSTING_READ(dpll_a_reg);
  406 + udelay(150);
  407 + if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
406 408 I915_WRITE(DPLL_A_MD, dev_priv->saveDPLL_A_MD);
407   - DRM_UDELAY(150);
  409 + POSTING_READ(DPLL_A_MD);
  410 + }
  411 + udelay(150);
408 412  
409 413 /* Restore mode */
410 414 I915_WRITE(HTOTAL_A, dev_priv->saveHTOTAL_A);
411 415  
412 416  
... ... @@ -460,16 +464,20 @@
460 464 if (dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) {
461 465 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B &
462 466 ~DPLL_VCO_ENABLE);
463   - DRM_UDELAY(150);
  467 + POSTING_READ(dpll_b_reg);
  468 + udelay(150);
464 469 }
465 470 I915_WRITE(fpb0_reg, dev_priv->saveFPB0);
466 471 I915_WRITE(fpb1_reg, dev_priv->saveFPB1);
467 472 /* Actually enable it */
468 473 I915_WRITE(dpll_b_reg, dev_priv->saveDPLL_B);
469   - DRM_UDELAY(150);
470   - if (IS_I965G(dev) && !IS_IRONLAKE(dev))
  474 + POSTING_READ(dpll_b_reg);
  475 + udelay(150);
  476 + if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
471 477 I915_WRITE(DPLL_B_MD, dev_priv->saveDPLL_B_MD);
472   - DRM_UDELAY(150);
  478 + POSTING_READ(DPLL_B_MD);
  479 + }
  480 + udelay(150);
473 481  
474 482 /* Restore mode */
475 483 I915_WRITE(HTOTAL_B, dev_priv->saveHTOTAL_B);
... ... @@ -730,7 +738,8 @@
730 738 I915_WRITE(VGA0, dev_priv->saveVGA0);
731 739 I915_WRITE(VGA1, dev_priv->saveVGA1);
732 740 I915_WRITE(VGA_PD, dev_priv->saveVGA_PD);
733   - DRM_UDELAY(150);
  741 + POSTING_READ(VGA_PD);
  742 + udelay(150);
734 743  
735 744 i915_restore_vga(dev);
736 745 }