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Commit 73feb5c09dcf0d64beb67aa5e1f79e11a388e0ff

Authored by Michael Hennerich
Committed by Bryan Wu
1 parent c97618d3b7
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

Blackfin arch: fix bugs and unify BFIN_KERNEL_CLOCK option 

- remove duplicated code and headers
 - add option allowing arbitrary SDRAM/DDR Timing parameters.
 - mark automatically calculated timings as EXPERIMENTAL
 - fix comment header block

Related to BUGs:
 - kernel boot up fails with CONFIG_BFIN_KERNEL_CLOCK item on.
 - kernel does not boot if re-program clocks

[ Mike Frysinger <vapier.adi@gmail.com>
 - fix comment header
 - mark do_sync static
 - document the DMA shutdown
 - simplify SIC_IWR handling
 - fix ANOMALY_05000265 handling to work as intended ]

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>

Showing 27 changed files with 515 additions and 3097 deletions Side-by-side Diff

arch/blackfin/Kconfig
Diff comments   View file @ 73feb5c
... ... @@ -473,6 +473,61 @@
473 473 bool "MT46V32M16_5B"
474 474 endchoice
475 475  
  476 +choice
  477 + prompt "DDR/SDRAM Timing"
  478 + depends on BFIN_KERNEL_CLOCK
  479 + default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  480 + help
  481 + This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  482 + The calculated SDRAM timing parameters may not be 100%
  483 + accurate - This option is therefore marked experimental.
  484 +
  485 +config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  486 + bool "Calculate Timings (EXPERIMENTAL)"
  487 + depends on EXPERIMENTAL
  488 +
  489 +config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  490 + bool "Provide accurate Timings based on target SCLK"
  491 + help
  492 + Please consult the Blackfin Hardware Reference Manuals as well
  493 + as the memory device datasheet.
  494 + http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  495 +endchoice
  496 +
  497 +menu "Memory Init Control"
  498 + depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  499 +
  500 +config MEM_DDRCTL0
  501 + depends on BF54x
  502 + hex "DDRCTL0"
  503 + default 0x0
  504 +
  505 +config MEM_DDRCTL1
  506 + depends on BF54x
  507 + hex "DDRCTL1"
  508 + default 0x0
  509 +
  510 +config MEM_DDRCTL2
  511 + depends on BF54x
  512 + hex "DDRCTL2"
  513 + default 0x0
  514 +
  515 +config MEM_EBIU_DDRQUE
  516 + depends on BF54x
  517 + hex "DDRQUE"
  518 + default 0x0
  519 +
  520 +config MEM_SDRRC
  521 + depends on !BF54x
  522 + hex "SDRRC"
  523 + default 0x0
  524 +
  525 +config MEM_SDGCTL
  526 + depends on !BF54x
  527 + hex "SDGCTL"
  528 + default 0x0
  529 +endmenu
  530 +
476 531 config MAX_MEM_SIZE
477 532 int "Max SDRAM Memory Size in MBytes"
478 533 depends on !MPU
479 534  
... ... @@ -1104,13 +1159,13 @@
1104 1159  
1105 1160 config CPU_VOLTAGE
1106 1161 bool "CPU Voltage scaling"
1107   - depends on EXPERIMENTAL
  1162 + depends on EXPERIMENTAL
1108 1163 depends on CPU_FREQ
1109 1164 default n
1110 1165 help
1111 1166 Say Y here if you want CPU voltage scaling according to the CPU frequency.
1112 1167 This option violates the PLL BYPASS recommendation in the Blackfin Processor
1113   - manuals. There is a theoretical risk that during VDDINT transitions
  1168 + manuals. There is a theoretical risk that during VDDINT transitions
1114 1169 the PLL may unlock.
1115 1170  
1116 1171 endmenu
arch/blackfin/Makefile
Diff comments   View file @ 73feb5c
... ... @@ -91,7 +91,7 @@
91 91 CHECKFLAGS_SILICON = $(shell echo "" | $(CPP) $(KBUILD_CFLAGS) -dD - 2>/dev/null | awk '$$2 == "__SILICON_REVISION__" { print $$3 }')
92 92 CHECKFLAGS += -D__SILICON_REVISION__=$(CHECKFLAGS_SILICON) -Dl1_text=__used__
93 93  
94   -head-y := arch/$(ARCH)/mach-$(MACHINE)/head.o arch/$(ARCH)/kernel/init_task.o
  94 +head-y := arch/$(ARCH)/kernel/init_task.o
95 95  
96 96 core-y += arch/$(ARCH)/kernel/ arch/$(ARCH)/mm/ arch/$(ARCH)/mach-common/
97 97  
arch/blackfin/include/asm/mem_init.h
Diff comments   View file @ 73feb5c
  1 +/*
  2 + * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
  3 + *
  4 + * Copyright 2004-2008 Analog Devices Inc.
  5 + *
  6 + * Licensed under the GPL-2 or later.
  7 + */
  8 +
  9 +#if defined(EBIU_SDGCTL)
  10 +#if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
  11 + defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
  12 + defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
  13 + defined(CONFIG_MEM_GENERIC_BOARD) || \
  14 + defined(CONFIG_MEM_MT48LC32M8A2_75) || \
  15 + defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
  16 + defined(CONFIG_MEM_MT48LC32M16A2TG_75)
  17 +#if (CONFIG_SCLK_HZ > 119402985)
  18 +#define SDRAM_tRP TRP_2
  19 +#define SDRAM_tRP_num 2
  20 +#define SDRAM_tRAS TRAS_7
  21 +#define SDRAM_tRAS_num 7
  22 +#define SDRAM_tRCD TRCD_2
  23 +#define SDRAM_tWR TWR_2
  24 +#endif
  25 +#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
  26 +#define SDRAM_tRP TRP_2
  27 +#define SDRAM_tRP_num 2
  28 +#define SDRAM_tRAS TRAS_6
  29 +#define SDRAM_tRAS_num 6
  30 +#define SDRAM_tRCD TRCD_2
  31 +#define SDRAM_tWR TWR_2
  32 +#endif
  33 +#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
  34 +#define SDRAM_tRP TRP_2
  35 +#define SDRAM_tRP_num 2
  36 +#define SDRAM_tRAS TRAS_5
  37 +#define SDRAM_tRAS_num 5
  38 +#define SDRAM_tRCD TRCD_2
  39 +#define SDRAM_tWR TWR_2
  40 +#endif
  41 +#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
  42 +#define SDRAM_tRP TRP_2
  43 +#define SDRAM_tRP_num 2
  44 +#define SDRAM_tRAS TRAS_4
  45 +#define SDRAM_tRAS_num 4
  46 +#define SDRAM_tRCD TRCD_2
  47 +#define SDRAM_tWR TWR_2
  48 +#endif
  49 +#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
  50 +#define SDRAM_tRP TRP_2
  51 +#define SDRAM_tRP_num 2
  52 +#define SDRAM_tRAS TRAS_3
  53 +#define SDRAM_tRAS_num 3
  54 +#define SDRAM_tRCD TRCD_2
  55 +#define SDRAM_tWR TWR_2
  56 +#endif
  57 +#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
  58 +#define SDRAM_tRP TRP_1
  59 +#define SDRAM_tRP_num 1
  60 +#define SDRAM_tRAS TRAS_4
  61 +#define SDRAM_tRAS_num 3
  62 +#define SDRAM_tRCD TRCD_1
  63 +#define SDRAM_tWR TWR_2
  64 +#endif
  65 +#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
  66 +#define SDRAM_tRP TRP_1
  67 +#define SDRAM_tRP_num 1
  68 +#define SDRAM_tRAS TRAS_3
  69 +#define SDRAM_tRAS_num 3
  70 +#define SDRAM_tRCD TRCD_1
  71 +#define SDRAM_tWR TWR_2
  72 +#endif
  73 +#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
  74 +#define SDRAM_tRP TRP_1
  75 +#define SDRAM_tRP_num 1
  76 +#define SDRAM_tRAS TRAS_2
  77 +#define SDRAM_tRAS_num 2
  78 +#define SDRAM_tRCD TRCD_1
  79 +#define SDRAM_tWR TWR_2
  80 +#endif
  81 +#if (CONFIG_SCLK_HZ <= 29850746)
  82 +#define SDRAM_tRP TRP_1
  83 +#define SDRAM_tRP_num 1
  84 +#define SDRAM_tRAS TRAS_1
  85 +#define SDRAM_tRAS_num 1
  86 +#define SDRAM_tRCD TRCD_1
  87 +#define SDRAM_tWR TWR_2
  88 +#endif
  89 +#endif
  90 +
  91 +#if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
  92 + defined(CONFIG_MEM_MT48LC8M32B2B5_7)
  93 + /*SDRAM INFORMATION: */
  94 +#define SDRAM_Tref 64 /* Refresh period in milliseconds */
  95 +#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
  96 +#define SDRAM_CL CL_3
  97 +#endif
  98 +
  99 +#if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
  100 + defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
  101 + defined(CONFIG_MEM_GENERIC_BOARD) || \
  102 + defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
  103 + defined(CONFIG_MEM_MT48LC16M16A2TG_75)
  104 + /*SDRAM INFORMATION: */
  105 +#define SDRAM_Tref 64 /* Refresh period in milliseconds */
  106 +#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
  107 +#define SDRAM_CL CL_3
  108 +#endif
  109 +
  110 +
  111 +#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
  112 +/* Equation from section 17 (p17-46) of BF533 HRM */
  113 +#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
  114 +
  115 +/* Enable SCLK Out */
  116 +#define mem_SDGCTL (0x80000000 | SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
  117 +#else
  118 +#define mem_SDRRC CONFIG_MEM_SDRRC
  119 +#define mem_SDGCTL CONFIG_MEM_SDGCTL
  120 +#endif
  121 +#endif
  122 +
  123 +
  124 +#if defined(EBIU_DDRCTL0)
  125 +#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
  126 +#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
  127 +#define DDR_CLK_HZ(x) (1000*1000*1000/x)
  128 +
  129 +#if defined(CONFIG_MEM_MT46V32M16_6T)
  130 +#define DDR_SIZE DEVSZ_512
  131 +#define DDR_WIDTH DEVWD_16
  132 +#define DDR_MAX_tCK 13
  133 +
  134 +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
  135 +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
  136 +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
  137 +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
  138 +#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
  139 +
  140 +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
  141 +#define DDR_tWTR DDR_TWTR(1)
  142 +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
  143 +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
  144 +#endif
  145 +
  146 +#if defined(CONFIG_MEM_MT46V32M16_5B)
  147 +#define DDR_SIZE DEVSZ_512
  148 +#define DDR_WIDTH DEVWD_16
  149 +#define DDR_MAX_tCK 13
  150 +
  151 +#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
  152 +#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
  153 +#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
  154 +#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
  155 +#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
  156 +
  157 +#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
  158 +#define DDR_tWTR DDR_TWTR(2)
  159 +#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
  160 +#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
  161 +#endif
  162 +
  163 +#if defined(CONFIG_MEM_GENERIC_BOARD)
  164 +#define DDR_SIZE DEVSZ_512
  165 +#define DDR_WIDTH DEVWD_16
  166 +#define DDR_MAX_tCK 13
  167 +
  168 +#define DDR_tRCD DDR_TRCD(3)
  169 +#define DDR_tWTR DDR_TWTR(2)
  170 +#define DDR_tWR DDR_TWR(2)
  171 +#define DDR_tMRD DDR_TMRD(2)
  172 +#define DDR_tRP DDR_TRP(3)
  173 +#define DDR_tRAS DDR_TRAS(7)
  174 +#define DDR_tRC DDR_TRC(10)
  175 +#define DDR_tRFC DDR_TRFC(12)
  176 +#define DDR_tREFI DDR_TREFI(1288)
  177 +#endif
  178 +
  179 +#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
  180 +# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
  181 +#elif(CONFIG_SCLK_HZ <= 133333333)
  182 +# define DDR_CL CL_2
  183 +#else
  184 +# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
  185 +#endif
  186 +
  187 +#ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
  188 +#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
  189 +#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
  190 + | DDR_tMRD | DDR_tWR | DDR_tRCD)
  191 +#define mem_DDRCTL2 DDR_CL
  192 +#else
  193 +#define mem_DDRCTL0 CONFIG_MEM_DDRCTL0
  194 +#define mem_DDRCTL1 CONFIG_MEM_DDRCTL1
  195 +#define mem_DDRCTL2 CONFIG_MEM_DDRCTL2
  196 +#endif
  197 +#endif
  198 +
  199 +#if defined CONFIG_CLKIN_HALF
  200 +#define CLKIN_HALF 1
  201 +#else
  202 +#define CLKIN_HALF 0
  203 +#endif
  204 +
  205 +#if defined CONFIG_PLL_BYPASS
  206 +#define PLL_BYPASS 1
  207 +#else
  208 +#define PLL_BYPASS 0
  209 +#endif
  210 +
  211 +/***************************************Currently Not Being Used *********************************/
  212 +
  213 +#if defined(CONFIG_FLASH_SPEED_BWAT) && \
  214 +defined(CONFIG_FLASH_SPEED_BRAT) && \
  215 +defined(CONFIG_FLASH_SPEED_BHT) && \
  216 +defined(CONFIG_FLASH_SPEED_BST) && \
  217 +defined(CONFIG_FLASH_SPEED_BTT)
  218 +
  219 +#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
  220 +#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
  221 +#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
  222 +#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
  223 +#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
  224 +
  225 +#if (flash_EBIU_AMBCTL_TT > 3)
  226 +#define flash_EBIU_AMBCTL0_TT B0TT_4
  227 +#endif
  228 +#if (flash_EBIU_AMBCTL_TT == 3)
  229 +#define flash_EBIU_AMBCTL0_TT B0TT_3
  230 +#endif
  231 +#if (flash_EBIU_AMBCTL_TT == 2)
  232 +#define flash_EBIU_AMBCTL0_TT B0TT_2
  233 +#endif
  234 +#if (flash_EBIU_AMBCTL_TT < 2)
  235 +#define flash_EBIU_AMBCTL0_TT B0TT_1
  236 +#endif
  237 +
  238 +#if (flash_EBIU_AMBCTL_ST > 3)
  239 +#define flash_EBIU_AMBCTL0_ST B0ST_4
  240 +#endif
  241 +#if (flash_EBIU_AMBCTL_ST == 3)
  242 +#define flash_EBIU_AMBCTL0_ST B0ST_3
  243 +#endif
  244 +#if (flash_EBIU_AMBCTL_ST == 2)
  245 +#define flash_EBIU_AMBCTL0_ST B0ST_2
  246 +#endif
  247 +#if (flash_EBIU_AMBCTL_ST < 2)
  248 +#define flash_EBIU_AMBCTL0_ST B0ST_1
  249 +#endif
  250 +
  251 +#if (flash_EBIU_AMBCTL_HT > 2)
  252 +#define flash_EBIU_AMBCTL0_HT B0HT_3
  253 +#endif
  254 +#if (flash_EBIU_AMBCTL_HT == 2)
  255 +#define flash_EBIU_AMBCTL0_HT B0HT_2
  256 +#endif
  257 +#if (flash_EBIU_AMBCTL_HT == 1)
  258 +#define flash_EBIU_AMBCTL0_HT B0HT_1
  259 +#endif
  260 +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
  261 +#define flash_EBIU_AMBCTL0_HT B0HT_0
  262 +#endif
  263 +#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
  264 +#define flash_EBIU_AMBCTL0_HT B0HT_1
  265 +#endif
  266 +
  267 +#if (flash_EBIU_AMBCTL_WAT > 14)
  268 +#define flash_EBIU_AMBCTL0_WAT B0WAT_15
  269 +#endif
  270 +#if (flash_EBIU_AMBCTL_WAT == 14)
  271 +#define flash_EBIU_AMBCTL0_WAT B0WAT_14
  272 +#endif
  273 +#if (flash_EBIU_AMBCTL_WAT == 13)
  274 +#define flash_EBIU_AMBCTL0_WAT B0WAT_13
  275 +#endif
  276 +#if (flash_EBIU_AMBCTL_WAT == 12)
  277 +#define flash_EBIU_AMBCTL0_WAT B0WAT_12
  278 +#endif
  279 +#if (flash_EBIU_AMBCTL_WAT == 11)
  280 +#define flash_EBIU_AMBCTL0_WAT B0WAT_11
  281 +#endif
  282 +#if (flash_EBIU_AMBCTL_WAT == 10)
  283 +#define flash_EBIU_AMBCTL0_WAT B0WAT_10
  284 +#endif
  285 +#if (flash_EBIU_AMBCTL_WAT == 9)
  286 +#define flash_EBIU_AMBCTL0_WAT B0WAT_9
  287 +#endif
  288 +#if (flash_EBIU_AMBCTL_WAT == 8)
  289 +#define flash_EBIU_AMBCTL0_WAT B0WAT_8
  290 +#endif
  291 +#if (flash_EBIU_AMBCTL_WAT == 7)
  292 +#define flash_EBIU_AMBCTL0_WAT B0WAT_7
  293 +#endif
  294 +#if (flash_EBIU_AMBCTL_WAT == 6)
  295 +#define flash_EBIU_AMBCTL0_WAT B0WAT_6
  296 +#endif
  297 +#if (flash_EBIU_AMBCTL_WAT == 5)
  298 +#define flash_EBIU_AMBCTL0_WAT B0WAT_5
  299 +#endif
  300 +#if (flash_EBIU_AMBCTL_WAT == 4)
  301 +#define flash_EBIU_AMBCTL0_WAT B0WAT_4
  302 +#endif
  303 +#if (flash_EBIU_AMBCTL_WAT == 3)
  304 +#define flash_EBIU_AMBCTL0_WAT B0WAT_3
  305 +#endif
  306 +#if (flash_EBIU_AMBCTL_WAT == 2)
  307 +#define flash_EBIU_AMBCTL0_WAT B0WAT_2
  308 +#endif
  309 +#if (flash_EBIU_AMBCTL_WAT == 1)
  310 +#define flash_EBIU_AMBCTL0_WAT B0WAT_1
  311 +#endif
  312 +
  313 +#if (flash_EBIU_AMBCTL_RAT > 14)
  314 +#define flash_EBIU_AMBCTL0_RAT B0RAT_15
  315 +#endif
  316 +#if (flash_EBIU_AMBCTL_RAT == 14)
  317 +#define flash_EBIU_AMBCTL0_RAT B0RAT_14
  318 +#endif
  319 +#if (flash_EBIU_AMBCTL_RAT == 13)
  320 +#define flash_EBIU_AMBCTL0_RAT B0RAT_13
  321 +#endif
  322 +#if (flash_EBIU_AMBCTL_RAT == 12)
  323 +#define flash_EBIU_AMBCTL0_RAT B0RAT_12
  324 +#endif
  325 +#if (flash_EBIU_AMBCTL_RAT == 11)
  326 +#define flash_EBIU_AMBCTL0_RAT B0RAT_11
  327 +#endif
  328 +#if (flash_EBIU_AMBCTL_RAT == 10)
  329 +#define flash_EBIU_AMBCTL0_RAT B0RAT_10
  330 +#endif
  331 +#if (flash_EBIU_AMBCTL_RAT == 9)
  332 +#define flash_EBIU_AMBCTL0_RAT B0RAT_9
  333 +#endif
  334 +#if (flash_EBIU_AMBCTL_RAT == 8)
  335 +#define flash_EBIU_AMBCTL0_RAT B0RAT_8
  336 +#endif
  337 +#if (flash_EBIU_AMBCTL_RAT == 7)
  338 +#define flash_EBIU_AMBCTL0_RAT B0RAT_7
  339 +#endif
  340 +#if (flash_EBIU_AMBCTL_RAT == 6)
  341 +#define flash_EBIU_AMBCTL0_RAT B0RAT_6
  342 +#endif
  343 +#if (flash_EBIU_AMBCTL_RAT == 5)
  344 +#define flash_EBIU_AMBCTL0_RAT B0RAT_5
  345 +#endif
  346 +#if (flash_EBIU_AMBCTL_RAT == 4)
  347 +#define flash_EBIU_AMBCTL0_RAT B0RAT_4
  348 +#endif
  349 +#if (flash_EBIU_AMBCTL_RAT == 3)
  350 +#define flash_EBIU_AMBCTL0_RAT B0RAT_3
  351 +#endif
  352 +#if (flash_EBIU_AMBCTL_RAT == 2)
  353 +#define flash_EBIU_AMBCTL0_RAT B0RAT_2
  354 +#endif
  355 +#if (flash_EBIU_AMBCTL_RAT == 1)
  356 +#define flash_EBIU_AMBCTL0_RAT B0RAT_1
  357 +#endif
  358 +
  359 +#define flash_EBIU_AMBCTL0 \
  360 + (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
  361 + flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
  362 +#endif
arch/blackfin/mach-bf518/Makefile
Diff comments   View file @ 73feb5c
... ... @@ -2,7 +2,5 @@
2 2 # arch/blackfin/mach-bf518/Makefile
3 3 #
4 4  
5   -extra-y := head.o
6   -
7 5 obj-y := ints-priority.o dma.o
arch/blackfin/mach-bf518/head.S
View file @ 73feb5c
1   -/*
2   - * File: arch/blackfin/mach-bf518/head.S
3   - * Based on: arch/blackfin/mach-bf527/head.S
4   - * Author: Bryan Wu <cooloney@kernel.org>
5   - *
6   - * Created: 2008
7   - * Description: Startup code for Blackfin BF51x
8   - *
9   - * Modified:
10   - * Copyright 2004-2008 Analog Devices Inc.
11   - *
12   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
13   - *
14   - * This program is free software; you can redistribute it and/or modify
15   - * it under the terms of the GNU General Public License as published by
16   - * the Free Software Foundation; either version 2 of the License, or
17   - * (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, see the file COPYING, or write
26   - * to the Free Software Foundation, Inc.,
27   - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28   - */
29   -
30   -#include <linux/linkage.h>
31   -#include <linux/init.h>
32   -#include <asm/blackfin.h>
33   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
34   -#include <asm/mach-common/clocks.h>
35   -#include <asm/mach/mem_init.h>
36   -#endif
37   -
38   -.section .l1.text
39   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
40   -ENTRY(_start_dma_code)
41   -
42   - /* Enable PHY CLK buffer output */
43   - p0.h = hi(VR_CTL);
44   - p0.l = lo(VR_CTL);
45   - r0.l = w[p0];
46   - bitset(r0, 14);
47   - w[p0] = r0.l;
48   - ssync;
49   -
50   - p0.h = hi(SIC_IWR0);
51   - p0.l = lo(SIC_IWR0);
52   - r0.l = 0x1;
53   - r0.h = 0x0;
54   - [p0] = r0;
55   - ssync;
56   -
57   - /*
58   - * Set PLL_CTL
59   - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
60   - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
61   - * - [7] = output delay (add 200ps of delay to mem signals)
62   - * - [6] = input delay (add 200ps of input delay to mem signals)
63   - * - [5] = PDWN : 1=All Clocks off
64   - * - [3] = STOPCK : 1=Core Clock off
65   - * - [1] = PLL_OFF : 1=Disable Power to PLL
66   - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
67   - * all other bits set to zero
68   - */
69   -
70   - p0.h = hi(PLL_LOCKCNT);
71   - p0.l = lo(PLL_LOCKCNT);
72   - r0 = 0x300(Z);
73   - w[p0] = r0.l;
74   - ssync;
75   -
76   - P2.H = hi(EBIU_SDGCTL);
77   - P2.L = lo(EBIU_SDGCTL);
78   - R0 = [P2];
79   - BITSET (R0, 24);
80   - [P2] = R0;
81   - ssync;
82   -
83   - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
84   - r0 = r0 << 9; /* Shift it over, */
85   - r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
86   - r0 = r1 | r0;
87   - r1 = PLL_BYPASS; /* Bypass the PLL? */
88   - r1 = r1 << 8; /* Shift it over */
89   - r0 = r1 | r0; /* add them all together */
90   -#ifdef ANOMALY_05000265
91   - BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
92   -#endif
93   -
94   - p0.h = hi(PLL_CTL);
95   - p0.l = lo(PLL_CTL); /* Load the address */
96   - cli r2; /* Disable interrupts */
97   - ssync;
98   - w[p0] = r0.l; /* Set the value */
99   - idle; /* Wait for the PLL to stablize */
100   - sti r2; /* Enable interrupts */
101   -
102   -.Lcheck_again:
103   - p0.h = hi(PLL_STAT);
104   - p0.l = lo(PLL_STAT);
105   - R0 = W[P0](Z);
106   - CC = BITTST(R0,5);
107   - if ! CC jump .Lcheck_again;
108   -
109   - /* Configure SCLK & CCLK Dividers */
110   - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
111   - p0.h = hi(PLL_DIV);
112   - p0.l = lo(PLL_DIV);
113   - w[p0] = r0.l;
114   - ssync;
115   -
116   - p0.l = lo(EBIU_SDRRC);
117   - p0.h = hi(EBIU_SDRRC);
118   - r0 = mem_SDRRC;
119   - w[p0] = r0.l;
120   - ssync;
121   -
122   - P2.H = hi(EBIU_SDGCTL);
123   - P2.L = lo(EBIU_SDGCTL);
124   - R0 = [P2];
125   - BITCLR (R0, 24);
126   - p0.h = hi(EBIU_SDSTAT);
127   - p0.l = lo(EBIU_SDSTAT);
128   - r2.l = w[p0];
129   - cc = bittst(r2,3);
130   - if !cc jump .Lskip;
131   - NOP;
132   - BITSET (R0, 23);
133   -.Lskip:
134   - [P2] = R0;
135   - SSYNC;
136   -
137   - R0.L = lo(mem_SDGCTL);
138   - R0.H = hi(mem_SDGCTL);
139   - R1 = [p2];
140   - R1 = R1 | R0;
141   - [P2] = R1;
142   - SSYNC;
143   -
144   - RTS;
145   -ENDPROC(_start_dma_code)
146   -#endif /* CONFIG_BFIN_KERNEL_CLOCK */
arch/blackfin/mach-bf518/include/mach/mem_init.h
View file @ 73feb5c
1   -/*
2   - * File: include/asm-blackfin/mach-bf518/mem_init.h
3   - * Based on:
4   - * Author:
5   - *
6   - * Created:
7   - * Description:
8   - *
9   - * Rev:
10   - *
11   - * Modified:
12   - * Copyright 2004-2007 Analog Devices Inc.
13   - *
14   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
15   - *
16   - * This program is free software; you can redistribute it and/or modify
17   - * it under the terms of the GNU General Public License as published by
18   - * the Free Software Foundation; either version 2, or (at your option)
19   - * any later version.
20   - *
21   - * This program is distributed in the hope that it will be useful,
22   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
23   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24   - * GNU General Public License for more details.
25   - *
26   - * You should have received a copy of the GNU General Public License
27   - * along with this program; see the file COPYING.
28   - * If not, write to the Free Software Foundation,
29   - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30   - */
31   -
32   -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
33   -#if (CONFIG_SCLK_HZ > 119402985)
34   -#define SDRAM_tRP TRP_2
35   -#define SDRAM_tRP_num 2
36   -#define SDRAM_tRAS TRAS_7
37   -#define SDRAM_tRAS_num 7
38   -#define SDRAM_tRCD TRCD_2
39   -#define SDRAM_tWR TWR_2
40   -#endif
41   -#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42   -#define SDRAM_tRP TRP_2
43   -#define SDRAM_tRP_num 2
44   -#define SDRAM_tRAS TRAS_6
45   -#define SDRAM_tRAS_num 6
46   -#define SDRAM_tRCD TRCD_2
47   -#define SDRAM_tWR TWR_2
48   -#endif
49   -#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50   -#define SDRAM_tRP TRP_2
51   -#define SDRAM_tRP_num 2
52   -#define SDRAM_tRAS TRAS_5
53   -#define SDRAM_tRAS_num 5
54   -#define SDRAM_tRCD TRCD_2
55   -#define SDRAM_tWR TWR_2
56   -#endif
57   -#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58   -#define SDRAM_tRP TRP_2
59   -#define SDRAM_tRP_num 2
60   -#define SDRAM_tRAS TRAS_4
61   -#define SDRAM_tRAS_num 4
62   -#define SDRAM_tRCD TRCD_2
63   -#define SDRAM_tWR TWR_2
64   -#endif
65   -#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66   -#define SDRAM_tRP TRP_2
67   -#define SDRAM_tRP_num 2
68   -#define SDRAM_tRAS TRAS_3
69   -#define SDRAM_tRAS_num 3
70   -#define SDRAM_tRCD TRCD_2
71   -#define SDRAM_tWR TWR_2
72   -#endif
73   -#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74   -#define SDRAM_tRP TRP_1
75   -#define SDRAM_tRP_num 1
76   -#define SDRAM_tRAS TRAS_4
77   -#define SDRAM_tRAS_num 3
78   -#define SDRAM_tRCD TRCD_1
79   -#define SDRAM_tWR TWR_2
80   -#endif
81   -#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82   -#define SDRAM_tRP TRP_1
83   -#define SDRAM_tRP_num 1
84   -#define SDRAM_tRAS TRAS_3
85   -#define SDRAM_tRAS_num 3
86   -#define SDRAM_tRCD TRCD_1
87   -#define SDRAM_tWR TWR_2
88   -#endif
89   -#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90   -#define SDRAM_tRP TRP_1
91   -#define SDRAM_tRP_num 1
92   -#define SDRAM_tRAS TRAS_2
93   -#define SDRAM_tRAS_num 2
94   -#define SDRAM_tRCD TRCD_1
95   -#define SDRAM_tWR TWR_2
96   -#endif
97   -#if (CONFIG_SCLK_HZ <= 29850746)
98   -#define SDRAM_tRP TRP_1
99   -#define SDRAM_tRP_num 1
100   -#define SDRAM_tRAS TRAS_1
101   -#define SDRAM_tRAS_num 1
102   -#define SDRAM_tRCD TRCD_1
103   -#define SDRAM_tWR TWR_2
104   -#endif
105   -#endif
106   -
107   -#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108   - /*SDRAM INFORMATION: */
109   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111   -#define SDRAM_CL CL_3
112   -#endif
113   -
114   -#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115   - /*SDRAM INFORMATION: */
116   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117   -#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118   -#define SDRAM_CL CL_3
119   -#endif
120   -
121   -#if (CONFIG_MEM_MT48LC32M8A2_75)
122   - /*SDRAM INFORMATION: */
123   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125   -#define SDRAM_CL CL_3
126   -#endif
127   -
128   -#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129   - /*SDRAM INFORMATION: */
130   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132   -#define SDRAM_CL CL_3
133   -#endif
134   -
135   -#if (CONFIG_MEM_GENERIC_BOARD)
136   - /*SDRAM INFORMATION: Modify this for your board */
137   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139   -#define SDRAM_CL CL_3
140   -#endif
141   -
142   -#if (CONFIG_MEM_MT48LC32M16A2TG_75)
143   - /*SDRAM INFORMATION: */
144   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
145   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
146   -#define SDRAM_CL CL_3
147   -#endif
148   -
149   -/* Equation from section 17 (p17-46) of BF533 HRM */
150   -#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
151   -
152   -/* Enable SCLK Out */
153   -#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
154   -
155   -#if defined CONFIG_CLKIN_HALF
156   -#define CLKIN_HALF 1
157   -#else
158   -#define CLKIN_HALF 0
159   -#endif
160   -
161   -#if defined CONFIG_PLL_BYPASS
162   -#define PLL_BYPASS 1
163   -#else
164   -#define PLL_BYPASS 0
165   -#endif
166   -
167   -/***************************************Currently Not Being Used *********************************/
168   -#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
169   -#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
170   -#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
171   -#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
172   -#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
173   -
174   -#if (flash_EBIU_AMBCTL_TT > 3)
175   -#define flash_EBIU_AMBCTL0_TT B0TT_4
176   -#endif
177   -#if (flash_EBIU_AMBCTL_TT == 3)
178   -#define flash_EBIU_AMBCTL0_TT B0TT_3
179   -#endif
180   -#if (flash_EBIU_AMBCTL_TT == 2)
181   -#define flash_EBIU_AMBCTL0_TT B0TT_2
182   -#endif
183   -#if (flash_EBIU_AMBCTL_TT < 2)
184   -#define flash_EBIU_AMBCTL0_TT B0TT_1
185   -#endif
186   -
187   -#if (flash_EBIU_AMBCTL_ST > 3)
188   -#define flash_EBIU_AMBCTL0_ST B0ST_4
189   -#endif
190   -#if (flash_EBIU_AMBCTL_ST == 3)
191   -#define flash_EBIU_AMBCTL0_ST B0ST_3
192   -#endif
193   -#if (flash_EBIU_AMBCTL_ST == 2)
194   -#define flash_EBIU_AMBCTL0_ST B0ST_2
195   -#endif
196   -#if (flash_EBIU_AMBCTL_ST < 2)
197   -#define flash_EBIU_AMBCTL0_ST B0ST_1
198   -#endif
199   -
200   -#if (flash_EBIU_AMBCTL_HT > 2)
201   -#define flash_EBIU_AMBCTL0_HT B0HT_3
202   -#endif
203   -#if (flash_EBIU_AMBCTL_HT == 2)
204   -#define flash_EBIU_AMBCTL0_HT B0HT_2
205   -#endif
206   -#if (flash_EBIU_AMBCTL_HT == 1)
207   -#define flash_EBIU_AMBCTL0_HT B0HT_1
208   -#endif
209   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
210   -#define flash_EBIU_AMBCTL0_HT B0HT_0
211   -#endif
212   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
213   -#define flash_EBIU_AMBCTL0_HT B0HT_1
214   -#endif
215   -
216   -#if (flash_EBIU_AMBCTL_WAT > 14)
217   -#define flash_EBIU_AMBCTL0_WAT B0WAT_15
218   -#endif
219   -#if (flash_EBIU_AMBCTL_WAT == 14)
220   -#define flash_EBIU_AMBCTL0_WAT B0WAT_14
221   -#endif
222   -#if (flash_EBIU_AMBCTL_WAT == 13)
223   -#define flash_EBIU_AMBCTL0_WAT B0WAT_13
224   -#endif
225   -#if (flash_EBIU_AMBCTL_WAT == 12)
226   -#define flash_EBIU_AMBCTL0_WAT B0WAT_12
227   -#endif
228   -#if (flash_EBIU_AMBCTL_WAT == 11)
229   -#define flash_EBIU_AMBCTL0_WAT B0WAT_11
230   -#endif
231   -#if (flash_EBIU_AMBCTL_WAT == 10)
232   -#define flash_EBIU_AMBCTL0_WAT B0WAT_10
233   -#endif
234   -#if (flash_EBIU_AMBCTL_WAT == 9)
235   -#define flash_EBIU_AMBCTL0_WAT B0WAT_9
236   -#endif
237   -#if (flash_EBIU_AMBCTL_WAT == 8)
238   -#define flash_EBIU_AMBCTL0_WAT B0WAT_8
239   -#endif
240   -#if (flash_EBIU_AMBCTL_WAT == 7)
241   -#define flash_EBIU_AMBCTL0_WAT B0WAT_7
242   -#endif
243   -#if (flash_EBIU_AMBCTL_WAT == 6)
244   -#define flash_EBIU_AMBCTL0_WAT B0WAT_6
245   -#endif
246   -#if (flash_EBIU_AMBCTL_WAT == 5)
247   -#define flash_EBIU_AMBCTL0_WAT B0WAT_5
248   -#endif
249   -#if (flash_EBIU_AMBCTL_WAT == 4)
250   -#define flash_EBIU_AMBCTL0_WAT B0WAT_4
251   -#endif
252   -#if (flash_EBIU_AMBCTL_WAT == 3)
253   -#define flash_EBIU_AMBCTL0_WAT B0WAT_3
254   -#endif
255   -#if (flash_EBIU_AMBCTL_WAT == 2)
256   -#define flash_EBIU_AMBCTL0_WAT B0WAT_2
257   -#endif
258   -#if (flash_EBIU_AMBCTL_WAT == 1)
259   -#define flash_EBIU_AMBCTL0_WAT B0WAT_1
260   -#endif
261   -
262   -#if (flash_EBIU_AMBCTL_RAT > 14)
263   -#define flash_EBIU_AMBCTL0_RAT B0RAT_15
264   -#endif
265   -#if (flash_EBIU_AMBCTL_RAT == 14)
266   -#define flash_EBIU_AMBCTL0_RAT B0RAT_14
267   -#endif
268   -#if (flash_EBIU_AMBCTL_RAT == 13)
269   -#define flash_EBIU_AMBCTL0_RAT B0RAT_13
270   -#endif
271   -#if (flash_EBIU_AMBCTL_RAT == 12)
272   -#define flash_EBIU_AMBCTL0_RAT B0RAT_12
273   -#endif
274   -#if (flash_EBIU_AMBCTL_RAT == 11)
275   -#define flash_EBIU_AMBCTL0_RAT B0RAT_11
276   -#endif
277   -#if (flash_EBIU_AMBCTL_RAT == 10)
278   -#define flash_EBIU_AMBCTL0_RAT B0RAT_10
279   -#endif
280   -#if (flash_EBIU_AMBCTL_RAT == 9)
281   -#define flash_EBIU_AMBCTL0_RAT B0RAT_9
282   -#endif
283   -#if (flash_EBIU_AMBCTL_RAT == 8)
284   -#define flash_EBIU_AMBCTL0_RAT B0RAT_8
285   -#endif
286   -#if (flash_EBIU_AMBCTL_RAT == 7)
287   -#define flash_EBIU_AMBCTL0_RAT B0RAT_7
288   -#endif
289   -#if (flash_EBIU_AMBCTL_RAT == 6)
290   -#define flash_EBIU_AMBCTL0_RAT B0RAT_6
291   -#endif
292   -#if (flash_EBIU_AMBCTL_RAT == 5)
293   -#define flash_EBIU_AMBCTL0_RAT B0RAT_5
294   -#endif
295   -#if (flash_EBIU_AMBCTL_RAT == 4)
296   -#define flash_EBIU_AMBCTL0_RAT B0RAT_4
297   -#endif
298   -#if (flash_EBIU_AMBCTL_RAT == 3)
299   -#define flash_EBIU_AMBCTL0_RAT B0RAT_3
300   -#endif
301   -#if (flash_EBIU_AMBCTL_RAT == 2)
302   -#define flash_EBIU_AMBCTL0_RAT B0RAT_2
303   -#endif
304   -#if (flash_EBIU_AMBCTL_RAT == 1)
305   -#define flash_EBIU_AMBCTL0_RAT B0RAT_1
306   -#endif
307   -
308   -#define flash_EBIU_AMBCTL0 \
309   - (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
310   - flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
arch/blackfin/mach-bf527/Makefile
Diff comments   View file @ 73feb5c
... ... @@ -2,7 +2,5 @@
2 2 # arch/blackfin/mach-bf527/Makefile
3 3 #
4 4  
5   -extra-y := head.o
6   -
7 5 obj-y := ints-priority.o dma.o
arch/blackfin/mach-bf527/head.S
View file @ 73feb5c
1   -/*
2   - * File: arch/blackfin/mach-bf527/head.S
3   - * Based on: arch/blackfin/mach-bf533/head.S
4   - * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5   - *
6   - * Created: 1998
7   - * Description: Startup code for Blackfin BF537
8   - *
9   - * Modified:
10   - * Copyright 2004-2007 Analog Devices Inc.
11   - *
12   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
13   - *
14   - * This program is free software; you can redistribute it and/or modify
15   - * it under the terms of the GNU General Public License as published by
16   - * the Free Software Foundation; either version 2 of the License, or
17   - * (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, see the file COPYING, or write
26   - * to the Free Software Foundation, Inc.,
27   - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28   - */
29   -
30   -#include <linux/linkage.h>
31   -#include <linux/init.h>
32   -#include <asm/blackfin.h>
33   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
34   -#include <asm/clocks.h>
35   -#include <mach/mem_init.h>
36   -#endif
37   -
38   -.section .l1.text
39   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
40   -ENTRY(_start_dma_code)
41   -
42   - /* Enable PHY CLK buffer output */
43   - p0.h = hi(VR_CTL);
44   - p0.l = lo(VR_CTL);
45   - r0.l = w[p0];
46   - bitset(r0, 14);
47   - w[p0] = r0.l;
48   - ssync;
49   -
50   - p0.h = hi(SIC_IWR0);
51   - p0.l = lo(SIC_IWR0);
52   - r0.l = 0x1;
53   - r0.h = 0x0;
54   - [p0] = r0;
55   - SSYNC;
56   -
57   - /*
58   - * Set PLL_CTL
59   - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
60   - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
61   - * - [7] = output delay (add 200ps of delay to mem signals)
62   - * - [6] = input delay (add 200ps of input delay to mem signals)
63   - * - [5] = PDWN : 1=All Clocks off
64   - * - [3] = STOPCK : 1=Core Clock off
65   - * - [1] = PLL_OFF : 1=Disable Power to PLL
66   - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
67   - * all other bits set to zero
68   - */
69   -
70   - p0.h = hi(PLL_LOCKCNT);
71   - p0.l = lo(PLL_LOCKCNT);
72   - r0 = 0x300(Z);
73   - w[p0] = r0.l;
74   - ssync;
75   -
76   - P2.H = hi(EBIU_SDGCTL);
77   - P2.L = lo(EBIU_SDGCTL);
78   - R0 = [P2];
79   - BITSET (R0, 24);
80   - [P2] = R0;
81   - SSYNC;
82   -
83   - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
84   - r0 = r0 << 9; /* Shift it over, */
85   - r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
86   - r0 = r1 | r0;
87   - r1 = PLL_BYPASS; /* Bypass the PLL? */
88   - r1 = r1 << 8; /* Shift it over */
89   - r0 = r1 | r0; /* add them all together */
90   -#ifdef ANOMALY_05000265
91   - BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
92   -#endif
93   -
94   - p0.h = hi(PLL_CTL);
95   - p0.l = lo(PLL_CTL); /* Load the address */
96   - cli r2; /* Disable interrupts */
97   - ssync;
98   - w[p0] = r0.l; /* Set the value */
99   - idle; /* Wait for the PLL to stablize */
100   - sti r2; /* Enable interrupts */
101   -
102   -.Lcheck_again:
103   - p0.h = hi(PLL_STAT);
104   - p0.l = lo(PLL_STAT);
105   - R0 = W[P0](Z);
106   - CC = BITTST(R0,5);
107   - if ! CC jump .Lcheck_again;
108   -
109   - /* Configure SCLK & CCLK Dividers */
110   - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
111   - p0.h = hi(PLL_DIV);
112   - p0.l = lo(PLL_DIV);
113   - w[p0] = r0.l;
114   - ssync;
115   -
116   - p0.l = lo(EBIU_SDRRC);
117   - p0.h = hi(EBIU_SDRRC);
118   - r0 = mem_SDRRC;
119   - w[p0] = r0.l;
120   - ssync;
121   -
122   - P2.H = hi(EBIU_SDGCTL);
123   - P2.L = lo(EBIU_SDGCTL);
124   - R0 = [P2];
125   - BITCLR (R0, 24);
126   - p0.h = hi(EBIU_SDSTAT);
127   - p0.l = lo(EBIU_SDSTAT);
128   - r2.l = w[p0];
129   - cc = bittst(r2,3);
130   - if !cc jump .Lskip;
131   - NOP;
132   - BITSET (R0, 23);
133   -.Lskip:
134   - [P2] = R0;
135   - SSYNC;
136   -
137   - R0.L = lo(mem_SDGCTL);
138   - R0.H = hi(mem_SDGCTL);
139   - R1 = [p2];
140   - R1 = R1 | R0;
141   - [P2] = R1;
142   - SSYNC;
143   -
144   - RTS;
145   -ENDPROC(_start_dma_code)
146   -#endif /* CONFIG_BFIN_KERNEL_CLOCK */
arch/blackfin/mach-bf527/include/mach/mem_init.h
View file @ 73feb5c
1   -/*
2   - * File: include/asm-blackfin/mach-bf527/mem_init.h
3   - * Based on:
4   - * Author:
5   - *
6   - * Created:
7   - * Description:
8   - *
9   - * Rev:
10   - *
11   - * Modified:
12   - * Copyright 2004-2007 Analog Devices Inc.
13   - *
14   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
15   - *
16   - * This program is free software; you can redistribute it and/or modify
17   - * it under the terms of the GNU General Public License as published by
18   - * the Free Software Foundation; either version 2, or (at your option)
19   - * any later version.
20   - *
21   - * This program is distributed in the hope that it will be useful,
22   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
23   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24   - * GNU General Public License for more details.
25   - *
26   - * You should have received a copy of the GNU General Public License
27   - * along with this program; see the file COPYING.
28   - * If not, write to the Free Software Foundation,
29   - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30   - */
31   -
32   -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
33   -#if (CONFIG_SCLK_HZ > 119402985)
34   -#define SDRAM_tRP TRP_2
35   -#define SDRAM_tRP_num 2
36   -#define SDRAM_tRAS TRAS_7
37   -#define SDRAM_tRAS_num 7
38   -#define SDRAM_tRCD TRCD_2
39   -#define SDRAM_tWR TWR_2
40   -#endif
41   -#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42   -#define SDRAM_tRP TRP_2
43   -#define SDRAM_tRP_num 2
44   -#define SDRAM_tRAS TRAS_6
45   -#define SDRAM_tRAS_num 6
46   -#define SDRAM_tRCD TRCD_2
47   -#define SDRAM_tWR TWR_2
48   -#endif
49   -#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50   -#define SDRAM_tRP TRP_2
51   -#define SDRAM_tRP_num 2
52   -#define SDRAM_tRAS TRAS_5
53   -#define SDRAM_tRAS_num 5
54   -#define SDRAM_tRCD TRCD_2
55   -#define SDRAM_tWR TWR_2
56   -#endif
57   -#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58   -#define SDRAM_tRP TRP_2
59   -#define SDRAM_tRP_num 2
60   -#define SDRAM_tRAS TRAS_4
61   -#define SDRAM_tRAS_num 4
62   -#define SDRAM_tRCD TRCD_2
63   -#define SDRAM_tWR TWR_2
64   -#endif
65   -#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66   -#define SDRAM_tRP TRP_2
67   -#define SDRAM_tRP_num 2
68   -#define SDRAM_tRAS TRAS_3
69   -#define SDRAM_tRAS_num 3
70   -#define SDRAM_tRCD TRCD_2
71   -#define SDRAM_tWR TWR_2
72   -#endif
73   -#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74   -#define SDRAM_tRP TRP_1
75   -#define SDRAM_tRP_num 1
76   -#define SDRAM_tRAS TRAS_4
77   -#define SDRAM_tRAS_num 3
78   -#define SDRAM_tRCD TRCD_1
79   -#define SDRAM_tWR TWR_2
80   -#endif
81   -#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82   -#define SDRAM_tRP TRP_1
83   -#define SDRAM_tRP_num 1
84   -#define SDRAM_tRAS TRAS_3
85   -#define SDRAM_tRAS_num 3
86   -#define SDRAM_tRCD TRCD_1
87   -#define SDRAM_tWR TWR_2
88   -#endif
89   -#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90   -#define SDRAM_tRP TRP_1
91   -#define SDRAM_tRP_num 1
92   -#define SDRAM_tRAS TRAS_2
93   -#define SDRAM_tRAS_num 2
94   -#define SDRAM_tRCD TRCD_1
95   -#define SDRAM_tWR TWR_2
96   -#endif
97   -#if (CONFIG_SCLK_HZ <= 29850746)
98   -#define SDRAM_tRP TRP_1
99   -#define SDRAM_tRP_num 1
100   -#define SDRAM_tRAS TRAS_1
101   -#define SDRAM_tRAS_num 1
102   -#define SDRAM_tRCD TRCD_1
103   -#define SDRAM_tWR TWR_2
104   -#endif
105   -#endif
106   -
107   -#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108   - /*SDRAM INFORMATION: */
109   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111   -#define SDRAM_CL CL_3
112   -#endif
113   -
114   -#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115   - /*SDRAM INFORMATION: */
116   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117   -#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118   -#define SDRAM_CL CL_3
119   -#endif
120   -
121   -#if (CONFIG_MEM_MT48LC32M8A2_75)
122   - /*SDRAM INFORMATION: */
123   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125   -#define SDRAM_CL CL_3
126   -#endif
127   -
128   -#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129   - /*SDRAM INFORMATION: */
130   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132   -#define SDRAM_CL CL_3
133   -#endif
134   -
135   -#if (CONFIG_MEM_GENERIC_BOARD)
136   - /*SDRAM INFORMATION: Modify this for your board */
137   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139   -#define SDRAM_CL CL_3
140   -#endif
141   -
142   -#if (CONFIG_MEM_MT48LC32M16A2TG_75)
143   - /*SDRAM INFORMATION: */
144   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
145   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
146   -#define SDRAM_CL CL_3
147   -#endif
148   -
149   -/* Equation from section 17 (p17-46) of BF533 HRM */
150   -#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
151   -
152   -/* Enable SCLK Out */
153   -#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
154   -
155   -#if defined CONFIG_CLKIN_HALF
156   -#define CLKIN_HALF 1
157   -#else
158   -#define CLKIN_HALF 0
159   -#endif
160   -
161   -#if defined CONFIG_PLL_BYPASS
162   -#define PLL_BYPASS 1
163   -#else
164   -#define PLL_BYPASS 0
165   -#endif
166   -
167   -/***************************************Currently Not Being Used *********************************/
168   -#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
169   -#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
170   -#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
171   -#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
172   -#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
173   -
174   -#if (flash_EBIU_AMBCTL_TT > 3)
175   -#define flash_EBIU_AMBCTL0_TT B0TT_4
176   -#endif
177   -#if (flash_EBIU_AMBCTL_TT == 3)
178   -#define flash_EBIU_AMBCTL0_TT B0TT_3
179   -#endif
180   -#if (flash_EBIU_AMBCTL_TT == 2)
181   -#define flash_EBIU_AMBCTL0_TT B0TT_2
182   -#endif
183   -#if (flash_EBIU_AMBCTL_TT < 2)
184   -#define flash_EBIU_AMBCTL0_TT B0TT_1
185   -#endif
186   -
187   -#if (flash_EBIU_AMBCTL_ST > 3)
188   -#define flash_EBIU_AMBCTL0_ST B0ST_4
189   -#endif
190   -#if (flash_EBIU_AMBCTL_ST == 3)
191   -#define flash_EBIU_AMBCTL0_ST B0ST_3
192   -#endif
193   -#if (flash_EBIU_AMBCTL_ST == 2)
194   -#define flash_EBIU_AMBCTL0_ST B0ST_2
195   -#endif
196   -#if (flash_EBIU_AMBCTL_ST < 2)
197   -#define flash_EBIU_AMBCTL0_ST B0ST_1
198   -#endif
199   -
200   -#if (flash_EBIU_AMBCTL_HT > 2)
201   -#define flash_EBIU_AMBCTL0_HT B0HT_3
202   -#endif
203   -#if (flash_EBIU_AMBCTL_HT == 2)
204   -#define flash_EBIU_AMBCTL0_HT B0HT_2
205   -#endif
206   -#if (flash_EBIU_AMBCTL_HT == 1)
207   -#define flash_EBIU_AMBCTL0_HT B0HT_1
208   -#endif
209   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
210   -#define flash_EBIU_AMBCTL0_HT B0HT_0
211   -#endif
212   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
213   -#define flash_EBIU_AMBCTL0_HT B0HT_1
214   -#endif
215   -
216   -#if (flash_EBIU_AMBCTL_WAT > 14)
217   -#define flash_EBIU_AMBCTL0_WAT B0WAT_15
218   -#endif
219   -#if (flash_EBIU_AMBCTL_WAT == 14)
220   -#define flash_EBIU_AMBCTL0_WAT B0WAT_14
221   -#endif
222   -#if (flash_EBIU_AMBCTL_WAT == 13)
223   -#define flash_EBIU_AMBCTL0_WAT B0WAT_13
224   -#endif
225   -#if (flash_EBIU_AMBCTL_WAT == 12)
226   -#define flash_EBIU_AMBCTL0_WAT B0WAT_12
227   -#endif
228   -#if (flash_EBIU_AMBCTL_WAT == 11)
229   -#define flash_EBIU_AMBCTL0_WAT B0WAT_11
230   -#endif
231   -#if (flash_EBIU_AMBCTL_WAT == 10)
232   -#define flash_EBIU_AMBCTL0_WAT B0WAT_10
233   -#endif
234   -#if (flash_EBIU_AMBCTL_WAT == 9)
235   -#define flash_EBIU_AMBCTL0_WAT B0WAT_9
236   -#endif
237   -#if (flash_EBIU_AMBCTL_WAT == 8)
238   -#define flash_EBIU_AMBCTL0_WAT B0WAT_8
239   -#endif
240   -#if (flash_EBIU_AMBCTL_WAT == 7)
241   -#define flash_EBIU_AMBCTL0_WAT B0WAT_7
242   -#endif
243   -#if (flash_EBIU_AMBCTL_WAT == 6)
244   -#define flash_EBIU_AMBCTL0_WAT B0WAT_6
245   -#endif
246   -#if (flash_EBIU_AMBCTL_WAT == 5)
247   -#define flash_EBIU_AMBCTL0_WAT B0WAT_5
248   -#endif
249   -#if (flash_EBIU_AMBCTL_WAT == 4)
250   -#define flash_EBIU_AMBCTL0_WAT B0WAT_4
251   -#endif
252   -#if (flash_EBIU_AMBCTL_WAT == 3)
253   -#define flash_EBIU_AMBCTL0_WAT B0WAT_3
254   -#endif
255   -#if (flash_EBIU_AMBCTL_WAT == 2)
256   -#define flash_EBIU_AMBCTL0_WAT B0WAT_2
257   -#endif
258   -#if (flash_EBIU_AMBCTL_WAT == 1)
259   -#define flash_EBIU_AMBCTL0_WAT B0WAT_1
260   -#endif
261   -
262   -#if (flash_EBIU_AMBCTL_RAT > 14)
263   -#define flash_EBIU_AMBCTL0_RAT B0RAT_15
264   -#endif
265   -#if (flash_EBIU_AMBCTL_RAT == 14)
266   -#define flash_EBIU_AMBCTL0_RAT B0RAT_14
267   -#endif
268   -#if (flash_EBIU_AMBCTL_RAT == 13)
269   -#define flash_EBIU_AMBCTL0_RAT B0RAT_13
270   -#endif
271   -#if (flash_EBIU_AMBCTL_RAT == 12)
272   -#define flash_EBIU_AMBCTL0_RAT B0RAT_12
273   -#endif
274   -#if (flash_EBIU_AMBCTL_RAT == 11)
275   -#define flash_EBIU_AMBCTL0_RAT B0RAT_11
276   -#endif
277   -#if (flash_EBIU_AMBCTL_RAT == 10)
278   -#define flash_EBIU_AMBCTL0_RAT B0RAT_10
279   -#endif
280   -#if (flash_EBIU_AMBCTL_RAT == 9)
281   -#define flash_EBIU_AMBCTL0_RAT B0RAT_9
282   -#endif
283   -#if (flash_EBIU_AMBCTL_RAT == 8)
284   -#define flash_EBIU_AMBCTL0_RAT B0RAT_8
285   -#endif
286   -#if (flash_EBIU_AMBCTL_RAT == 7)
287   -#define flash_EBIU_AMBCTL0_RAT B0RAT_7
288   -#endif
289   -#if (flash_EBIU_AMBCTL_RAT == 6)
290   -#define flash_EBIU_AMBCTL0_RAT B0RAT_6
291   -#endif
292   -#if (flash_EBIU_AMBCTL_RAT == 5)
293   -#define flash_EBIU_AMBCTL0_RAT B0RAT_5
294   -#endif
295   -#if (flash_EBIU_AMBCTL_RAT == 4)
296   -#define flash_EBIU_AMBCTL0_RAT B0RAT_4
297   -#endif
298   -#if (flash_EBIU_AMBCTL_RAT == 3)
299   -#define flash_EBIU_AMBCTL0_RAT B0RAT_3
300   -#endif
301   -#if (flash_EBIU_AMBCTL_RAT == 2)
302   -#define flash_EBIU_AMBCTL0_RAT B0RAT_2
303   -#endif
304   -#if (flash_EBIU_AMBCTL_RAT == 1)
305   -#define flash_EBIU_AMBCTL0_RAT B0RAT_1
306   -#endif
307   -
308   -#define flash_EBIU_AMBCTL0 \
309   - (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
310   - flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
arch/blackfin/mach-bf533/Makefile
Diff comments   View file @ 73feb5c
... ... @@ -2,7 +2,5 @@
2 2 # arch/blackfin/mach-bf533/Makefile
3 3 #
4 4  
5   -extra-y := head.o
6   -
7 5 obj-y := ints-priority.o dma.o
arch/blackfin/mach-bf533/head.S
View file @ 73feb5c
1   -/*
2   - * File: arch/blackfin/mach-bf533/head.S
3   - * Based on:
4   - * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5   - *
6   - * Created: 1998
7   - * Description: bf533 startup file
8   - *
9   - * Modified:
10   - * Copyright 2004-2006 Analog Devices Inc.
11   - *
12   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
13   - *
14   - * This program is free software; you can redistribute it and/or modify
15   - * it under the terms of the GNU General Public License as published by
16   - * the Free Software Foundation; either version 2 of the License, or
17   - * (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, see the file COPYING, or write
26   - * to the Free Software Foundation, Inc.,
27   - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28   - */
29   -
30   -#include <linux/linkage.h>
31   -#include <linux/init.h>
32   -#include <asm/blackfin.h>
33   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
34   -#include <asm/clocks.h>
35   -#include <mach/mem_init.h>
36   -#endif
37   -
38   -.section .l1.text
39   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
40   -ENTRY(_start_dma_code)
41   - p0.h = hi(SIC_IWR);
42   - p0.l = lo(SIC_IWR);
43   - r0.l = 0x1;
44   - r0.h = 0x0;
45   - [p0] = r0;
46   - SSYNC;
47   -
48   - /*
49   - * Set PLL_CTL
50   - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
51   - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
52   - * - [7] = output delay (add 200ps of delay to mem signals)
53   - * - [6] = input delay (add 200ps of input delay to mem signals)
54   - * - [5] = PDWN : 1=All Clocks off
55   - * - [3] = STOPCK : 1=Core Clock off
56   - * - [1] = PLL_OFF : 1=Disable Power to PLL
57   - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
58   - * all other bits set to zero
59   - */
60   -
61   - p0.h = hi(PLL_LOCKCNT);
62   - p0.l = lo(PLL_LOCKCNT);
63   - r0 = 0x300(Z);
64   - w[p0] = r0.l;
65   - ssync;
66   -
67   - P2.H = hi(EBIU_SDGCTL);
68   - P2.L = lo(EBIU_SDGCTL);
69   - R0 = [P2];
70   - BITSET (R0, 24);
71   - [P2] = R0;
72   - SSYNC;
73   -
74   - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
75   - r0 = r0 << 9; /* Shift it over, */
76   - r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
77   - r0 = r1 | r0;
78   - r1 = PLL_BYPASS; /* Bypass the PLL? */
79   - r1 = r1 << 8; /* Shift it over */
80   - r0 = r1 | r0; /* add them all together */
81   -#ifdef ANOMALY_05000265
82   - BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
83   -#endif
84   -
85   - p0.h = hi(PLL_CTL);
86   - p0.l = lo(PLL_CTL); /* Load the address */
87   - cli r2; /* Disable interrupts */
88   - ssync;
89   - w[p0] = r0.l; /* Set the value */
90   - idle; /* Wait for the PLL to stablize */
91   - sti r2; /* Enable interrupts */
92   -
93   -.Lcheck_again:
94   - p0.h = hi(PLL_STAT);
95   - p0.l = lo(PLL_STAT);
96   - R0 = W[P0](Z);
97   - CC = BITTST(R0,5);
98   - if ! CC jump .Lcheck_again;
99   -
100   - /* Configure SCLK & CCLK Dividers */
101   - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
102   - p0.h = hi(PLL_DIV);
103   - p0.l = lo(PLL_DIV);
104   - w[p0] = r0.l;
105   - ssync;
106   -
107   - p0.l = lo(EBIU_SDRRC);
108   - p0.h = hi(EBIU_SDRRC);
109   - r0 = mem_SDRRC;
110   - w[p0] = r0.l;
111   - ssync;
112   -
113   - P2.H = hi(EBIU_SDGCTL);
114   - P2.L = lo(EBIU_SDGCTL);
115   - R0 = [P2];
116   - BITCLR (R0, 24);
117   - p0.h = hi(EBIU_SDSTAT);
118   - p0.l = lo(EBIU_SDSTAT);
119   - r2.l = w[p0];
120   - cc = bittst(r2,3);
121   - if !cc jump .Lskip;
122   - NOP;
123   - BITSET (R0, 23);
124   -.Lskip:
125   - [P2] = R0;
126   - SSYNC;
127   -
128   - R0.L = lo(mem_SDGCTL);
129   - R0.H = hi(mem_SDGCTL);
130   - R1 = [p2];
131   - R1 = R1 | R0;
132   - [P2] = R1;
133   - SSYNC;
134   -
135   - RTS;
136   -ENDPROC(_start_dma_code)
137   -#endif /* CONFIG_BFIN_KERNEL_CLOCK */
arch/blackfin/mach-bf533/include/mach/mem_init.h
View file @ 73feb5c
1   -/*
2   - * File: include/asm-blackfin/mach-bf533/mem_init.h
3   - * Based on:
4   - * Author:
5   - *
6   - * Created:
7   - * Description:
8   - *
9   - * Rev:
10   - *
11   - * Modified:
12   - * Copyright 2004-2006 Analog Devices Inc.
13   - *
14   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
15   - *
16   - * This program is free software; you can redistribute it and/or modify
17   - * it under the terms of the GNU General Public License as published by
18   - * the Free Software Foundation; either version 2, or (at your option)
19   - * any later version.
20   - *
21   - * This program is distributed in the hope that it will be useful,
22   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
23   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24   - * GNU General Public License for more details.
25   - *
26   - * You should have received a copy of the GNU General Public License
27   - * along with this program; see the file COPYING.
28   - * If not, write to the Free Software Foundation,
29   - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30   - */
31   -
32   -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
33   - CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
34   -#if (CONFIG_SCLK_HZ > 119402985)
35   -#define SDRAM_tRP TRP_2
36   -#define SDRAM_tRP_num 2
37   -#define SDRAM_tRAS TRAS_7
38   -#define SDRAM_tRAS_num 7
39   -#define SDRAM_tRCD TRCD_2
40   -#define SDRAM_tWR TWR_2
41   -#endif
42   -#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
43   -#define SDRAM_tRP TRP_2
44   -#define SDRAM_tRP_num 2
45   -#define SDRAM_tRAS TRAS_6
46   -#define SDRAM_tRAS_num 6
47   -#define SDRAM_tRCD TRCD_2
48   -#define SDRAM_tWR TWR_2
49   -#endif
50   -#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
51   -#define SDRAM_tRP TRP_2
52   -#define SDRAM_tRP_num 2
53   -#define SDRAM_tRAS TRAS_5
54   -#define SDRAM_tRAS_num 5
55   -#define SDRAM_tRCD TRCD_2
56   -#define SDRAM_tWR TWR_2
57   -#endif
58   -#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
59   -#define SDRAM_tRP TRP_2
60   -#define SDRAM_tRP_num 2
61   -#define SDRAM_tRAS TRAS_4
62   -#define SDRAM_tRAS_num 4
63   -#define SDRAM_tRCD TRCD_2
64   -#define SDRAM_tWR TWR_2
65   -#endif
66   -#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
67   -#define SDRAM_tRP TRP_2
68   -#define SDRAM_tRP_num 2
69   -#define SDRAM_tRAS TRAS_3
70   -#define SDRAM_tRAS_num 3
71   -#define SDRAM_tRCD TRCD_2
72   -#define SDRAM_tWR TWR_2
73   -#endif
74   -#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
75   -#define SDRAM_tRP TRP_1
76   -#define SDRAM_tRP_num 1
77   -#define SDRAM_tRAS TRAS_4
78   -#define SDRAM_tRAS_num 3
79   -#define SDRAM_tRCD TRCD_1
80   -#define SDRAM_tWR TWR_2
81   -#endif
82   -#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
83   -#define SDRAM_tRP TRP_1
84   -#define SDRAM_tRP_num 1
85   -#define SDRAM_tRAS TRAS_3
86   -#define SDRAM_tRAS_num 3
87   -#define SDRAM_tRCD TRCD_1
88   -#define SDRAM_tWR TWR_2
89   -#endif
90   -#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
91   -#define SDRAM_tRP TRP_1
92   -#define SDRAM_tRP_num 1
93   -#define SDRAM_tRAS TRAS_2
94   -#define SDRAM_tRAS_num 2
95   -#define SDRAM_tRCD TRCD_1
96   -#define SDRAM_tWR TWR_2
97   -#endif
98   -#if (CONFIG_SCLK_HZ <= 29850746)
99   -#define SDRAM_tRP TRP_1
100   -#define SDRAM_tRP_num 1
101   -#define SDRAM_tRAS TRAS_1
102   -#define SDRAM_tRAS_num 1
103   -#define SDRAM_tRCD TRCD_1
104   -#define SDRAM_tWR TWR_2
105   -#endif
106   -#endif
107   -
108   -#if (CONFIG_MEM_MT48LC16M16A2TG_75)
109   - /*SDRAM INFORMATION: */
110   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
111   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
112   -#define SDRAM_CL CL_3
113   -#endif
114   -
115   -#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
116   - /*SDRAM INFORMATION: */
117   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
118   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
119   -#define SDRAM_CL CL_3
120   -#endif
121   -
122   -#if (CONFIG_MEM_MT48LC32M16A2TG_75)
123   - /*SDRAM INFORMATION: */
124   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
125   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
126   -#define SDRAM_CL CL_3
127   -#endif
128   -
129   -#if (CONFIG_MEM_GENERIC_BOARD)
130   - /*SDRAM INFORMATION: Modify this for your board */
131   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
132   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
133   -#define SDRAM_CL CL_3
134   -#endif
135   -
136   -/* Equation from section 17 (p17-46) of BF533 HRM */
137   -#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
138   -
139   -/* Enable SCLK Out */
140   -#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
141   -
142   -#if defined CONFIG_CLKIN_HALF
143   -#define CLKIN_HALF 1
144   -#else
145   -#define CLKIN_HALF 0
146   -#endif
147   -
148   -#if defined CONFIG_PLL_BYPASS
149   -#define PLL_BYPASS 1
150   -#else
151   -#define PLL_BYPASS 0
152   -#endif
153   -
154   -/***************************************Currently Not Being Used *********************************/
155   -#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
156   -#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
157   -#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
158   -#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
159   -#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
160   -
161   -#if (flash_EBIU_AMBCTL_TT > 3)
162   -#define flash_EBIU_AMBCTL0_TT B0TT_4
163   -#endif
164   -#if (flash_EBIU_AMBCTL_TT == 3)
165   -#define flash_EBIU_AMBCTL0_TT B0TT_3
166   -#endif
167   -#if (flash_EBIU_AMBCTL_TT == 2)
168   -#define flash_EBIU_AMBCTL0_TT B0TT_2
169   -#endif
170   -#if (flash_EBIU_AMBCTL_TT < 2)
171   -#define flash_EBIU_AMBCTL0_TT B0TT_1
172   -#endif
173   -
174   -#if (flash_EBIU_AMBCTL_ST > 3)
175   -#define flash_EBIU_AMBCTL0_ST B0ST_4
176   -#endif
177   -#if (flash_EBIU_AMBCTL_ST == 3)
178   -#define flash_EBIU_AMBCTL0_ST B0ST_3
179   -#endif
180   -#if (flash_EBIU_AMBCTL_ST == 2)
181   -#define flash_EBIU_AMBCTL0_ST B0ST_2
182   -#endif
183   -#if (flash_EBIU_AMBCTL_ST < 2)
184   -#define flash_EBIU_AMBCTL0_ST B0ST_1
185   -#endif
186   -
187   -#if (flash_EBIU_AMBCTL_HT > 2)
188   -#define flash_EBIU_AMBCTL0_HT B0HT_3
189   -#endif
190   -#if (flash_EBIU_AMBCTL_HT == 2)
191   -#define flash_EBIU_AMBCTL0_HT B0HT_2
192   -#endif
193   -#if (flash_EBIU_AMBCTL_HT == 1)
194   -#define flash_EBIU_AMBCTL0_HT B0HT_1
195   -#endif
196   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
197   -#define flash_EBIU_AMBCTL0_HT B0HT_0
198   -#endif
199   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
200   -#define flash_EBIU_AMBCTL0_HT B0HT_1
201   -#endif
202   -
203   -#if (flash_EBIU_AMBCTL_WAT > 14)
204   -#define flash_EBIU_AMBCTL0_WAT B0WAT_15
205   -#endif
206   -#if (flash_EBIU_AMBCTL_WAT == 14)
207   -#define flash_EBIU_AMBCTL0_WAT B0WAT_14
208   -#endif
209   -#if (flash_EBIU_AMBCTL_WAT == 13)
210   -#define flash_EBIU_AMBCTL0_WAT B0WAT_13
211   -#endif
212   -#if (flash_EBIU_AMBCTL_WAT == 12)
213   -#define flash_EBIU_AMBCTL0_WAT B0WAT_12
214   -#endif
215   -#if (flash_EBIU_AMBCTL_WAT == 11)
216   -#define flash_EBIU_AMBCTL0_WAT B0WAT_11
217   -#endif
218   -#if (flash_EBIU_AMBCTL_WAT == 10)
219   -#define flash_EBIU_AMBCTL0_WAT B0WAT_10
220   -#endif
221   -#if (flash_EBIU_AMBCTL_WAT == 9)
222   -#define flash_EBIU_AMBCTL0_WAT B0WAT_9
223   -#endif
224   -#if (flash_EBIU_AMBCTL_WAT == 8)
225   -#define flash_EBIU_AMBCTL0_WAT B0WAT_8
226   -#endif
227   -#if (flash_EBIU_AMBCTL_WAT == 7)
228   -#define flash_EBIU_AMBCTL0_WAT B0WAT_7
229   -#endif
230   -#if (flash_EBIU_AMBCTL_WAT == 6)
231   -#define flash_EBIU_AMBCTL0_WAT B0WAT_6
232   -#endif
233   -#if (flash_EBIU_AMBCTL_WAT == 5)
234   -#define flash_EBIU_AMBCTL0_WAT B0WAT_5
235   -#endif
236   -#if (flash_EBIU_AMBCTL_WAT == 4)
237   -#define flash_EBIU_AMBCTL0_WAT B0WAT_4
238   -#endif
239   -#if (flash_EBIU_AMBCTL_WAT == 3)
240   -#define flash_EBIU_AMBCTL0_WAT B0WAT_3
241   -#endif
242   -#if (flash_EBIU_AMBCTL_WAT == 2)
243   -#define flash_EBIU_AMBCTL0_WAT B0WAT_2
244   -#endif
245   -#if (flash_EBIU_AMBCTL_WAT == 1)
246   -#define flash_EBIU_AMBCTL0_WAT B0WAT_1
247   -#endif
248   -
249   -#if (flash_EBIU_AMBCTL_RAT > 14)
250   -#define flash_EBIU_AMBCTL0_RAT B0RAT_15
251   -#endif
252   -#if (flash_EBIU_AMBCTL_RAT == 14)
253   -#define flash_EBIU_AMBCTL0_RAT B0RAT_14
254   -#endif
255   -#if (flash_EBIU_AMBCTL_RAT == 13)
256   -#define flash_EBIU_AMBCTL0_RAT B0RAT_13
257   -#endif
258   -#if (flash_EBIU_AMBCTL_RAT == 12)
259   -#define flash_EBIU_AMBCTL0_RAT B0RAT_12
260   -#endif
261   -#if (flash_EBIU_AMBCTL_RAT == 11)
262   -#define flash_EBIU_AMBCTL0_RAT B0RAT_11
263   -#endif
264   -#if (flash_EBIU_AMBCTL_RAT == 10)
265   -#define flash_EBIU_AMBCTL0_RAT B0RAT_10
266   -#endif
267   -#if (flash_EBIU_AMBCTL_RAT == 9)
268   -#define flash_EBIU_AMBCTL0_RAT B0RAT_9
269   -#endif
270   -#if (flash_EBIU_AMBCTL_RAT == 8)
271   -#define flash_EBIU_AMBCTL0_RAT B0RAT_8
272   -#endif
273   -#if (flash_EBIU_AMBCTL_RAT == 7)
274   -#define flash_EBIU_AMBCTL0_RAT B0RAT_7
275   -#endif
276   -#if (flash_EBIU_AMBCTL_RAT == 6)
277   -#define flash_EBIU_AMBCTL0_RAT B0RAT_6
278   -#endif
279   -#if (flash_EBIU_AMBCTL_RAT == 5)
280   -#define flash_EBIU_AMBCTL0_RAT B0RAT_5
281   -#endif
282   -#if (flash_EBIU_AMBCTL_RAT == 4)
283   -#define flash_EBIU_AMBCTL0_RAT B0RAT_4
284   -#endif
285   -#if (flash_EBIU_AMBCTL_RAT == 3)
286   -#define flash_EBIU_AMBCTL0_RAT B0RAT_3
287   -#endif
288   -#if (flash_EBIU_AMBCTL_RAT == 2)
289   -#define flash_EBIU_AMBCTL0_RAT B0RAT_2
290   -#endif
291   -#if (flash_EBIU_AMBCTL_RAT == 1)
292   -#define flash_EBIU_AMBCTL0_RAT B0RAT_1
293   -#endif
294   -
295   -#define flash_EBIU_AMBCTL0 \
296   - (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
297   - flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
arch/blackfin/mach-bf537/Makefile
Diff comments   View file @ 73feb5c
... ... @@ -2,7 +2,5 @@
2 2 # arch/blackfin/mach-bf537/Makefile
3 3 #
4 4  
5   -extra-y := head.o
6   -
7 5 obj-y := ints-priority.o dma.o
arch/blackfin/mach-bf537/head.S
View file @ 73feb5c
1   -/*
2   - * File: arch/blackfin/mach-bf537/head.S
3   - * Based on: arch/blackfin/mach-bf533/head.S
4   - * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5   - *
6   - * Created: 1998
7   - * Description: Startup code for Blackfin BF537
8   - *
9   - * Modified:
10   - * Copyright 2004-2006 Analog Devices Inc.
11   - *
12   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
13   - *
14   - * This program is free software; you can redistribute it and/or modify
15   - * it under the terms of the GNU General Public License as published by
16   - * the Free Software Foundation; either version 2 of the License, or
17   - * (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, see the file COPYING, or write
26   - * to the Free Software Foundation, Inc.,
27   - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28   - */
29   -
30   -#include <linux/linkage.h>
31   -#include <linux/init.h>
32   -#include <asm/blackfin.h>
33   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
34   -#include <asm/clocks.h>
35   -#include <mach/mem_init.h>
36   -#endif
37   -
38   -.section .l1.text
39   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
40   -ENTRY(_start_dma_code)
41   -
42   - /* Enable PHY CLK buffer output */
43   - p0.h = hi(VR_CTL);
44   - p0.l = lo(VR_CTL);
45   - r0.l = w[p0];
46   - bitset(r0, 14);
47   - w[p0] = r0.l;
48   - ssync;
49   -
50   - p0.h = hi(SIC_IWR);
51   - p0.l = lo(SIC_IWR);
52   - r0.l = 0x1;
53   - r0.h = 0x0;
54   - [p0] = r0;
55   - SSYNC;
56   -
57   - /*
58   - * Set PLL_CTL
59   - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
60   - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
61   - * - [7] = output delay (add 200ps of delay to mem signals)
62   - * - [6] = input delay (add 200ps of input delay to mem signals)
63   - * - [5] = PDWN : 1=All Clocks off
64   - * - [3] = STOPCK : 1=Core Clock off
65   - * - [1] = PLL_OFF : 1=Disable Power to PLL
66   - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
67   - * all other bits set to zero
68   - */
69   -
70   - p0.h = hi(PLL_LOCKCNT);
71   - p0.l = lo(PLL_LOCKCNT);
72   - r0 = 0x300(Z);
73   - w[p0] = r0.l;
74   - ssync;
75   -
76   - P2.H = hi(EBIU_SDGCTL);
77   - P2.L = lo(EBIU_SDGCTL);
78   - R0 = [P2];
79   - BITSET (R0, 24);
80   - [P2] = R0;
81   - SSYNC;
82   -
83   - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
84   - r0 = r0 << 9; /* Shift it over, */
85   - r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
86   - r0 = r1 | r0;
87   - r1 = PLL_BYPASS; /* Bypass the PLL? */
88   - r1 = r1 << 8; /* Shift it over */
89   - r0 = r1 | r0; /* add them all together */
90   -#ifdef ANOMALY_05000265
91   - BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
92   -#endif
93   -
94   - p0.h = hi(PLL_CTL);
95   - p0.l = lo(PLL_CTL); /* Load the address */
96   - cli r2; /* Disable interrupts */
97   - ssync;
98   - w[p0] = r0.l; /* Set the value */
99   - idle; /* Wait for the PLL to stablize */
100   - sti r2; /* Enable interrupts */
101   -
102   -.Lcheck_again:
103   - p0.h = hi(PLL_STAT);
104   - p0.l = lo(PLL_STAT);
105   - R0 = W[P0](Z);
106   - CC = BITTST(R0,5);
107   - if ! CC jump .Lcheck_again;
108   -
109   - /* Configure SCLK & CCLK Dividers */
110   - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
111   - p0.h = hi(PLL_DIV);
112   - p0.l = lo(PLL_DIV);
113   - w[p0] = r0.l;
114   - ssync;
115   -
116   - p0.l = lo(EBIU_SDRRC);
117   - p0.h = hi(EBIU_SDRRC);
118   - r0 = mem_SDRRC;
119   - w[p0] = r0.l;
120   - ssync;
121   -
122   - P2.H = hi(EBIU_SDGCTL);
123   - P2.L = lo(EBIU_SDGCTL);
124   - R0 = [P2];
125   - BITCLR (R0, 24);
126   - p0.h = hi(EBIU_SDSTAT);
127   - p0.l = lo(EBIU_SDSTAT);
128   - r2.l = w[p0];
129   - cc = bittst(r2,3);
130   - if !cc jump .Lskip;
131   - NOP;
132   - BITSET (R0, 23);
133   -.Lskip:
134   - [P2] = R0;
135   - SSYNC;
136   -
137   - R0.L = lo(mem_SDGCTL);
138   - R0.H = hi(mem_SDGCTL);
139   - R1 = [p2];
140   - R1 = R1 | R0;
141   - [P2] = R1;
142   - SSYNC;
143   -
144   - RTS;
145   -ENDPROC(_start_dma_code)
146   -#endif /* CONFIG_BFIN_KERNEL_CLOCK */
arch/blackfin/mach-bf537/include/mach/mem_init.h
View file @ 73feb5c
1   -/*
2   - * File: include/asm-blackfin/mach-bf537/mem_init.h
3   - * Based on:
4   - * Author:
5   - *
6   - * Created:
7   - * Description:
8   - *
9   - * Rev:
10   - *
11   - * Modified:
12   - * Copyright 2004-2006 Analog Devices Inc.
13   - *
14   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
15   - *
16   - * This program is free software; you can redistribute it and/or modify
17   - * it under the terms of the GNU General Public License as published by
18   - * the Free Software Foundation; either version 2, or (at your option)
19   - * any later version.
20   - *
21   - * This program is distributed in the hope that it will be useful,
22   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
23   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24   - * GNU General Public License for more details.
25   - *
26   - * You should have received a copy of the GNU General Public License
27   - * along with this program; see the file COPYING.
28   - * If not, write to the Free Software Foundation,
29   - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30   - */
31   -
32   -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
33   -#if (CONFIG_SCLK_HZ > 119402985)
34   -#define SDRAM_tRP TRP_2
35   -#define SDRAM_tRP_num 2
36   -#define SDRAM_tRAS TRAS_7
37   -#define SDRAM_tRAS_num 7
38   -#define SDRAM_tRCD TRCD_2
39   -#define SDRAM_tWR TWR_2
40   -#endif
41   -#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42   -#define SDRAM_tRP TRP_2
43   -#define SDRAM_tRP_num 2
44   -#define SDRAM_tRAS TRAS_6
45   -#define SDRAM_tRAS_num 6
46   -#define SDRAM_tRCD TRCD_2
47   -#define SDRAM_tWR TWR_2
48   -#endif
49   -#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50   -#define SDRAM_tRP TRP_2
51   -#define SDRAM_tRP_num 2
52   -#define SDRAM_tRAS TRAS_5
53   -#define SDRAM_tRAS_num 5
54   -#define SDRAM_tRCD TRCD_2
55   -#define SDRAM_tWR TWR_2
56   -#endif
57   -#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58   -#define SDRAM_tRP TRP_2
59   -#define SDRAM_tRP_num 2
60   -#define SDRAM_tRAS TRAS_4
61   -#define SDRAM_tRAS_num 4
62   -#define SDRAM_tRCD TRCD_2
63   -#define SDRAM_tWR TWR_2
64   -#endif
65   -#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66   -#define SDRAM_tRP TRP_2
67   -#define SDRAM_tRP_num 2
68   -#define SDRAM_tRAS TRAS_3
69   -#define SDRAM_tRAS_num 3
70   -#define SDRAM_tRCD TRCD_2
71   -#define SDRAM_tWR TWR_2
72   -#endif
73   -#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74   -#define SDRAM_tRP TRP_1
75   -#define SDRAM_tRP_num 1
76   -#define SDRAM_tRAS TRAS_4
77   -#define SDRAM_tRAS_num 3
78   -#define SDRAM_tRCD TRCD_1
79   -#define SDRAM_tWR TWR_2
80   -#endif
81   -#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82   -#define SDRAM_tRP TRP_1
83   -#define SDRAM_tRP_num 1
84   -#define SDRAM_tRAS TRAS_3
85   -#define SDRAM_tRAS_num 3
86   -#define SDRAM_tRCD TRCD_1
87   -#define SDRAM_tWR TWR_2
88   -#endif
89   -#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90   -#define SDRAM_tRP TRP_1
91   -#define SDRAM_tRP_num 1
92   -#define SDRAM_tRAS TRAS_2
93   -#define SDRAM_tRAS_num 2
94   -#define SDRAM_tRCD TRCD_1
95   -#define SDRAM_tWR TWR_2
96   -#endif
97   -#if (CONFIG_SCLK_HZ <= 29850746)
98   -#define SDRAM_tRP TRP_1
99   -#define SDRAM_tRP_num 1
100   -#define SDRAM_tRAS TRAS_1
101   -#define SDRAM_tRAS_num 1
102   -#define SDRAM_tRCD TRCD_1
103   -#define SDRAM_tWR TWR_2
104   -#endif
105   -#endif
106   -
107   -#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108   - /*SDRAM INFORMATION: */
109   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111   -#define SDRAM_CL CL_3
112   -#endif
113   -
114   -#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115   - /*SDRAM INFORMATION: */
116   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117   -#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118   -#define SDRAM_CL CL_3
119   -#endif
120   -
121   -#if (CONFIG_MEM_MT48LC32M8A2_75)
122   - /*SDRAM INFORMATION: */
123   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125   -#define SDRAM_CL CL_3
126   -#endif
127   -
128   -#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129   - /*SDRAM INFORMATION: */
130   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132   -#define SDRAM_CL CL_3
133   -#endif
134   -
135   -#if (CONFIG_MEM_GENERIC_BOARD)
136   - /*SDRAM INFORMATION: Modify this for your board */
137   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139   -#define SDRAM_CL CL_3
140   -#endif
141   -
142   -/* Equation from section 17 (p17-46) of BF533 HRM */
143   -#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
144   -
145   -/* Enable SCLK Out */
146   -#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
147   -
148   -#if defined CONFIG_CLKIN_HALF
149   -#define CLKIN_HALF 1
150   -#else
151   -#define CLKIN_HALF 0
152   -#endif
153   -
154   -#if defined CONFIG_PLL_BYPASS
155   -#define PLL_BYPASS 1
156   -#else
157   -#define PLL_BYPASS 0
158   -#endif
159   -
160   -/***************************************Currently Not Being Used *********************************/
161   -#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
162   -#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
163   -#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
164   -#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
165   -#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
166   -
167   -#if (flash_EBIU_AMBCTL_TT > 3)
168   -#define flash_EBIU_AMBCTL0_TT B0TT_4
169   -#endif
170   -#if (flash_EBIU_AMBCTL_TT == 3)
171   -#define flash_EBIU_AMBCTL0_TT B0TT_3
172   -#endif
173   -#if (flash_EBIU_AMBCTL_TT == 2)
174   -#define flash_EBIU_AMBCTL0_TT B0TT_2
175   -#endif
176   -#if (flash_EBIU_AMBCTL_TT < 2)
177   -#define flash_EBIU_AMBCTL0_TT B0TT_1
178   -#endif
179   -
180   -#if (flash_EBIU_AMBCTL_ST > 3)
181   -#define flash_EBIU_AMBCTL0_ST B0ST_4
182   -#endif
183   -#if (flash_EBIU_AMBCTL_ST == 3)
184   -#define flash_EBIU_AMBCTL0_ST B0ST_3
185   -#endif
186   -#if (flash_EBIU_AMBCTL_ST == 2)
187   -#define flash_EBIU_AMBCTL0_ST B0ST_2
188   -#endif
189   -#if (flash_EBIU_AMBCTL_ST < 2)
190   -#define flash_EBIU_AMBCTL0_ST B0ST_1
191   -#endif
192   -
193   -#if (flash_EBIU_AMBCTL_HT > 2)
194   -#define flash_EBIU_AMBCTL0_HT B0HT_3
195   -#endif
196   -#if (flash_EBIU_AMBCTL_HT == 2)
197   -#define flash_EBIU_AMBCTL0_HT B0HT_2
198   -#endif
199   -#if (flash_EBIU_AMBCTL_HT == 1)
200   -#define flash_EBIU_AMBCTL0_HT B0HT_1
201   -#endif
202   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
203   -#define flash_EBIU_AMBCTL0_HT B0HT_0
204   -#endif
205   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
206   -#define flash_EBIU_AMBCTL0_HT B0HT_1
207   -#endif
208   -
209   -#if (flash_EBIU_AMBCTL_WAT > 14)
210   -#define flash_EBIU_AMBCTL0_WAT B0WAT_15
211   -#endif
212   -#if (flash_EBIU_AMBCTL_WAT == 14)
213   -#define flash_EBIU_AMBCTL0_WAT B0WAT_14
214   -#endif
215   -#if (flash_EBIU_AMBCTL_WAT == 13)
216   -#define flash_EBIU_AMBCTL0_WAT B0WAT_13
217   -#endif
218   -#if (flash_EBIU_AMBCTL_WAT == 12)
219   -#define flash_EBIU_AMBCTL0_WAT B0WAT_12
220   -#endif
221   -#if (flash_EBIU_AMBCTL_WAT == 11)
222   -#define flash_EBIU_AMBCTL0_WAT B0WAT_11
223   -#endif
224   -#if (flash_EBIU_AMBCTL_WAT == 10)
225   -#define flash_EBIU_AMBCTL0_WAT B0WAT_10
226   -#endif
227   -#if (flash_EBIU_AMBCTL_WAT == 9)
228   -#define flash_EBIU_AMBCTL0_WAT B0WAT_9
229   -#endif
230   -#if (flash_EBIU_AMBCTL_WAT == 8)
231   -#define flash_EBIU_AMBCTL0_WAT B0WAT_8
232   -#endif
233   -#if (flash_EBIU_AMBCTL_WAT == 7)
234   -#define flash_EBIU_AMBCTL0_WAT B0WAT_7
235   -#endif
236   -#if (flash_EBIU_AMBCTL_WAT == 6)
237   -#define flash_EBIU_AMBCTL0_WAT B0WAT_6
238   -#endif
239   -#if (flash_EBIU_AMBCTL_WAT == 5)
240   -#define flash_EBIU_AMBCTL0_WAT B0WAT_5
241   -#endif
242   -#if (flash_EBIU_AMBCTL_WAT == 4)
243   -#define flash_EBIU_AMBCTL0_WAT B0WAT_4
244   -#endif
245   -#if (flash_EBIU_AMBCTL_WAT == 3)
246   -#define flash_EBIU_AMBCTL0_WAT B0WAT_3
247   -#endif
248   -#if (flash_EBIU_AMBCTL_WAT == 2)
249   -#define flash_EBIU_AMBCTL0_WAT B0WAT_2
250   -#endif
251   -#if (flash_EBIU_AMBCTL_WAT == 1)
252   -#define flash_EBIU_AMBCTL0_WAT B0WAT_1
253   -#endif
254   -
255   -#if (flash_EBIU_AMBCTL_RAT > 14)
256   -#define flash_EBIU_AMBCTL0_RAT B0RAT_15
257   -#endif
258   -#if (flash_EBIU_AMBCTL_RAT == 14)
259   -#define flash_EBIU_AMBCTL0_RAT B0RAT_14
260   -#endif
261   -#if (flash_EBIU_AMBCTL_RAT == 13)
262   -#define flash_EBIU_AMBCTL0_RAT B0RAT_13
263   -#endif
264   -#if (flash_EBIU_AMBCTL_RAT == 12)
265   -#define flash_EBIU_AMBCTL0_RAT B0RAT_12
266   -#endif
267   -#if (flash_EBIU_AMBCTL_RAT == 11)
268   -#define flash_EBIU_AMBCTL0_RAT B0RAT_11
269   -#endif
270   -#if (flash_EBIU_AMBCTL_RAT == 10)
271   -#define flash_EBIU_AMBCTL0_RAT B0RAT_10
272   -#endif
273   -#if (flash_EBIU_AMBCTL_RAT == 9)
274   -#define flash_EBIU_AMBCTL0_RAT B0RAT_9
275   -#endif
276   -#if (flash_EBIU_AMBCTL_RAT == 8)
277   -#define flash_EBIU_AMBCTL0_RAT B0RAT_8
278   -#endif
279   -#if (flash_EBIU_AMBCTL_RAT == 7)
280   -#define flash_EBIU_AMBCTL0_RAT B0RAT_7
281   -#endif
282   -#if (flash_EBIU_AMBCTL_RAT == 6)
283   -#define flash_EBIU_AMBCTL0_RAT B0RAT_6
284   -#endif
285   -#if (flash_EBIU_AMBCTL_RAT == 5)
286   -#define flash_EBIU_AMBCTL0_RAT B0RAT_5
287   -#endif
288   -#if (flash_EBIU_AMBCTL_RAT == 4)
289   -#define flash_EBIU_AMBCTL0_RAT B0RAT_4
290   -#endif
291   -#if (flash_EBIU_AMBCTL_RAT == 3)
292   -#define flash_EBIU_AMBCTL0_RAT B0RAT_3
293   -#endif
294   -#if (flash_EBIU_AMBCTL_RAT == 2)
295   -#define flash_EBIU_AMBCTL0_RAT B0RAT_2
296   -#endif
297   -#if (flash_EBIU_AMBCTL_RAT == 1)
298   -#define flash_EBIU_AMBCTL0_RAT B0RAT_1
299   -#endif
300   -
301   -#define flash_EBIU_AMBCTL0 \
302   - (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
303   - flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
arch/blackfin/mach-bf538/Makefile
Diff comments   View file @ 73feb5c
... ... @@ -2,7 +2,5 @@
2 2 # arch/blackfin/mach-bf538/Makefile
3 3 #
4 4  
5   -extra-y := head.o
6   -
7 5 obj-y := ints-priority.o dma.o
arch/blackfin/mach-bf538/head.S
View file @ 73feb5c
1   -/*
2   - * File: arch/blackfin/mach-bf538/head.S
3   - * Based on:
4   - * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5   - *
6   - * Created: 1998
7   - * Description: bf533 startup file
8   - *
9   - * Modified:
10   - * Copyright 2004-2006 Analog Devices Inc.
11   - *
12   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
13   - *
14   - * This program is free software; you can redistribute it and/or modify
15   - * it under the terms of the GNU General Public License as published by
16   - * the Free Software Foundation; either version 2 of the License, or
17   - * (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, see the file COPYING, or write
26   - * to the Free Software Foundation, Inc.,
27   - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28   - */
29   -
30   -#include <linux/linkage.h>
31   -#include <linux/init.h>
32   -#include <asm/blackfin.h>
33   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
34   -#include <asm/mach-common/clocks.h>
35   -#include <asm/mach/mem_init.h>
36   -#endif
37   -
38   -.section .l1.text
39   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
40   -ENTRY(_start_dma_code)
41   - p0.h = hi(SIC_IWR0);
42   - p0.l = lo(SIC_IWR0);
43   - r0.l = 0x1;
44   - r0.h = 0x0;
45   - [p0] = r0;
46   - SSYNC;
47   -
48   - /*
49   - * Set PLL_CTL
50   - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
51   - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
52   - * - [7] = output delay (add 200ps of delay to mem signals)
53   - * - [6] = input delay (add 200ps of input delay to mem signals)
54   - * - [5] = PDWN : 1=All Clocks off
55   - * - [3] = STOPCK : 1=Core Clock off
56   - * - [1] = PLL_OFF : 1=Disable Power to PLL
57   - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
58   - * all other bits set to zero
59   - */
60   -
61   - p0.h = hi(PLL_LOCKCNT);
62   - p0.l = lo(PLL_LOCKCNT);
63   - r0 = 0x300(Z);
64   - w[p0] = r0.l;
65   - ssync;
66   -
67   - P2.H = hi(EBIU_SDGCTL);
68   - P2.L = lo(EBIU_SDGCTL);
69   - R0 = [P2];
70   - BITSET (R0, 24);
71   - [P2] = R0;
72   - SSYNC;
73   -
74   - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
75   - r0 = r0 << 9; /* Shift it over, */
76   - r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
77   - r0 = r1 | r0;
78   - r1 = PLL_BYPASS; /* Bypass the PLL? */
79   - r1 = r1 << 8; /* Shift it over */
80   - r0 = r1 | r0; /* add them all together */
81   -#ifdef ANOMALY_05000265
82   - BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
83   -#endif
84   -
85   - p0.h = hi(PLL_CTL);
86   - p0.l = lo(PLL_CTL); /* Load the address */
87   - cli r2; /* Disable interrupts */
88   - ssync;
89   - w[p0] = r0.l; /* Set the value */
90   - idle; /* Wait for the PLL to stablize */
91   - sti r2; /* Enable interrupts */
92   -
93   -.Lcheck_again:
94   - p0.h = hi(PLL_STAT);
95   - p0.l = lo(PLL_STAT);
96   - R0 = W[P0](Z);
97   - CC = BITTST(R0,5);
98   - if ! CC jump .Lcheck_again;
99   -
100   - /* Configure SCLK & CCLK Dividers */
101   - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
102   - p0.h = hi(PLL_DIV);
103   - p0.l = lo(PLL_DIV);
104   - w[p0] = r0.l;
105   - ssync;
106   -
107   - p0.l = lo(EBIU_SDRRC);
108   - p0.h = hi(EBIU_SDRRC);
109   - r0 = mem_SDRRC;
110   - w[p0] = r0.l;
111   - ssync;
112   -
113   - P2.H = hi(EBIU_SDGCTL);
114   - P2.L = lo(EBIU_SDGCTL);
115   - R0 = [P2];
116   - BITCLR (R0, 24);
117   - p0.h = hi(EBIU_SDSTAT);
118   - p0.l = lo(EBIU_SDSTAT);
119   - r2.l = w[p0];
120   - cc = bittst(r2,3);
121   - if !cc jump .Lskip;
122   - NOP;
123   - BITSET (R0, 23);
124   -.Lskip:
125   - [P2] = R0;
126   - SSYNC;
127   -
128   - R0.L = lo(mem_SDGCTL);
129   - R0.H = hi(mem_SDGCTL);
130   - R1 = [p2];
131   - R1 = R1 | R0;
132   - [P2] = R1;
133   - SSYNC;
134   -
135   - RTS;
136   -ENDPROC(_start_dma_code)
137   -#endif /* CONFIG_BFIN_KERNEL_CLOCK */
arch/blackfin/mach-bf538/include/mach/mem_init.h
View file @ 73feb5c
1   -/*
2   - * File: include/asm-blackfin/mach-bf538/mem_init.h
3   - * Based on:
4   - * Author:
5   - *
6   - * Created:
7   - * Description:
8   - *
9   - * Rev:
10   - *
11   - * Modified:
12   - * Copyright 2004-2006 Analog Devices Inc.
13   - *
14   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
15   - *
16   - * This program is free software; you can redistribute it and/or modify
17   - * it under the terms of the GNU General Public License as published by
18   - * the Free Software Foundation; either version 2, or (at your option)
19   - * any later version.
20   - *
21   - * This program is distributed in the hope that it will be useful,
22   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
23   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24   - * GNU General Public License for more details.
25   - *
26   - * You should have received a copy of the GNU General Public License
27   - * along with this program; see the file COPYING.
28   - * If not, write to the Free Software Foundation,
29   - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30   - */
31   -
32   -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
33   -#if (CONFIG_SCLK_HZ > 119402985)
34   -#define SDRAM_tRP TRP_2
35   -#define SDRAM_tRP_num 2
36   -#define SDRAM_tRAS TRAS_7
37   -#define SDRAM_tRAS_num 7
38   -#define SDRAM_tRCD TRCD_2
39   -#define SDRAM_tWR TWR_2
40   -#endif
41   -#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
42   -#define SDRAM_tRP TRP_2
43   -#define SDRAM_tRP_num 2
44   -#define SDRAM_tRAS TRAS_6
45   -#define SDRAM_tRAS_num 6
46   -#define SDRAM_tRCD TRCD_2
47   -#define SDRAM_tWR TWR_2
48   -#endif
49   -#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
50   -#define SDRAM_tRP TRP_2
51   -#define SDRAM_tRP_num 2
52   -#define SDRAM_tRAS TRAS_5
53   -#define SDRAM_tRAS_num 5
54   -#define SDRAM_tRCD TRCD_2
55   -#define SDRAM_tWR TWR_2
56   -#endif
57   -#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
58   -#define SDRAM_tRP TRP_2
59   -#define SDRAM_tRP_num 2
60   -#define SDRAM_tRAS TRAS_4
61   -#define SDRAM_tRAS_num 4
62   -#define SDRAM_tRCD TRCD_2
63   -#define SDRAM_tWR TWR_2
64   -#endif
65   -#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
66   -#define SDRAM_tRP TRP_2
67   -#define SDRAM_tRP_num 2
68   -#define SDRAM_tRAS TRAS_3
69   -#define SDRAM_tRAS_num 3
70   -#define SDRAM_tRCD TRCD_2
71   -#define SDRAM_tWR TWR_2
72   -#endif
73   -#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
74   -#define SDRAM_tRP TRP_1
75   -#define SDRAM_tRP_num 1
76   -#define SDRAM_tRAS TRAS_4
77   -#define SDRAM_tRAS_num 3
78   -#define SDRAM_tRCD TRCD_1
79   -#define SDRAM_tWR TWR_2
80   -#endif
81   -#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
82   -#define SDRAM_tRP TRP_1
83   -#define SDRAM_tRP_num 1
84   -#define SDRAM_tRAS TRAS_3
85   -#define SDRAM_tRAS_num 3
86   -#define SDRAM_tRCD TRCD_1
87   -#define SDRAM_tWR TWR_2
88   -#endif
89   -#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
90   -#define SDRAM_tRP TRP_1
91   -#define SDRAM_tRP_num 1
92   -#define SDRAM_tRAS TRAS_2
93   -#define SDRAM_tRAS_num 2
94   -#define SDRAM_tRCD TRCD_1
95   -#define SDRAM_tWR TWR_2
96   -#endif
97   -#if (CONFIG_SCLK_HZ <= 29850746)
98   -#define SDRAM_tRP TRP_1
99   -#define SDRAM_tRP_num 1
100   -#define SDRAM_tRAS TRAS_1
101   -#define SDRAM_tRAS_num 1
102   -#define SDRAM_tRCD TRCD_1
103   -#define SDRAM_tWR TWR_2
104   -#endif
105   -#endif
106   -
107   -#if (CONFIG_MEM_MT48LC16M16A2TG_75)
108   - /*SDRAM INFORMATION: */
109   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
110   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
111   -#define SDRAM_CL CL_3
112   -#endif
113   -
114   -#if (CONFIG_MEM_MT48LC16M8A2TG_75)
115   - /*SDRAM INFORMATION: */
116   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
117   -#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
118   -#define SDRAM_CL CL_3
119   -#endif
120   -
121   -#if (CONFIG_MEM_MT48LC32M8A2_75)
122   - /*SDRAM INFORMATION: */
123   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
124   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
125   -#define SDRAM_CL CL_3
126   -#endif
127   -
128   -#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
129   - /*SDRAM INFORMATION: */
130   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
131   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
132   -#define SDRAM_CL CL_3
133   -#endif
134   -
135   -#if (CONFIG_MEM_GENERIC_BOARD)
136   - /*SDRAM INFORMATION: Modify this for your board */
137   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
138   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
139   -#define SDRAM_CL CL_3
140   -#endif
141   -
142   -/* Equation from section 17 (p17-46) of BF533 HRM */
143   -#define mem_SDRRC ((((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num))
144   -
145   -/* Enable SCLK Out */
146   -#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
147   -
148   -#if defined CONFIG_CLKIN_HALF
149   -#define CLKIN_HALF 1
150   -#else
151   -#define CLKIN_HALF 0
152   -#endif
153   -
154   -#if defined CONFIG_PLL_BYPASS
155   -#define PLL_BYPASS 1
156   -#else
157   -#define PLL_BYPASS 0
158   -#endif
159   -
160   -/***************************************Currently Not Being Used *********************************/
161   -#define flash_EBIU_AMBCTL_WAT (((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1)
162   -#define flash_EBIU_AMBCTL_RAT (((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1)
163   -#define flash_EBIU_AMBCTL_HT (((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ)))
164   -#define flash_EBIU_AMBCTL_ST (((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1)
165   -#define flash_EBIU_AMBCTL_TT (((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1)
166   -
167   -#if (flash_EBIU_AMBCTL_TT > 3)
168   -#define flash_EBIU_AMBCTL0_TT B0TT_4
169   -#endif
170   -#if (flash_EBIU_AMBCTL_TT == 3)
171   -#define flash_EBIU_AMBCTL0_TT B0TT_3
172   -#endif
173   -#if (flash_EBIU_AMBCTL_TT == 2)
174   -#define flash_EBIU_AMBCTL0_TT B0TT_2
175   -#endif
176   -#if (flash_EBIU_AMBCTL_TT < 2)
177   -#define flash_EBIU_AMBCTL0_TT B0TT_1
178   -#endif
179   -
180   -#if (flash_EBIU_AMBCTL_ST > 3)
181   -#define flash_EBIU_AMBCTL0_ST B0ST_4
182   -#endif
183   -#if (flash_EBIU_AMBCTL_ST == 3)
184   -#define flash_EBIU_AMBCTL0_ST B0ST_3
185   -#endif
186   -#if (flash_EBIU_AMBCTL_ST == 2)
187   -#define flash_EBIU_AMBCTL0_ST B0ST_2
188   -#endif
189   -#if (flash_EBIU_AMBCTL_ST < 2)
190   -#define flash_EBIU_AMBCTL0_ST B0ST_1
191   -#endif
192   -
193   -#if (flash_EBIU_AMBCTL_HT > 2)
194   -#define flash_EBIU_AMBCTL0_HT B0HT_3
195   -#endif
196   -#if (flash_EBIU_AMBCTL_HT == 2)
197   -#define flash_EBIU_AMBCTL0_HT B0HT_2
198   -#endif
199   -#if (flash_EBIU_AMBCTL_HT == 1)
200   -#define flash_EBIU_AMBCTL0_HT B0HT_1
201   -#endif
202   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
203   -#define flash_EBIU_AMBCTL0_HT B0HT_0
204   -#endif
205   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
206   -#define flash_EBIU_AMBCTL0_HT B0HT_1
207   -#endif
208   -
209   -#if (flash_EBIU_AMBCTL_WAT > 14)
210   -#define flash_EBIU_AMBCTL0_WAT B0WAT_15
211   -#endif
212   -#if (flash_EBIU_AMBCTL_WAT == 14)
213   -#define flash_EBIU_AMBCTL0_WAT B0WAT_14
214   -#endif
215   -#if (flash_EBIU_AMBCTL_WAT == 13)
216   -#define flash_EBIU_AMBCTL0_WAT B0WAT_13
217   -#endif
218   -#if (flash_EBIU_AMBCTL_WAT == 12)
219   -#define flash_EBIU_AMBCTL0_WAT B0WAT_12
220   -#endif
221   -#if (flash_EBIU_AMBCTL_WAT == 11)
222   -#define flash_EBIU_AMBCTL0_WAT B0WAT_11
223   -#endif
224   -#if (flash_EBIU_AMBCTL_WAT == 10)
225   -#define flash_EBIU_AMBCTL0_WAT B0WAT_10
226   -#endif
227   -#if (flash_EBIU_AMBCTL_WAT == 9)
228   -#define flash_EBIU_AMBCTL0_WAT B0WAT_9
229   -#endif
230   -#if (flash_EBIU_AMBCTL_WAT == 8)
231   -#define flash_EBIU_AMBCTL0_WAT B0WAT_8
232   -#endif
233   -#if (flash_EBIU_AMBCTL_WAT == 7)
234   -#define flash_EBIU_AMBCTL0_WAT B0WAT_7
235   -#endif
236   -#if (flash_EBIU_AMBCTL_WAT == 6)
237   -#define flash_EBIU_AMBCTL0_WAT B0WAT_6
238   -#endif
239   -#if (flash_EBIU_AMBCTL_WAT == 5)
240   -#define flash_EBIU_AMBCTL0_WAT B0WAT_5
241   -#endif
242   -#if (flash_EBIU_AMBCTL_WAT == 4)
243   -#define flash_EBIU_AMBCTL0_WAT B0WAT_4
244   -#endif
245   -#if (flash_EBIU_AMBCTL_WAT == 3)
246   -#define flash_EBIU_AMBCTL0_WAT B0WAT_3
247   -#endif
248   -#if (flash_EBIU_AMBCTL_WAT == 2)
249   -#define flash_EBIU_AMBCTL0_WAT B0WAT_2
250   -#endif
251   -#if (flash_EBIU_AMBCTL_WAT == 1)
252   -#define flash_EBIU_AMBCTL0_WAT B0WAT_1
253   -#endif
254   -
255   -#if (flash_EBIU_AMBCTL_RAT > 14)
256   -#define flash_EBIU_AMBCTL0_RAT B0RAT_15
257   -#endif
258   -#if (flash_EBIU_AMBCTL_RAT == 14)
259   -#define flash_EBIU_AMBCTL0_RAT B0RAT_14
260   -#endif
261   -#if (flash_EBIU_AMBCTL_RAT == 13)
262   -#define flash_EBIU_AMBCTL0_RAT B0RAT_13
263   -#endif
264   -#if (flash_EBIU_AMBCTL_RAT == 12)
265   -#define flash_EBIU_AMBCTL0_RAT B0RAT_12
266   -#endif
267   -#if (flash_EBIU_AMBCTL_RAT == 11)
268   -#define flash_EBIU_AMBCTL0_RAT B0RAT_11
269   -#endif
270   -#if (flash_EBIU_AMBCTL_RAT == 10)
271   -#define flash_EBIU_AMBCTL0_RAT B0RAT_10
272   -#endif
273   -#if (flash_EBIU_AMBCTL_RAT == 9)
274   -#define flash_EBIU_AMBCTL0_RAT B0RAT_9
275   -#endif
276   -#if (flash_EBIU_AMBCTL_RAT == 8)
277   -#define flash_EBIU_AMBCTL0_RAT B0RAT_8
278   -#endif
279   -#if (flash_EBIU_AMBCTL_RAT == 7)
280   -#define flash_EBIU_AMBCTL0_RAT B0RAT_7
281   -#endif
282   -#if (flash_EBIU_AMBCTL_RAT == 6)
283   -#define flash_EBIU_AMBCTL0_RAT B0RAT_6
284   -#endif
285   -#if (flash_EBIU_AMBCTL_RAT == 5)
286   -#define flash_EBIU_AMBCTL0_RAT B0RAT_5
287   -#endif
288   -#if (flash_EBIU_AMBCTL_RAT == 4)
289   -#define flash_EBIU_AMBCTL0_RAT B0RAT_4
290   -#endif
291   -#if (flash_EBIU_AMBCTL_RAT == 3)
292   -#define flash_EBIU_AMBCTL0_RAT B0RAT_3
293   -#endif
294   -#if (flash_EBIU_AMBCTL_RAT == 2)
295   -#define flash_EBIU_AMBCTL0_RAT B0RAT_2
296   -#endif
297   -#if (flash_EBIU_AMBCTL_RAT == 1)
298   -#define flash_EBIU_AMBCTL0_RAT B0RAT_1
299   -#endif
300   -
301   -#define flash_EBIU_AMBCTL0 \
302   - (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
303   - flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
arch/blackfin/mach-bf548/Makefile
Diff comments   View file @ 73feb5c
... ... @@ -2,7 +2,5 @@
2 2 # arch/blackfin/mach-bf537/Makefile
3 3 #
4 4  
5   -extra-y := head.o
6   -
7 5 obj-y := ints-priority.o dma.o
arch/blackfin/mach-bf548/head.S
View file @ 73feb5c
1   -/*
2   - * File: arch/blackfin/mach-bf548/head.S
3   - * Based on: arch/blackfin/mach-bf537/head.S
4   - * Author: Jeff Dionne <jeff@uclinux.org> COPYRIGHT 1998 D. Jeff Dionne
5   - *
6   - * Created: 1998
7   - * Description: Startup code for Blackfin BF548
8   - *
9   - * Modified:
10   - * Copyright 2004-2007 Analog Devices Inc.
11   - *
12   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
13   - *
14   - * This program is free software; you can redistribute it and/or modify
15   - * it under the terms of the GNU General Public License as published by
16   - * the Free Software Foundation; either version 2 of the License, or
17   - * (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, see the file COPYING, or write
26   - * to the Free Software Foundation, Inc.,
27   - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28   - */
29   -
30   -#include <linux/linkage.h>
31   -#include <linux/init.h>
32   -#include <asm/blackfin.h>
33   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
34   -#include <asm/clocks.h>
35   -#include <mach/mem_init.h>
36   -#endif
37   -
38   -.section .l1.text
39   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
40   -ENTRY(_start_dma_code)
41   -
42   - /* Enable PHY CLK buffer output */
43   - p0.h = hi(VR_CTL);
44   - p0.l = lo(VR_CTL);
45   - r0.l = w[p0];
46   - bitset(r0, 14);
47   - w[p0] = r0.l;
48   - ssync;
49   -
50   - p0.h = hi(SIC_IWR0);
51   - p0.l = lo(SIC_IWR0);
52   - r0.l = 0x1;
53   - r0.h = 0x0;
54   - [p0] = r0;
55   - SSYNC;
56   -
57   - /*
58   - * Set PLL_CTL
59   - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
60   - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
61   - * - [7] = output delay (add 200ps of delay to mem signals)
62   - * - [6] = input delay (add 200ps of input delay to mem signals)
63   - * - [5] = PDWN : 1=All Clocks off
64   - * - [3] = STOPCK : 1=Core Clock off
65   - * - [1] = PLL_OFF : 1=Disable Power to PLL
66   - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
67   - * all other bits set to zero
68   - */
69   -
70   - p0.h = hi(PLL_LOCKCNT);
71   - p0.l = lo(PLL_LOCKCNT);
72   - r0 = 0x300(Z);
73   - w[p0] = r0.l;
74   - ssync;
75   -
76   - /* enable self refresh via SRREQ */
77   - P2.H = hi(EBIU_RSTCTL);
78   - P2.L = lo(EBIU_RSTCTL);
79   - R0 = [P2];
80   - BITSET (R0, 3);
81   - [P2] = R0;
82   - SSYNC;
83   -
84   - /* wait for SRACK bit to be set */
85   -.LSRR_MODE:
86   - R0 = [P2];
87   - CC = BITTST(R0, 4);
88   - if !CC JUMP .LSRR_MODE;
89   -
90   - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
91   - r0 = r0 << 9; /* Shift it over, */
92   - r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
93   - r0 = r1 | r0;
94   - r1 = PLL_BYPASS; /* Bypass the PLL? */
95   - r1 = r1 << 8; /* Shift it over */
96   - r0 = r1 | r0; /* add them all together */
97   -#ifdef ANOMALY_05000265
98   - BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
99   -#endif
100   -
101   - p0.h = hi(PLL_CTL);
102   - p0.l = lo(PLL_CTL); /* Load the address */
103   - cli r2; /* Disable interrupts */
104   - ssync;
105   - w[p0] = r0.l; /* Set the value */
106   - idle; /* Wait for the PLL to stablize */
107   - sti r2; /* Enable interrupts */
108   -
109   -.Lcheck_again:
110   - p0.h = hi(PLL_STAT);
111   - p0.l = lo(PLL_STAT);
112   - R0 = W[P0](Z);
113   - CC = BITTST(R0,5);
114   - if ! CC jump .Lcheck_again;
115   -
116   - /* Configure SCLK & CCLK Dividers */
117   - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
118   - p0.h = hi(PLL_DIV);
119   - p0.l = lo(PLL_DIV);
120   - w[p0] = r0.l;
121   - ssync;
122   -
123   - /* disable self refresh by clearing SRREQ */
124   - P2.H = hi(EBIU_RSTCTL);
125   - P2.L = lo(EBIU_RSTCTL);
126   - R0 = [P2];
127   - CC = BITTST(R0, 0);
128   - if CC jump .Lskipddrrst;
129   - BITSET (R0, 0);
130   -.Lskipddrrst:
131   - BITCLR (R0, 3);
132   - [P2] = R0;
133   - SSYNC;
134   -
135   - p0.l = lo(EBIU_DDRCTL0);
136   - p0.h = hi(EBIU_DDRCTL0);
137   - r0.l = lo(mem_DDRCTL0);
138   - r0.h = hi(mem_DDRCTL0);
139   - [p0] = r0;
140   - ssync;
141   -
142   - p0.l = lo(EBIU_DDRCTL1);
143   - p0.h = hi(EBIU_DDRCTL1);
144   - r0.l = lo(mem_DDRCTL1);
145   - r0.h = hi(mem_DDRCTL1);
146   - [p0] = r0;
147   - ssync;
148   -
149   - p0.l = lo(EBIU_DDRCTL2);
150   - p0.h = hi(EBIU_DDRCTL2);
151   - r0.l = lo(mem_DDRCTL2);
152   - r0.h = hi(mem_DDRCTL2);
153   - [p0] = r0;
154   - ssync;
155   -
156   - RTS;
157   -ENDPROC(_start_dma_code)
158   -#endif /* CONFIG_BFIN_KERNEL_CLOCK */
arch/blackfin/mach-bf548/include/mach/mem_init.h
View file @ 73feb5c
1   -/*
2   - * File: include/asm-blackfin/mach-bf548/mem_init.h
3   - * Based on:
4   - * Author:
5   - *
6   - * Created:
7   - * Description:
8   - *
9   - * Rev:
10   - *
11   - * Modified:
12   - * Copyright 2004-2006 Analog Devices Inc.
13   - *
14   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
15   - *
16   - * This program is free software; you can redistribute it and/or modify
17   - * it under the terms of the GNU General Public License as published by
18   - * the Free Software Foundation; either version 2, or (at your option)
19   - * any later version.
20   - *
21   - * This program is distributed in the hope that it will be useful,
22   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
23   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24   - * GNU General Public License for more details.
25   - *
26   - * You should have received a copy of the GNU General Public License
27   - * along with this program; see the file COPYING.
28   - * If not, write to the Free Software Foundation,
29   - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30   - */
31   -#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
32   -#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
33   -#define DDR_CLK_HZ(x) (1000*1000*1000/x)
34   -
35   -#if (CONFIG_MEM_MT46V32M16_6T)
36   -#define DDR_SIZE DEVSZ_512
37   -#define DDR_WIDTH DEVWD_16
38   -#define DDR_MAX_tCK 13
39   -
40   -#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(60))
41   -#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(42))
42   -#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
43   -#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(72))
44   -#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
45   -
46   -#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
47   -#define DDR_tWTR DDR_TWTR(1)
48   -#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(12))
49   -#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
50   -#endif
51   -
52   -#if (CONFIG_MEM_MT46V32M16_5B)
53   -#define DDR_SIZE DEVSZ_512
54   -#define DDR_WIDTH DEVWD_16
55   -#define DDR_MAX_tCK 13
56   -
57   -#define DDR_tRC DDR_TRC(MIN_DDR_SCLK(55))
58   -#define DDR_tRAS DDR_TRAS(MIN_DDR_SCLK(40))
59   -#define DDR_tRP DDR_TRP(MIN_DDR_SCLK(15))
60   -#define DDR_tRFC DDR_TRFC(MIN_DDR_SCLK(70))
61   -#define DDR_tREFI DDR_TREFI(MAX_DDR_SCLK(7800))
62   -
63   -#define DDR_tRCD DDR_TRCD(MIN_DDR_SCLK(15))
64   -#define DDR_tWTR DDR_TWTR(2)
65   -#define DDR_tMRD DDR_TMRD(MIN_DDR_SCLK(10))
66   -#define DDR_tWR DDR_TWR(MIN_DDR_SCLK(15))
67   -#endif
68   -
69   -#if (CONFIG_MEM_GENERIC_BOARD)
70   -#define DDR_SIZE DEVSZ_512
71   -#define DDR_WIDTH DEVWD_16
72   -#define DDR_MAX_tCK 13
73   -
74   -#define DDR_tRCD DDR_TRCD(3)
75   -#define DDR_tWTR DDR_TWTR(2)
76   -#define DDR_tWR DDR_TWR(2)
77   -#define DDR_tMRD DDR_TMRD(2)
78   -#define DDR_tRP DDR_TRP(3)
79   -#define DDR_tRAS DDR_TRAS(7)
80   -#define DDR_tRC DDR_TRC(10)
81   -#define DDR_tRFC DDR_TRFC(12)
82   -#define DDR_tREFI DDR_TREFI(1288)
83   -#endif
84   -
85   -#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
86   -# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
87   -#elif(CONFIG_SCLK_HZ <= 133333333)
88   -# define DDR_CL CL_2
89   -#else
90   -# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
91   -#endif
92   -
93   -
94   -#define mem_DDRCTL0 (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
95   -#define mem_DDRCTL1 (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
96   - | DDR_tMRD | DDR_tWR | DDR_tRCD)
97   -#define mem_DDRCTL2 DDR_CL
98   -
99   -
100   -#if defined CONFIG_CLKIN_HALF
101   -#define CLKIN_HALF 1
102   -#else
103   -#define CLKIN_HALF 0
104   -#endif
105   -
106   -#if defined CONFIG_PLL_BYPASS
107   -#define PLL_BYPASS 1
108   -#else
109   -#define PLL_BYPASS 0
110   -#endif
111   -
112   -/***************************************Currently Not Being Used *********************************/
113   -#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
114   -#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
115   -#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
116   -#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
117   -#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
118   -
119   -#if (flash_EBIU_AMBCTL_TT > 3)
120   -#define flash_EBIU_AMBCTL0_TT B0TT_4
121   -#endif
122   -#if (flash_EBIU_AMBCTL_TT == 3)
123   -#define flash_EBIU_AMBCTL0_TT B0TT_3
124   -#endif
125   -#if (flash_EBIU_AMBCTL_TT == 2)
126   -#define flash_EBIU_AMBCTL0_TT B0TT_2
127   -#endif
128   -#if (flash_EBIU_AMBCTL_TT < 2)
129   -#define flash_EBIU_AMBCTL0_TT B0TT_1
130   -#endif
131   -
132   -#if (flash_EBIU_AMBCTL_ST > 3)
133   -#define flash_EBIU_AMBCTL0_ST B0ST_4
134   -#endif
135   -#if (flash_EBIU_AMBCTL_ST == 3)
136   -#define flash_EBIU_AMBCTL0_ST B0ST_3
137   -#endif
138   -#if (flash_EBIU_AMBCTL_ST == 2)
139   -#define flash_EBIU_AMBCTL0_ST B0ST_2
140   -#endif
141   -#if (flash_EBIU_AMBCTL_ST < 2)
142   -#define flash_EBIU_AMBCTL0_ST B0ST_1
143   -#endif
144   -
145   -#if (flash_EBIU_AMBCTL_HT > 2)
146   -#define flash_EBIU_AMBCTL0_HT B0HT_3
147   -#endif
148   -#if (flash_EBIU_AMBCTL_HT == 2)
149   -#define flash_EBIU_AMBCTL0_HT B0HT_2
150   -#endif
151   -#if (flash_EBIU_AMBCTL_HT == 1)
152   -#define flash_EBIU_AMBCTL0_HT B0HT_1
153   -#endif
154   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
155   -#define flash_EBIU_AMBCTL0_HT B0HT_0
156   -#endif
157   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
158   -#define flash_EBIU_AMBCTL0_HT B0HT_1
159   -#endif
160   -
161   -#if (flash_EBIU_AMBCTL_WAT > 14)
162   -#define flash_EBIU_AMBCTL0_WAT B0WAT_15
163   -#endif
164   -#if (flash_EBIU_AMBCTL_WAT == 14)
165   -#define flash_EBIU_AMBCTL0_WAT B0WAT_14
166   -#endif
167   -#if (flash_EBIU_AMBCTL_WAT == 13)
168   -#define flash_EBIU_AMBCTL0_WAT B0WAT_13
169   -#endif
170   -#if (flash_EBIU_AMBCTL_WAT == 12)
171   -#define flash_EBIU_AMBCTL0_WAT B0WAT_12
172   -#endif
173   -#if (flash_EBIU_AMBCTL_WAT == 11)
174   -#define flash_EBIU_AMBCTL0_WAT B0WAT_11
175   -#endif
176   -#if (flash_EBIU_AMBCTL_WAT == 10)
177   -#define flash_EBIU_AMBCTL0_WAT B0WAT_10
178   -#endif
179   -#if (flash_EBIU_AMBCTL_WAT == 9)
180   -#define flash_EBIU_AMBCTL0_WAT B0WAT_9
181   -#endif
182   -#if (flash_EBIU_AMBCTL_WAT == 8)
183   -#define flash_EBIU_AMBCTL0_WAT B0WAT_8
184   -#endif
185   -#if (flash_EBIU_AMBCTL_WAT == 7)
186   -#define flash_EBIU_AMBCTL0_WAT B0WAT_7
187   -#endif
188   -#if (flash_EBIU_AMBCTL_WAT == 6)
189   -#define flash_EBIU_AMBCTL0_WAT B0WAT_6
190   -#endif
191   -#if (flash_EBIU_AMBCTL_WAT == 5)
192   -#define flash_EBIU_AMBCTL0_WAT B0WAT_5
193   -#endif
194   -#if (flash_EBIU_AMBCTL_WAT == 4)
195   -#define flash_EBIU_AMBCTL0_WAT B0WAT_4
196   -#endif
197   -#if (flash_EBIU_AMBCTL_WAT == 3)
198   -#define flash_EBIU_AMBCTL0_WAT B0WAT_3
199   -#endif
200   -#if (flash_EBIU_AMBCTL_WAT == 2)
201   -#define flash_EBIU_AMBCTL0_WAT B0WAT_2
202   -#endif
203   -#if (flash_EBIU_AMBCTL_WAT == 1)
204   -#define flash_EBIU_AMBCTL0_WAT B0WAT_1
205   -#endif
206   -
207   -#if (flash_EBIU_AMBCTL_RAT > 14)
208   -#define flash_EBIU_AMBCTL0_RAT B0RAT_15
209   -#endif
210   -#if (flash_EBIU_AMBCTL_RAT == 14)
211   -#define flash_EBIU_AMBCTL0_RAT B0RAT_14
212   -#endif
213   -#if (flash_EBIU_AMBCTL_RAT == 13)
214   -#define flash_EBIU_AMBCTL0_RAT B0RAT_13
215   -#endif
216   -#if (flash_EBIU_AMBCTL_RAT == 12)
217   -#define flash_EBIU_AMBCTL0_RAT B0RAT_12
218   -#endif
219   -#if (flash_EBIU_AMBCTL_RAT == 11)
220   -#define flash_EBIU_AMBCTL0_RAT B0RAT_11
221   -#endif
222   -#if (flash_EBIU_AMBCTL_RAT == 10)
223   -#define flash_EBIU_AMBCTL0_RAT B0RAT_10
224   -#endif
225   -#if (flash_EBIU_AMBCTL_RAT == 9)
226   -#define flash_EBIU_AMBCTL0_RAT B0RAT_9
227   -#endif
228   -#if (flash_EBIU_AMBCTL_RAT == 8)
229   -#define flash_EBIU_AMBCTL0_RAT B0RAT_8
230   -#endif
231   -#if (flash_EBIU_AMBCTL_RAT == 7)
232   -#define flash_EBIU_AMBCTL0_RAT B0RAT_7
233   -#endif
234   -#if (flash_EBIU_AMBCTL_RAT == 6)
235   -#define flash_EBIU_AMBCTL0_RAT B0RAT_6
236   -#endif
237   -#if (flash_EBIU_AMBCTL_RAT == 5)
238   -#define flash_EBIU_AMBCTL0_RAT B0RAT_5
239   -#endif
240   -#if (flash_EBIU_AMBCTL_RAT == 4)
241   -#define flash_EBIU_AMBCTL0_RAT B0RAT_4
242   -#endif
243   -#if (flash_EBIU_AMBCTL_RAT == 3)
244   -#define flash_EBIU_AMBCTL0_RAT B0RAT_3
245   -#endif
246   -#if (flash_EBIU_AMBCTL_RAT == 2)
247   -#define flash_EBIU_AMBCTL0_RAT B0RAT_2
248   -#endif
249   -#if (flash_EBIU_AMBCTL_RAT == 1)
250   -#define flash_EBIU_AMBCTL0_RAT B0RAT_1
251   -#endif
252   -
253   -#define flash_EBIU_AMBCTL0 \
254   - (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
255   - flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
arch/blackfin/mach-bf561/Makefile
Diff comments   View file @ 73feb5c
... ... @@ -2,8 +2,6 @@
2 2 # arch/blackfin/mach-bf561/Makefile
3 3 #
4 4  
5   -extra-y := head.o
6   -
7 5 obj-y := ints-priority.o dma.o
8 6  
9 7 obj-$(CONFIG_BF561_COREB) += coreb.o
arch/blackfin/mach-bf561/head.S
View file @ 73feb5c
1   -/*
2   - * File: arch/blackfin/mach-bf561/head.S
3   - * Based on: arch/blackfin/mach-bf533/head.S
4   - * Author:
5   - *
6   - * Created:
7   - * Description: BF561 startup file
8   - *
9   - * Modified:
10   - * Copyright 2004-2006 Analog Devices Inc.
11   - *
12   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
13   - *
14   - * This program is free software; you can redistribute it and/or modify
15   - * it under the terms of the GNU General Public License as published by
16   - * the Free Software Foundation; either version 2 of the License, or
17   - * (at your option) any later version.
18   - *
19   - * This program is distributed in the hope that it will be useful,
20   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
21   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22   - * GNU General Public License for more details.
23   - *
24   - * You should have received a copy of the GNU General Public License
25   - * along with this program; if not, see the file COPYING, or write
26   - * to the Free Software Foundation, Inc.,
27   - * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
28   - */
29   -
30   -#include <linux/linkage.h>
31   -#include <linux/init.h>
32   -#include <asm/blackfin.h>
33   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
34   -#include <asm/clocks.h>
35   -#include <mach/mem_init.h>
36   -#endif
37   -
38   -.section .l1.text
39   -#ifdef CONFIG_BFIN_KERNEL_CLOCK
40   -ENTRY(_start_dma_code)
41   - p0.h = hi(SICA_IWR0);
42   - p0.l = lo(SICA_IWR0);
43   - r0.l = 0x1;
44   - [p0] = r0;
45   - SSYNC;
46   -
47   - /*
48   - * Set PLL_CTL
49   - * - [14:09] = MSEL[5:0] : CLKIN / VCO multiplication factors
50   - * - [8] = BYPASS : BYPASS the PLL, run CLKIN into CCLK/SCLK
51   - * - [7] = output delay (add 200ps of delay to mem signals)
52   - * - [6] = input delay (add 200ps of input delay to mem signals)
53   - * - [5] = PDWN : 1=All Clocks off
54   - * - [3] = STOPCK : 1=Core Clock off
55   - * - [1] = PLL_OFF : 1=Disable Power to PLL
56   - * - [0] = DF : 1=Pass CLKIN/2 to PLL / 0=Pass CLKIN to PLL
57   - * all other bits set to zero
58   - */
59   -
60   - p0.h = hi(PLL_LOCKCNT);
61   - p0.l = lo(PLL_LOCKCNT);
62   - r0 = 0x300(Z);
63   - w[p0] = r0.l;
64   - ssync;
65   -
66   - P2.H = hi(EBIU_SDGCTL);
67   - P2.L = lo(EBIU_SDGCTL);
68   - R0 = [P2];
69   - BITSET (R0, 24);
70   - [P2] = R0;
71   - SSYNC;
72   -
73   - r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
74   - r0 = r0 << 9; /* Shift it over, */
75   - r1 = CLKIN_HALF; /* Do we need to divide CLKIN by 2?*/
76   - r0 = r1 | r0;
77   - r1 = PLL_BYPASS; /* Bypass the PLL? */
78   - r1 = r1 << 8; /* Shift it over */
79   - r0 = r1 | r0; /* add them all together */
80   -#ifdef ANOMALY_05000265
81   - BITSET(r0, 15); /* Add 250 mV of hysteresis to SPORT input pins */
82   -#endif
83   -
84   - p0.h = hi(PLL_CTL);
85   - p0.l = lo(PLL_CTL); /* Load the address */
86   - cli r2; /* Disable interrupts */
87   - ssync;
88   - w[p0] = r0.l; /* Set the value */
89   - idle; /* Wait for the PLL to stablize */
90   - sti r2; /* Enable interrupts */
91   -
92   -.Lcheck_again:
93   - p0.h = hi(PLL_STAT);
94   - p0.l = lo(PLL_STAT);
95   - R0 = W[P0](Z);
96   - CC = BITTST(R0,5);
97   - if ! CC jump .Lcheck_again;
98   -
99   - /* Configure SCLK & CCLK Dividers */
100   - r0 = (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
101   - p0.h = hi(PLL_DIV);
102   - p0.l = lo(PLL_DIV);
103   - w[p0] = r0.l;
104   - ssync;
105   -
106   - p0.l = lo(EBIU_SDRRC);
107   - p0.h = hi(EBIU_SDRRC);
108   - r0 = mem_SDRRC;
109   - w[p0] = r0.l;
110   - ssync;
111   -
112   - P2.H = hi(EBIU_SDGCTL);
113   - P2.L = lo(EBIU_SDGCTL);
114   - R0 = [P2];
115   - BITCLR (R0, 24);
116   - p0.h = hi(EBIU_SDSTAT);
117   - p0.l = lo(EBIU_SDSTAT);
118   - r2.l = w[p0];
119   - cc = bittst(r2,3);
120   - if !cc jump .Lskip;
121   - NOP;
122   - BITSET (R0, 23);
123   -.Lskip:
124   - [P2] = R0;
125   - SSYNC;
126   -
127   - R0.L = lo(mem_SDGCTL);
128   - R0.H = hi(mem_SDGCTL);
129   - R1 = [p2];
130   - R1 = R1 | R0;
131   - [P2] = R1;
132   - SSYNC;
133   -
134   - RTS;
135   -ENDPROC(_start_dma_code)
136   -#endif /* CONFIG_BFIN_KERNEL_CLOCK */
arch/blackfin/mach-bf561/include/mach/mem_init.h
View file @ 73feb5c
1   -/*
2   - * File: include/asm-blackfin/mach-bf561/mem_init.h
3   - * Based on:
4   - * Author:
5   - *
6   - * Created:
7   - * Description:
8   - *
9   - * Rev:
10   - *
11   - * Modified:
12   - *
13   - * Bugs: Enter bugs at http://blackfin.uclinux.org/
14   - *
15   - * This program is free software; you can redistribute it and/or modify
16   - * it under the terms of the GNU General Public License as published by
17   - * the Free Software Foundation; either version 2, or (at your option)
18   - * any later version.
19   - *
20   - * This program is distributed in the hope that it will be useful,
21   - * but WITHOUT ANY WARRANTY; without even the implied warranty of
22   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23   - * GNU General Public License for more details.
24   - *
25   - * You should have received a copy of the GNU General Public License
26   - * along with this program; see the file COPYING.
27   - * If not, write to the Free Software Foundation,
28   - * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
29   - */
30   -
31   -#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
32   -#if (CONFIG_SCLK_HZ > 119402985)
33   -#define SDRAM_tRP TRP_2
34   -#define SDRAM_tRP_num 2
35   -#define SDRAM_tRAS TRAS_7
36   -#define SDRAM_tRAS_num 7
37   -#define SDRAM_tRCD TRCD_2
38   -#define SDRAM_tWR TWR_2
39   -#endif
40   -#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
41   -#define SDRAM_tRP TRP_2
42   -#define SDRAM_tRP_num 2
43   -#define SDRAM_tRAS TRAS_6
44   -#define SDRAM_tRAS_num 6
45   -#define SDRAM_tRCD TRCD_2
46   -#define SDRAM_tWR TWR_2
47   -#endif
48   -#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
49   -#define SDRAM_tRP TRP_2
50   -#define SDRAM_tRP_num 2
51   -#define SDRAM_tRAS TRAS_5
52   -#define SDRAM_tRAS_num 5
53   -#define SDRAM_tRCD TRCD_2
54   -#define SDRAM_tWR TWR_2
55   -#endif
56   -#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
57   -#define SDRAM_tRP TRP_2
58   -#define SDRAM_tRP_num 2
59   -#define SDRAM_tRAS TRAS_4
60   -#define SDRAM_tRAS_num 4
61   -#define SDRAM_tRCD TRCD_2
62   -#define SDRAM_tWR TWR_2
63   -#endif
64   -#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
65   -#define SDRAM_tRP TRP_2
66   -#define SDRAM_tRP_num 2
67   -#define SDRAM_tRAS TRAS_3
68   -#define SDRAM_tRAS_num 3
69   -#define SDRAM_tRCD TRCD_2
70   -#define SDRAM_tWR TWR_2
71   -#endif
72   -#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
73   -#define SDRAM_tRP TRP_1
74   -#define SDRAM_tRP_num 1
75   -#define SDRAM_tRAS TRAS_4
76   -#define SDRAM_tRAS_num 3
77   -#define SDRAM_tRCD TRCD_1
78   -#define SDRAM_tWR TWR_2
79   -#endif
80   -#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
81   -#define SDRAM_tRP TRP_1
82   -#define SDRAM_tRP_num 1
83   -#define SDRAM_tRAS TRAS_3
84   -#define SDRAM_tRAS_num 3
85   -#define SDRAM_tRCD TRCD_1
86   -#define SDRAM_tWR TWR_2
87   -#endif
88   -#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
89   -#define SDRAM_tRP TRP_1
90   -#define SDRAM_tRP_num 1
91   -#define SDRAM_tRAS TRAS_2
92   -#define SDRAM_tRAS_num 2
93   -#define SDRAM_tRCD TRCD_1
94   -#define SDRAM_tWR TWR_2
95   -#endif
96   -#if (CONFIG_SCLK_HZ <= 29850746)
97   -#define SDRAM_tRP TRP_1
98   -#define SDRAM_tRP_num 1
99   -#define SDRAM_tRAS TRAS_1
100   -#define SDRAM_tRAS_num 1
101   -#define SDRAM_tRCD TRCD_1
102   -#define SDRAM_tWR TWR_2
103   -#endif
104   -#endif
105   -
106   -#if (CONFIG_MEM_MT48LC16M16A2TG_75)
107   - /*SDRAM INFORMATION: */
108   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
109   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
110   -#define SDRAM_CL CL_3
111   -#endif
112   -
113   -#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
114   - /*SDRAM INFORMATION: */
115   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
116   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
117   -#define SDRAM_CL CL_3
118   -#endif
119   -
120   -#if (CONFIG_MEM_MT48LC8M32B2B5_7)
121   - /*SDRAM INFORMATION: */
122   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
123   -#define SDRAM_NRA 4096 /* Number of row addresses in SDRAM */
124   -#define SDRAM_CL CL_3
125   -#endif
126   -
127   -#if (CONFIG_MEM_GENERIC_BOARD)
128   - /*SDRAM INFORMATION: Modify this for your board */
129   -#define SDRAM_Tref 64 /* Refresh period in milliseconds */
130   -#define SDRAM_NRA 8192 /* Number of row addresses in SDRAM */
131   -#define SDRAM_CL CL_3
132   -#endif
133   -
134   -/* Equation from section 17 (p17-46) of BF533 HRM */
135   -#define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
136   -
137   -/* Enable SCLK Out */
138   -#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
139   -
140   -#if defined CONFIG_CLKIN_HALF
141   -#define CLKIN_HALF 1
142   -#else
143   -#define CLKIN_HALF 0
144   -#endif
145   -
146   -#if defined CONFIG_PLL_BYPASS
147   -#define PLL_BYPASS 1
148   -#else
149   -#define PLL_BYPASS 0
150   -#endif
151   -
152   -/***************************************Currently Not Being Used *********************************/
153   -#define flash_EBIU_AMBCTL_WAT ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
154   -#define flash_EBIU_AMBCTL_RAT ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
155   -#define flash_EBIU_AMBCTL_HT ((CONFIG_FLASH_SPEED_BHT * 4) / (4000000000 / CONFIG_SCLK_HZ))
156   -#define flash_EBIU_AMBCTL_ST ((CONFIG_FLASH_SPEED_BST * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
157   -#define flash_EBIU_AMBCTL_TT ((CONFIG_FLASH_SPEED_BTT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
158   -
159   -#if (flash_EBIU_AMBCTL_TT > 3)
160   -#define flash_EBIU_AMBCTL0_TT B0TT_4
161   -#endif
162   -#if (flash_EBIU_AMBCTL_TT == 3)
163   -#define flash_EBIU_AMBCTL0_TT B0TT_3
164   -#endif
165   -#if (flash_EBIU_AMBCTL_TT == 2)
166   -#define flash_EBIU_AMBCTL0_TT B0TT_2
167   -#endif
168   -#if (flash_EBIU_AMBCTL_TT < 2)
169   -#define flash_EBIU_AMBCTL0_TT B0TT_1
170   -#endif
171   -
172   -#if (flash_EBIU_AMBCTL_ST > 3)
173   -#define flash_EBIU_AMBCTL0_ST B0ST_4
174   -#endif
175   -#if (flash_EBIU_AMBCTL_ST == 3)
176   -#define flash_EBIU_AMBCTL0_ST B0ST_3
177   -#endif
178   -#if (flash_EBIU_AMBCTL_ST == 2)
179   -#define flash_EBIU_AMBCTL0_ST B0ST_2
180   -#endif
181   -#if (flash_EBIU_AMBCTL_ST < 2)
182   -#define flash_EBIU_AMBCTL0_ST B0ST_1
183   -#endif
184   -
185   -#if (flash_EBIU_AMBCTL_HT > 2)
186   -#define flash_EBIU_AMBCTL0_HT B0HT_3
187   -#endif
188   -#if (flash_EBIU_AMBCTL_HT == 2)
189   -#define flash_EBIU_AMBCTL0_HT B0HT_2
190   -#endif
191   -#if (flash_EBIU_AMBCTL_HT == 1)
192   -#define flash_EBIU_AMBCTL0_HT B0HT_1
193   -#endif
194   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
195   -#define flash_EBIU_AMBCTL0_HT B0HT_0
196   -#endif
197   -#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
198   -#define flash_EBIU_AMBCTL0_HT B0HT_1
199   -#endif
200   -
201   -#if (flash_EBIU_AMBCTL_WAT > 14)
202   -#define flash_EBIU_AMBCTL0_WAT B0WAT_15
203   -#endif
204   -#if (flash_EBIU_AMBCTL_WAT == 14)
205   -#define flash_EBIU_AMBCTL0_WAT B0WAT_14
206   -#endif
207   -#if (flash_EBIU_AMBCTL_WAT == 13)
208   -#define flash_EBIU_AMBCTL0_WAT B0WAT_13
209   -#endif
210   -#if (flash_EBIU_AMBCTL_WAT == 12)
211   -#define flash_EBIU_AMBCTL0_WAT B0WAT_12
212   -#endif
213   -#if (flash_EBIU_AMBCTL_WAT == 11)
214   -#define flash_EBIU_AMBCTL0_WAT B0WAT_11
215   -#endif
216   -#if (flash_EBIU_AMBCTL_WAT == 10)
217   -#define flash_EBIU_AMBCTL0_WAT B0WAT_10
218   -#endif
219   -#if (flash_EBIU_AMBCTL_WAT == 9)
220   -#define flash_EBIU_AMBCTL0_WAT B0WAT_9
221   -#endif
222   -#if (flash_EBIU_AMBCTL_WAT == 8)
223   -#define flash_EBIU_AMBCTL0_WAT B0WAT_8
224   -#endif
225   -#if (flash_EBIU_AMBCTL_WAT == 7)
226   -#define flash_EBIU_AMBCTL0_WAT B0WAT_7
227   -#endif
228   -#if (flash_EBIU_AMBCTL_WAT == 6)
229   -#define flash_EBIU_AMBCTL0_WAT B0WAT_6
230   -#endif
231   -#if (flash_EBIU_AMBCTL_WAT == 5)
232   -#define flash_EBIU_AMBCTL0_WAT B0WAT_5
233   -#endif
234   -#if (flash_EBIU_AMBCTL_WAT == 4)
235   -#define flash_EBIU_AMBCTL0_WAT B0WAT_4
236   -#endif
237   -#if (flash_EBIU_AMBCTL_WAT == 3)
238   -#define flash_EBIU_AMBCTL0_WAT B0WAT_3
239   -#endif
240   -#if (flash_EBIU_AMBCTL_WAT == 2)
241   -#define flash_EBIU_AMBCTL0_WAT B0WAT_2
242   -#endif
243   -#if (flash_EBIU_AMBCTL_WAT == 1)
244   -#define flash_EBIU_AMBCTL0_WAT B0WAT_1
245   -#endif
246   -
247   -#if (flash_EBIU_AMBCTL_RAT > 14)
248   -#define flash_EBIU_AMBCTL0_RAT B0RAT_15
249   -#endif
250   -#if (flash_EBIU_AMBCTL_RAT == 14)
251   -#define flash_EBIU_AMBCTL0_RAT B0RAT_14
252   -#endif
253   -#if (flash_EBIU_AMBCTL_RAT == 13)
254   -#define flash_EBIU_AMBCTL0_RAT B0RAT_13
255   -#endif
256   -#if (flash_EBIU_AMBCTL_RAT == 12)
257   -#define flash_EBIU_AMBCTL0_RAT B0RAT_12
258   -#endif
259   -#if (flash_EBIU_AMBCTL_RAT == 11)
260   -#define flash_EBIU_AMBCTL0_RAT B0RAT_11
261   -#endif
262   -#if (flash_EBIU_AMBCTL_RAT == 10)
263   -#define flash_EBIU_AMBCTL0_RAT B0RAT_10
264   -#endif
265   -#if (flash_EBIU_AMBCTL_RAT == 9)
266   -#define flash_EBIU_AMBCTL0_RAT B0RAT_9
267   -#endif
268   -#if (flash_EBIU_AMBCTL_RAT == 8)
269   -#define flash_EBIU_AMBCTL0_RAT B0RAT_8
270   -#endif
271   -#if (flash_EBIU_AMBCTL_RAT == 7)
272   -#define flash_EBIU_AMBCTL0_RAT B0RAT_7
273   -#endif
274   -#if (flash_EBIU_AMBCTL_RAT == 6)
275   -#define flash_EBIU_AMBCTL0_RAT B0RAT_6
276   -#endif
277   -#if (flash_EBIU_AMBCTL_RAT == 5)
278   -#define flash_EBIU_AMBCTL0_RAT B0RAT_5
279   -#endif
280   -#if (flash_EBIU_AMBCTL_RAT == 4)
281   -#define flash_EBIU_AMBCTL0_RAT B0RAT_4
282   -#endif
283   -#if (flash_EBIU_AMBCTL_RAT == 3)
284   -#define flash_EBIU_AMBCTL0_RAT B0RAT_3
285   -#endif
286   -#if (flash_EBIU_AMBCTL_RAT == 2)
287   -#define flash_EBIU_AMBCTL0_RAT B0RAT_2
288   -#endif
289   -#if (flash_EBIU_AMBCTL_RAT == 1)
290   -#define flash_EBIU_AMBCTL0_RAT B0RAT_1
291   -#endif
292   -
293   -#define flash_EBIU_AMBCTL0 \
294   - (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
295   - flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
arch/blackfin/mach-common/Makefile
Diff comments   View file @ 73feb5c
... ... @@ -11,4 +11,5 @@
11 11 obj-$(CONFIG_CPU_FREQ) += cpufreq.o
12 12 obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
13 13 obj-$(CONFIG_SMP) += smp.o
  14 +obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
arch/blackfin/mach-common/clocks-init.c
Diff comments   View file @ 73feb5c
  1 +/*
  2 + * arch/blackfin/mach-common/clocks-init.c - reprogram clocks / memory
  3 + *
  4 + * Copyright 2004-2008 Analog Devices Inc.
  5 + *
  6 + * Licensed under the GPL-2 or later.
  7 + */
  8 +
  9 +#include <linux/linkage.h>
  10 +#include <linux/init.h>
  11 +#include <asm/blackfin.h>
  12 +
  13 +#include <asm/dma.h>
  14 +#include <asm/clocks.h>
  15 +#include <asm/mem_init.h>
  16 +
  17 +#define PLL_CTL_VAL \
  18 + (((CONFIG_VCO_MULT & 63) << 9) | CLKIN_HALF | \
  19 + (PLL_BYPASS << 8) | (ANOMALY_05000265 ? 0x8000 : 0))
  20 +
  21 +__attribute__((l1_text))
  22 +static void do_sync(void)
  23 +{
  24 + __builtin_bfin_ssync();
  25 +}
  26 +
  27 +__attribute__((l1_text))
  28 +void init_clocks(void)
  29 +{
  30 + /* Kill any active DMAs as they may trigger external memory accesses
  31 + * in the middle of reprogramming things, and that'll screw us up.
  32 + * For example, any automatic DMAs left by U-Boot for splash screens.
  33 + */
  34 + size_t i;
  35 + for (i = 0; i < MAX_BLACKFIN_DMA_CHANNEL; ++i) {
  36 + struct dma_register *dma = dma_io_base_addr[i];
  37 + dma->cfg = 0;
  38 + }
  39 +
  40 + do_sync();
  41 +
  42 +#ifdef SIC_IWR0
  43 + bfin_write_SIC_IWR0(IWR_ENABLE(0));
  44 +# ifdef SIC_IWR1
  45 + /* BF52x system reset does not properly reset SIC_IWR1 which
  46 + * will screw up the bootrom as it relies on MDMA0/1 waking it
  47 + * up from IDLE instructions. See this report for more info:
  48 + * http://blackfin.uclinux.org/gf/tracker/4323
  49 + */
  50 + if (ANOMALY_05000435)
  51 + bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
  52 + else
  53 + bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
  54 +# endif
  55 +# ifdef SIC_IWR2
  56 + bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
  57 +# endif
  58 +#else
  59 + bfin_write_SIC_IWR(IWR_ENABLE(0));
  60 +#endif
  61 + do_sync();
  62 +#ifdef EBIU_SDGCTL
  63 + bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
  64 + do_sync();
  65 +#endif
  66 +
  67 +#ifdef CLKBUFOE
  68 + bfin_write16(VR_CTL, bfin_read_VR_CTL() | CLKBUFOE);
  69 + do_sync();
  70 + __asm__ __volatile__("IDLE;");
  71 +#endif
  72 + bfin_write_PLL_LOCKCNT(0x300);
  73 + do_sync();
  74 + bfin_write16(PLL_CTL, PLL_CTL_VAL);
  75 + __asm__ __volatile__("IDLE;");
  76 + bfin_write_PLL_DIV(CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV);
  77 +#ifdef EBIU_SDGCTL
  78 + bfin_write_EBIU_SDRRC(mem_SDRRC);
  79 + bfin_write_EBIU_SDGCTL(mem_SDGCTL);
  80 +#else
  81 + bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
  82 + do_sync();
  83 + bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1);
  84 + bfin_write_EBIU_DDRCTL0(mem_DDRCTL0);
  85 + bfin_write_EBIU_DDRCTL1(mem_DDRCTL1);
  86 + bfin_write_EBIU_DDRCTL2(mem_DDRCTL2);
  87 +#ifdef CONFIG_MEM_EBIU_DDRQUE
  88 + bfin_write_EBIU_DDRQUE(CONFIG_MEM_EBIU_DDRQUE);
  89 +#endif
  90 +#endif
  91 + do_sync();
  92 + bfin_read16(0);
  93 +}
arch/blackfin/mach-common/head.S
Diff comments   View file @ 73feb5c
... ... @@ -147,7 +147,7 @@
147 147 /* Put The Code for PLL Programming and SDRAM Programming in L1 ISRAM */
148 148 call _bfin_relocate_l1_mem;
149 149 #ifdef CONFIG_BFIN_KERNEL_CLOCK
150   - call _start_dma_code;
  150 + call _init_clocks;
151 151 #endif
152 152  
153 153 /* This section keeps the processor in supervisor mode