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Commit 756e46dbaacf1d6d3cbefcef725e0f969afcb1e5

Authored by Abhilash Kesavan
Committed by Kukjin Kim
1 parent f4a75d2eb7
Exists in smarc-l5.0.0_1.0.0-ga and in 5 other branches imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga

ARM: EXYNOS: fix the hotplug for Cortex-A15 

The sequence of cpu_enter_lowpower() for Cortex-A15 is
different from the sequence for Cortex-A9. This patch
implements cpu_enter_lowpower() for EXYNOS5 SoC which
has Cortex-A15 cores.

Basded on original patch has been submitted by Changhwan Youn

Signed-off-by: Changhwan Youn <chaos.youn@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
[kgene.kim@samsung.com: use flush_cache_louis() instead of
flush_cache_all() as per Lorenzo and Santosh's suggestion]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

Showing 1 changed file with 42 additions and 3 deletions Side-by-side Diff

arch/arm/mach-exynos/hotplug.c
Diff comments   View file @ 756e46d
... ... @@ -20,10 +20,11 @@
20 20 #include <asm/smp_plat.h>
21 21  
22 22 #include <mach/regs-pmu.h>
  23 +#include <plat/cpu.h>
23 24  
24 25 #include "common.h"
25 26  
26   -static inline void cpu_enter_lowpower(void)
  27 +static inline void cpu_enter_lowpower_a9(void)
27 28 {
28 29 unsigned int v;
29 30  
... ... @@ -45,6 +46,35 @@
45 46 : "cc");
46 47 }
47 48  
  49 +static inline void cpu_enter_lowpower_a15(void)
  50 +{
  51 + unsigned int v;
  52 +
  53 + asm volatile(
  54 + " mrc p15, 0, %0, c1, c0, 0\n"
  55 + " bic %0, %0, %1\n"
  56 + " mcr p15, 0, %0, c1, c0, 0\n"
  57 + : "=&r" (v)
  58 + : "Ir" (CR_C)
  59 + : "cc");
  60 +
  61 + flush_cache_louis();
  62 +
  63 + asm volatile(
  64 + /*
  65 + * Turn off coherency
  66 + */
  67 + " mrc p15, 0, %0, c1, c0, 1\n"
  68 + " bic %0, %0, %1\n"
  69 + " mcr p15, 0, %0, c1, c0, 1\n"
  70 + : "=&r" (v)
  71 + : "Ir" (0x40)
  72 + : "cc");
  73 +
  74 + isb();
  75 + dsb();
  76 +}
  77 +
48 78 static inline void cpu_leave_lowpower(void)
49 79 {
50 80 unsigned int v;
51 81  
52 82  
... ... @@ -103,11 +133,20 @@
103 133 void __ref exynos_cpu_die(unsigned int cpu)
104 134 {
105 135 int spurious = 0;
  136 + int primary_part = 0;
106 137  
107 138 /*
108   - * we're ready for shutdown now, so do it
  139 + * we're ready for shutdown now, so do it.
  140 + * Exynos4 is A9 based while Exynos5 is A15; check the CPU part
  141 + * number by reading the Main ID register and then perform the
  142 + * appropriate sequence for entering low power.
109 143 */
110   - cpu_enter_lowpower();
  144 + asm("mrc p15, 0, %0, c0, c0, 0" : "=r"(primary_part) : : "cc");
  145 + if ((primary_part & 0xfff0) == 0xc0f0)
  146 + cpu_enter_lowpower_a15();
  147 + else
  148 + cpu_enter_lowpower_a9();
  149 +
111 150 platform_do_lowpower(cpu, &spurious);
112 151  
113 152 /*