Merge branch 'sh/intc-extension'

Paul Mundt
2 parents 7561f2dd39 d519095344
Showing 2 changed files Side-by-side Diff
drivers/sh/intc.c
include/linux/sh_intc.h
@@ -259,6 +259,43 @@
 	}
 }
  
+static void (*intc_enable_noprio_fns[])(unsigned long addr,
+					unsigned long handle,
+					void (*fn)(unsigned long,
+						   unsigned long,
+						   unsigned long),
+					unsigned int irq) = {
+	[MODE_ENABLE_REG] = intc_mode_field,
+	[MODE_MASK_REG] = intc_mode_zero,
+	[MODE_DUAL_REG] = intc_mode_field,
+	[MODE_PRIO_REG] = intc_mode_field,
+	[MODE_PCLR_REG] = intc_mode_field,
+};
+
+static void intc_enable_disable(struct intc_desc_int *d,
+				unsigned long handle, int do_enable)
+{
+	unsigned long addr;
+	unsigned int cpu;
+	void (*fn)(unsigned long, unsigned long,
+		   void (*)(unsigned long, unsigned long, unsigned long),
+		   unsigned int);
+
+	if (do_enable) {
+		for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
+			addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
+			fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
+			fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
+		}
+	} else {
+		for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
+			addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
+			fn = intc_disable_fns[_INTC_MODE(handle)];
+			fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
+		}
+	}
+}
+
 static int intc_set_wake(unsigned int irq, unsigned int on)
 {
 	return 0; /* allow wakeup, but setup hardware in intc_suspend() */
  
@@ -400,11 +437,11 @@
 static intc_enum __init intc_grp_id(struct intc_desc *desc,
 				    intc_enum enum_id)
 {
-	struct intc_group *g = desc->groups;
+	struct intc_group *g = desc->hw.groups;
 	unsigned int i, j;
  
-	for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
-		g = desc->groups + i;
+	for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
+		g = desc->hw.groups + i;
  
 		for (j = 0; g->enum_ids[j]; j++) {
 			if (g->enum_ids[j] != enum_id)
  
  
  
@@ -417,19 +454,21 @@
 	return 0;
 }
  
-static unsigned int __init intc_mask_data(struct intc_desc *desc,
-					  struct intc_desc_int *d,
-					  intc_enum enum_id, int do_grps)
+static unsigned int __init _intc_mask_data(struct intc_desc *desc,
+					   struct intc_desc_int *d,
+					   intc_enum enum_id,
+					   unsigned int *reg_idx,
+					   unsigned int *fld_idx)
 {
-	struct intc_mask_reg *mr = desc->mask_regs;
-	unsigned int i, j, fn, mode;
+	struct intc_mask_reg *mr = desc->hw.mask_regs;
+	unsigned int fn, mode;
 	unsigned long reg_e, reg_d;
  
-	for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
-		mr = desc->mask_regs + i;
+	while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
+		mr = desc->hw.mask_regs + *reg_idx;
  
-		for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
-			if (mr->enum_ids[j] != enum_id)
+		for (; *fld_idx < ARRAY_SIZE(mr->enum_ids); (*fld_idx)++) {
+			if (mr->enum_ids[*fld_idx] != enum_id)
 				continue;
  
 			if (mr->set_reg && mr->clr_reg) {
  
  
  
  
  
  
@@ -455,29 +494,49 @@
 					intc_get_reg(d, reg_e),
 					intc_get_reg(d, reg_d),
 					1,
-					(mr->reg_width - 1) - j);
+					(mr->reg_width - 1) - *fld_idx);
 		}
+
+		*fld_idx = 0;
+		(*reg_idx)++;
 	}
  
+	return 0;
+}
+
+static unsigned int __init intc_mask_data(struct intc_desc *desc,
+					  struct intc_desc_int *d,
+					  intc_enum enum_id, int do_grps)
+{
+	unsigned int i = 0;
+	unsigned int j = 0;
+	unsigned int ret;
+
+	ret = _intc_mask_data(desc, d, enum_id, &i, &j);
+	if (ret)
+		return ret;
+
 	if (do_grps)
 		return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
  
 	return 0;
 }
  
-static unsigned int __init intc_prio_data(struct intc_desc *desc,
-					  struct intc_desc_int *d,
-					  intc_enum enum_id, int do_grps)
+static unsigned int __init _intc_prio_data(struct intc_desc *desc,
+					   struct intc_desc_int *d,
+					   intc_enum enum_id,
+					   unsigned int *reg_idx,
+					   unsigned int *fld_idx)
 {
-	struct intc_prio_reg *pr = desc->prio_regs;
-	unsigned int i, j, fn, mode, bit;
+	struct intc_prio_reg *pr = desc->hw.prio_regs;
+	unsigned int fn, n, mode, bit;
 	unsigned long reg_e, reg_d;
  
-	for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
-		pr = desc->prio_regs + i;
+	while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
+		pr = desc->hw.prio_regs + *reg_idx;
  
-		for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
-			if (pr->enum_ids[j] != enum_id)
+		for (; *fld_idx < ARRAY_SIZE(pr->enum_ids); (*fld_idx)++) {
+			if (pr->enum_ids[*fld_idx] != enum_id)
 				continue;
  
 			if (pr->set_reg && pr->clr_reg) {
  
  
  
  
  
  
  
@@ -495,34 +554,79 @@
 			}
  
 			fn += (pr->reg_width >> 3) - 1;
+			n = *fld_idx + 1;
  
-			BUG_ON((j + 1) * pr->field_width > pr->reg_width);
+			BUG_ON(n * pr->field_width > pr->reg_width);
  
-			bit = pr->reg_width - ((j + 1) * pr->field_width);
+			bit = pr->reg_width - (n * pr->field_width);
  
 			return _INTC_MK(fn, mode,
 					intc_get_reg(d, reg_e),
 					intc_get_reg(d, reg_d),
 					pr->field_width, bit);
 		}
+
+		*fld_idx = 0;
+		(*reg_idx)++;
 	}
  
+	return 0;
+}
+
+static unsigned int __init intc_prio_data(struct intc_desc *desc,
+					  struct intc_desc_int *d,
+					  intc_enum enum_id, int do_grps)
+{
+	unsigned int i = 0;
+	unsigned int j = 0;
+	unsigned int ret;
+
+	ret = _intc_prio_data(desc, d, enum_id, &i, &j);
+	if (ret)
+		return ret;
+
 	if (do_grps)
 		return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
  
 	return 0;
 }
  
+static void __init intc_enable_disable_enum(struct intc_desc *desc,
+					    struct intc_desc_int *d,
+					    intc_enum enum_id, int enable)
+{
+	unsigned int i, j, data;
+
+	/* go through and enable/disable all mask bits */
+	i = j = 0;
+	do {
+		data = _intc_mask_data(desc, d, enum_id, &i, &j);
+		if (data)
+			intc_enable_disable(d, data, enable);
+		j++;
+	} while (data);
+
+	/* go through and enable/disable all priority fields */
+	i = j = 0;
+	do {
+		data = _intc_prio_data(desc, d, enum_id, &i, &j);
+		if (data)
+			intc_enable_disable(d, data, enable);
+
+		j++;
+	} while (data);
+}
+
 static unsigned int __init intc_ack_data(struct intc_desc *desc,
 					  struct intc_desc_int *d,
 					  intc_enum enum_id)
 {
-	struct intc_mask_reg *mr = desc->ack_regs;
+	struct intc_mask_reg *mr = desc->hw.ack_regs;
 	unsigned int i, j, fn, mode;
 	unsigned long reg_e, reg_d;
  
-	for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
-		mr = desc->ack_regs + i;
+	for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
+		mr = desc->hw.ack_regs + i;
  
 		for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
 			if (mr->enum_ids[j] != enum_id)
  
@@ -549,11 +653,11 @@
 					   struct intc_desc_int *d,
 					   intc_enum enum_id)
 {
-	struct intc_sense_reg *sr = desc->sense_regs;
+	struct intc_sense_reg *sr = desc->hw.sense_regs;
 	unsigned int i, j, fn, bit;
  
-	for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
-		sr = desc->sense_regs + i;
+	for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
+		sr = desc->hw.sense_regs + i;
  
 		for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
 			if (sr->enum_ids[j] != enum_id)
@@ -656,7 +760,7 @@
 	/* irq should be disabled by default */
 	d->chip.mask(irq);
  
-	if (desc->ack_regs)
+	if (desc->hw.ack_regs)
 		ack_handle[irq] = intc_ack_data(desc, d, enum_id);
 }
  
@@ -684,6 +788,7 @@
 void __init register_intc_controller(struct intc_desc *desc)
 {
 	unsigned int i, k, smp;
+	struct intc_hw_desc *hw = &desc->hw;
 	struct intc_desc_int *d;
  
 	d = kzalloc(sizeof(*d), GFP_NOWAIT);
@@ -691,10 +796,10 @@
 	INIT_LIST_HEAD(&d->list);
 	list_add(&d->list, &intc_list);
  
-	d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
-	d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
-	d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
-	d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
+	d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
+	d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
+	d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
+	d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
  
 	d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
 #ifdef CONFIG_SMP
  
  
  
  
@@ -702,30 +807,31 @@
 #endif
 	k = 0;
  
-	if (desc->mask_regs) {
-		for (i = 0; i < desc->nr_mask_regs; i++) {
-			smp = IS_SMP(desc->mask_regs[i]);
-			k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
-			k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
+	if (hw->mask_regs) {
+		for (i = 0; i < hw->nr_mask_regs; i++) {
+			smp = IS_SMP(hw->mask_regs[i]);
+			k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
+			k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
 		}
 	}
  
-	if (desc->prio_regs) {
-		d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT);
+	if (hw->prio_regs) {
+		d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
+				  GFP_NOWAIT);
  
-		for (i = 0; i < desc->nr_prio_regs; i++) {
-			smp = IS_SMP(desc->prio_regs[i]);
-			k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
-			k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
+		for (i = 0; i < hw->nr_prio_regs; i++) {
+			smp = IS_SMP(hw->prio_regs[i]);
+			k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
+			k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
 		}
 	}
  
-	if (desc->sense_regs) {
-		d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT);
+	if (hw->sense_regs) {
+		d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
+				   GFP_NOWAIT);
  
-		for (i = 0; i < desc->nr_sense_regs; i++) {
-			k += save_reg(d, k, desc->sense_regs[i].reg, 0);
-		}
+		for (i = 0; i < hw->nr_sense_regs; i++)
+			k += save_reg(d, k, hw->sense_regs[i].reg, 0);
 	}
  
 	d->chip.name = desc->name;
  
  
@@ -738,18 +844,23 @@
 	d->chip.set_type = intc_set_sense;
 	d->chip.set_wake = intc_set_wake;
  
-	if (desc->ack_regs) {
-		for (i = 0; i < desc->nr_ack_regs; i++)
-			k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
+	if (hw->ack_regs) {
+		for (i = 0; i < hw->nr_ack_regs; i++)
+			k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
  
 		d->chip.mask_ack = intc_mask_ack;
 	}
  
+
+	/* disable bits matching force_enable before registering irqs */
+	if (desc->force_enable)
+		intc_enable_disable_enum(desc, d, desc->force_enable, 0);
+
 	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
  
 	/* register the vectors one by one */
-	for (i = 0; i < desc->nr_vectors; i++) {
-		struct intc_vect *vect = desc->vectors + i;
+	for (i = 0; i < hw->nr_vectors; i++) {
+		struct intc_vect *vect = hw->vectors + i;
 		unsigned int irq = evt2irq(vect->vect);
 		struct irq_desc *irq_desc;
  
@@ -764,8 +875,8 @@
  
 		intc_register_irq(desc, d, vect->enum_id, irq);
  
-		for (k = i + 1; k < desc->nr_vectors; k++) {
-			struct intc_vect *vect2 = desc->vectors + k;
+		for (k = i + 1; k < hw->nr_vectors; k++) {
+			struct intc_vect *vect2 = hw->vectors + k;
 			unsigned int irq2 = evt2irq(vect2->vect);
  
 			if (vect->enum_id != vect2->enum_id)
@@ -790,6 +901,10 @@
 			set_irq_data(irq2, (void *)irq);
 		}
 	}
+
+	/* enable bits matching force_enable after registering irqs */
+	if (desc->force_enable)
+		intc_enable_disable_enum(desc, d, desc->force_enable, 1);
 }
  
 static int intc_suspend(struct sys_device *dev, pm_message_t state)
@@ -45,7 +45,7 @@
 #define INTC_SMP(stride, nr)
 #endif
  
-struct intc_desc {
+struct intc_hw_desc {
 	struct intc_vect *vectors;
 	unsigned int nr_vectors;
 	struct intc_group *groups;
  
  
  
@@ -56,29 +56,39 @@
 	unsigned int nr_prio_regs;
 	struct intc_sense_reg *sense_regs;
 	unsigned int nr_sense_regs;
-	char *name;
 	struct intc_mask_reg *ack_regs;
 	unsigned int nr_ack_regs;
 };
  
 #define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
+#define INTC_HW_DESC(vectors, groups, mask_regs,	\
+		     prio_regs,	sense_regs, ack_regs)	\
+{							\
+	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),	\
+	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),	\
+	_INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs),	\
+}
+
+struct intc_desc {
+	char *name;
+	intc_enum force_enable;
+	struct intc_hw_desc hw;
+};
+
 #define DECLARE_INTC_DESC(symbol, chipname, vectors, groups,		\
 	mask_regs, prio_regs, sense_regs)				\
 struct intc_desc symbol __initdata = {					\
-	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),			\
-	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),			\
-	_INTC_ARRAY(sense_regs),					\
-	chipname,							\
+	.name = chipname,						\
+	.hw = INTC_HW_DESC(vectors, groups, mask_regs,			\
+			   prio_regs, sense_regs, NULL),		\
 }
  
 #define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups,	\
 	mask_regs, prio_regs, sense_regs, ack_regs)			\
 struct intc_desc symbol __initdata = {					\
-	_INTC_ARRAY(vectors), _INTC_ARRAY(groups),			\
-	_INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs),			\
-	_INTC_ARRAY(sense_regs),					\
-	chipname,							\
-	_INTC_ARRAY(ack_regs),						\
+	.name = chipname,						\
+	.hw = INTC_HW_DESC(vectors, groups, mask_regs,			\
+			   prio_regs, sense_regs, ack_regs),		\
 }
  
 void __init register_intc_controller(struct intc_desc *desc);
...	...	@@ -259,6 +259,43 @@
259	259	}
260	260	}
261	261
	262	+static void (*intc_enable_noprio_fns[])(unsigned long addr,
	263	+ unsigned long handle,
	264	+ void (*fn)(unsigned long,
	265	+ unsigned long,
	266	+ unsigned long),
	267	+ unsigned int irq) = {
	268	+ [MODE_ENABLE_REG] = intc_mode_field,
	269	+ [MODE_MASK_REG] = intc_mode_zero,
	270	+ [MODE_DUAL_REG] = intc_mode_field,
	271	+ [MODE_PRIO_REG] = intc_mode_field,
	272	+ [MODE_PCLR_REG] = intc_mode_field,
	273	+};
	274	+
	275	+static void intc_enable_disable(struct intc_desc_int *d,
	276	+ unsigned long handle, int do_enable)
	277	+{
	278	+ unsigned long addr;
	279	+ unsigned int cpu;
	280	+ void (*fn)(unsigned long, unsigned long,
	281	+ void (*)(unsigned long, unsigned long, unsigned long),
	282	+ unsigned int);
	283	+
	284	+ if (do_enable) {
	285	+ for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
	286	+ addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
	287	+ fn = intc_enable_noprio_fns[_INTC_MODE(handle)];
	288	+ fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
	289	+ }
	290	+ } else {
	291	+ for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
	292	+ addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
	293	+ fn = intc_disable_fns[_INTC_MODE(handle)];
	294	+ fn(addr, handle, intc_reg_fns[_INTC_FN(handle)], 0);
	295	+ }
	296	+ }
	297	+}
	298	+
262	299	static int intc_set_wake(unsigned int irq, unsigned int on)
263	300	{
264	301	return 0; /* allow wakeup, but setup hardware in intc_suspend() */
265	302
...	...	@@ -400,11 +437,11 @@
400	437	static intc_enum __init intc_grp_id(struct intc_desc *desc,
401	438	intc_enum enum_id)
402	439	{
403		- struct intc_group *g = desc->groups;
	440	+ struct intc_group *g = desc->hw.groups;
404	441	unsigned int i, j;
405	442
406		- for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
407		- g = desc->groups + i;
	443	+ for (i = 0; g && enum_id && i < desc->hw.nr_groups; i++) {
	444	+ g = desc->hw.groups + i;
408	445
409	446	for (j = 0; g->enum_ids[j]; j++) {
410	447	if (g->enum_ids[j] != enum_id)
411	448
412	449
413	450
...	...	@@ -417,19 +454,21 @@
417	454	return 0;
418	455	}
419	456
420		-static unsigned int __init intc_mask_data(struct intc_desc *desc,
421		- struct intc_desc_int *d,
422		- intc_enum enum_id, int do_grps)
	457	+static unsigned int __init _intc_mask_data(struct intc_desc *desc,
	458	+ struct intc_desc_int *d,
	459	+ intc_enum enum_id,
	460	+ unsigned int *reg_idx,
	461	+ unsigned int *fld_idx)
423	462	{
424		- struct intc_mask_reg *mr = desc->mask_regs;
425		- unsigned int i, j, fn, mode;
	463	+ struct intc_mask_reg *mr = desc->hw.mask_regs;
	464	+ unsigned int fn, mode;
426	465	unsigned long reg_e, reg_d;
427	466
428		- for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
429		- mr = desc->mask_regs + i;
	467	+ while (mr && enum_id && *reg_idx < desc->hw.nr_mask_regs) {
	468	+ mr = desc->hw.mask_regs + *reg_idx;
430	469
431		- for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
432		- if (mr->enum_ids[j] != enum_id)
	470	+ for (; fld_idx < ARRAY_SIZE(mr->enum_ids); (fld_idx)++) {
	471	+ if (mr->enum_ids[*fld_idx] != enum_id)
433	472	continue;
434	473
435	474	if (mr->set_reg && mr->clr_reg) {
436	475
437	476
438	477
439	478
440	479
441	480
...	...	@@ -455,29 +494,49 @@
455	494	intc_get_reg(d, reg_e),
456	495	intc_get_reg(d, reg_d),
457	496	1,
458		- (mr->reg_width - 1) - j);
	497	+ (mr->reg_width - 1) - *fld_idx);
459	498	}
	499	+
	500	+ *fld_idx = 0;
	501	+ (*reg_idx)++;
460	502	}
461	503
	504	+ return 0;
	505	+}
	506	+
	507	+static unsigned int __init intc_mask_data(struct intc_desc *desc,
	508	+ struct intc_desc_int *d,
	509	+ intc_enum enum_id, int do_grps)
	510	+{
	511	+ unsigned int i = 0;
	512	+ unsigned int j = 0;
	513	+ unsigned int ret;
	514	+
	515	+ ret = _intc_mask_data(desc, d, enum_id, &i, &j);
	516	+ if (ret)
	517	+ return ret;
	518	+
462	519	if (do_grps)
463	520	return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
464	521
465	522	return 0;
466	523	}
467	524
468		-static unsigned int __init intc_prio_data(struct intc_desc *desc,
469		- struct intc_desc_int *d,
470		- intc_enum enum_id, int do_grps)
	525	+static unsigned int __init _intc_prio_data(struct intc_desc *desc,
	526	+ struct intc_desc_int *d,
	527	+ intc_enum enum_id,
	528	+ unsigned int *reg_idx,
	529	+ unsigned int *fld_idx)
471	530	{
472		- struct intc_prio_reg *pr = desc->prio_regs;
473		- unsigned int i, j, fn, mode, bit;
	531	+ struct intc_prio_reg *pr = desc->hw.prio_regs;
	532	+ unsigned int fn, n, mode, bit;
474	533	unsigned long reg_e, reg_d;
475	534
476		- for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
477		- pr = desc->prio_regs + i;
	535	+ while (pr && enum_id && *reg_idx < desc->hw.nr_prio_regs) {
	536	+ pr = desc->hw.prio_regs + *reg_idx;
478	537
479		- for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
480		- if (pr->enum_ids[j] != enum_id)
	538	+ for (; fld_idx < ARRAY_SIZE(pr->enum_ids); (fld_idx)++) {
	539	+ if (pr->enum_ids[*fld_idx] != enum_id)
481	540	continue;
482	541
483	542	if (pr->set_reg && pr->clr_reg) {
484	543
485	544
486	545
487	546
488	547
489	548
490	549
...	...	@@ -495,34 +554,79 @@
495	554	}
496	555
497	556	fn += (pr->reg_width >> 3) - 1;
	557	+ n = *fld_idx + 1;
498	558
499		- BUG_ON((j + 1) * pr->field_width > pr->reg_width);
	559	+ BUG_ON(n * pr->field_width > pr->reg_width);
500	560
501		- bit = pr->reg_width - ((j + 1) * pr->field_width);
	561	+ bit = pr->reg_width - (n * pr->field_width);
502	562
503	563	return _INTC_MK(fn, mode,
504	564	intc_get_reg(d, reg_e),
505	565	intc_get_reg(d, reg_d),
506	566	pr->field_width, bit);
507	567	}
	568	+
	569	+ *fld_idx = 0;
	570	+ (*reg_idx)++;
508	571	}
509	572
	573	+ return 0;
	574	+}
	575	+
	576	+static unsigned int __init intc_prio_data(struct intc_desc *desc,
	577	+ struct intc_desc_int *d,
	578	+ intc_enum enum_id, int do_grps)
	579	+{
	580	+ unsigned int i = 0;
	581	+ unsigned int j = 0;
	582	+ unsigned int ret;
	583	+
	584	+ ret = _intc_prio_data(desc, d, enum_id, &i, &j);
	585	+ if (ret)
	586	+ return ret;
	587	+
510	588	if (do_grps)
511	589	return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
512	590
513	591	return 0;
514	592	}
515	593
	594	+static void __init intc_enable_disable_enum(struct intc_desc *desc,
	595	+ struct intc_desc_int *d,
	596	+ intc_enum enum_id, int enable)
	597	+{
	598	+ unsigned int i, j, data;
	599	+
	600	+ /* go through and enable/disable all mask bits */
	601	+ i = j = 0;
	602	+ do {
	603	+ data = _intc_mask_data(desc, d, enum_id, &i, &j);
	604	+ if (data)
	605	+ intc_enable_disable(d, data, enable);
	606	+ j++;
	607	+ } while (data);
	608	+
	609	+ /* go through and enable/disable all priority fields */
	610	+ i = j = 0;
	611	+ do {
	612	+ data = _intc_prio_data(desc, d, enum_id, &i, &j);
	613	+ if (data)
	614	+ intc_enable_disable(d, data, enable);
	615	+
	616	+ j++;
	617	+ } while (data);
	618	+}
	619	+
516	620	static unsigned int __init intc_ack_data(struct intc_desc *desc,
517	621	struct intc_desc_int *d,
518	622	intc_enum enum_id)
519	623	{
520		- struct intc_mask_reg *mr = desc->ack_regs;
	624	+ struct intc_mask_reg *mr = desc->hw.ack_regs;
521	625	unsigned int i, j, fn, mode;
522	626	unsigned long reg_e, reg_d;
523	627
524		- for (i = 0; mr && enum_id && i < desc->nr_ack_regs; i++) {
525		- mr = desc->ack_regs + i;
	628	+ for (i = 0; mr && enum_id && i < desc->hw.nr_ack_regs; i++) {
	629	+ mr = desc->hw.ack_regs + i;
526	630
527	631	for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
528	632	if (mr->enum_ids[j] != enum_id)
529	633
...	...	@@ -549,11 +653,11 @@
549	653	struct intc_desc_int *d,
550	654	intc_enum enum_id)
551	655	{
552		- struct intc_sense_reg *sr = desc->sense_regs;
	656	+ struct intc_sense_reg *sr = desc->hw.sense_regs;
553	657	unsigned int i, j, fn, bit;
554	658
555		- for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
556		- sr = desc->sense_regs + i;
	659	+ for (i = 0; sr && enum_id && i < desc->hw.nr_sense_regs; i++) {
	660	+ sr = desc->hw.sense_regs + i;
557	661
558	662	for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
559	663	if (sr->enum_ids[j] != enum_id)
...	...	@@ -656,7 +760,7 @@
656	760	/* irq should be disabled by default */
657	761	d->chip.mask(irq);
658	762
659		- if (desc->ack_regs)
	763	+ if (desc->hw.ack_regs)
660	764	ack_handle[irq] = intc_ack_data(desc, d, enum_id);
661	765	}
662	766
...	...	@@ -684,6 +788,7 @@
684	788	void __init register_intc_controller(struct intc_desc *desc)
685	789	{
686	790	unsigned int i, k, smp;
	791	+ struct intc_hw_desc *hw = &desc->hw;
687	792	struct intc_desc_int *d;
688	793
689	794	d = kzalloc(sizeof(*d), GFP_NOWAIT);
...	...	@@ -691,10 +796,10 @@
691	796	INIT_LIST_HEAD(&d->list);
692	797	list_add(&d->list, &intc_list);
693	798
694		- d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
695		- d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
696		- d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
697		- d->nr_reg += desc->ack_regs ? desc->nr_ack_regs : 0;
	799	+ d->nr_reg = hw->mask_regs ? hw->nr_mask_regs * 2 : 0;
	800	+ d->nr_reg += hw->prio_regs ? hw->nr_prio_regs * 2 : 0;
	801	+ d->nr_reg += hw->sense_regs ? hw->nr_sense_regs : 0;
	802	+ d->nr_reg += hw->ack_regs ? hw->nr_ack_regs : 0;
698	803
699	804	d->reg = kzalloc(d->nr_reg * sizeof(*d->reg), GFP_NOWAIT);
700	805	#ifdef CONFIG_SMP
701	806
702	807
703	808
704	809
...	...	@@ -702,30 +807,31 @@
702	807	#endif
703	808	k = 0;
704	809
705		- if (desc->mask_regs) {
706		- for (i = 0; i < desc->nr_mask_regs; i++) {
707		- smp = IS_SMP(desc->mask_regs[i]);
708		- k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
709		- k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
	810	+ if (hw->mask_regs) {
	811	+ for (i = 0; i < hw->nr_mask_regs; i++) {
	812	+ smp = IS_SMP(hw->mask_regs[i]);
	813	+ k += save_reg(d, k, hw->mask_regs[i].set_reg, smp);
	814	+ k += save_reg(d, k, hw->mask_regs[i].clr_reg, smp);
710	815	}
711	816	}
712	817
713		- if (desc->prio_regs) {
714		- d->prio = kzalloc(desc->nr_vectors * sizeof(*d->prio), GFP_NOWAIT);
	818	+ if (hw->prio_regs) {
	819	+ d->prio = kzalloc(hw->nr_vectors * sizeof(*d->prio),
	820	+ GFP_NOWAIT);
715	821
716		- for (i = 0; i < desc->nr_prio_regs; i++) {
717		- smp = IS_SMP(desc->prio_regs[i]);
718		- k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
719		- k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
	822	+ for (i = 0; i < hw->nr_prio_regs; i++) {
	823	+ smp = IS_SMP(hw->prio_regs[i]);
	824	+ k += save_reg(d, k, hw->prio_regs[i].set_reg, smp);
	825	+ k += save_reg(d, k, hw->prio_regs[i].clr_reg, smp);
720	826	}
721	827	}
722	828
723		- if (desc->sense_regs) {
724		- d->sense = kzalloc(desc->nr_vectors * sizeof(*d->sense), GFP_NOWAIT);
	829	+ if (hw->sense_regs) {
	830	+ d->sense = kzalloc(hw->nr_vectors * sizeof(*d->sense),
	831	+ GFP_NOWAIT);
725	832
726		- for (i = 0; i < desc->nr_sense_regs; i++) {
727		- k += save_reg(d, k, desc->sense_regs[i].reg, 0);
728		- }
	833	+ for (i = 0; i < hw->nr_sense_regs; i++)
	834	+ k += save_reg(d, k, hw->sense_regs[i].reg, 0);
729	835	}
730	836
731	837	d->chip.name = desc->name;
732	838
733	839
...	...	@@ -738,18 +844,23 @@
738	844	d->chip.set_type = intc_set_sense;
739	845	d->chip.set_wake = intc_set_wake;
740	846
741		- if (desc->ack_regs) {
742		- for (i = 0; i < desc->nr_ack_regs; i++)
743		- k += save_reg(d, k, desc->ack_regs[i].set_reg, 0);
	847	+ if (hw->ack_regs) {
	848	+ for (i = 0; i < hw->nr_ack_regs; i++)
	849	+ k += save_reg(d, k, hw->ack_regs[i].set_reg, 0);
744	850
745	851	d->chip.mask_ack = intc_mask_ack;
746	852	}
747	853
	854	+
	855	+ /* disable bits matching force_enable before registering irqs */
	856	+ if (desc->force_enable)
	857	+ intc_enable_disable_enum(desc, d, desc->force_enable, 0);
	858	+
748	859	BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
749	860
750	861	/* register the vectors one by one */
751		- for (i = 0; i < desc->nr_vectors; i++) {
752		- struct intc_vect *vect = desc->vectors + i;
	862	+ for (i = 0; i < hw->nr_vectors; i++) {
	863	+ struct intc_vect *vect = hw->vectors + i;
753	864	unsigned int irq = evt2irq(vect->vect);
754	865	struct irq_desc *irq_desc;
755	866
...	...	@@ -764,8 +875,8 @@
764	875
765	876	intc_register_irq(desc, d, vect->enum_id, irq);
766	877
767		- for (k = i + 1; k < desc->nr_vectors; k++) {
768		- struct intc_vect *vect2 = desc->vectors + k;
	878	+ for (k = i + 1; k < hw->nr_vectors; k++) {
	879	+ struct intc_vect *vect2 = hw->vectors + k;
769	880	unsigned int irq2 = evt2irq(vect2->vect);
770	881
771	882	if (vect->enum_id != vect2->enum_id)
...	...	@@ -790,6 +901,10 @@
790	901	set_irq_data(irq2, (void *)irq);
791	902	}
792	903	}
	904	+
	905	+ /* enable bits matching force_enable after registering irqs */
	906	+ if (desc->force_enable)
	907	+ intc_enable_disable_enum(desc, d, desc->force_enable, 1);
793	908	}
794	909
795	910	static int intc_suspend(struct sys_device *dev, pm_message_t state)
...	...	@@ -45,7 +45,7 @@
45	45	#define INTC_SMP(stride, nr)
46	46	#endif
47	47
48		-struct intc_desc {
	48	+struct intc_hw_desc {
49	49	struct intc_vect *vectors;
50	50	unsigned int nr_vectors;
51	51	struct intc_group *groups;
52	52
53	53
54	54
...	...	@@ -56,29 +56,39 @@
56	56	unsigned int nr_prio_regs;
57	57	struct intc_sense_reg *sense_regs;
58	58	unsigned int nr_sense_regs;
59		- char *name;
60	59	struct intc_mask_reg *ack_regs;
61	60	unsigned int nr_ack_regs;
62	61	};
63	62
64	63	#define _INTC_ARRAY(a) a, sizeof(a)/sizeof(*a)
	64	+#define INTC_HW_DESC(vectors, groups, mask_regs, \
	65	+ prio_regs, sense_regs, ack_regs) \
	66	+{ \
	67	+ _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
	68	+ _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
	69	+ _INTC_ARRAY(sense_regs), _INTC_ARRAY(ack_regs), \
	70	+}
	71	+
	72	+struct intc_desc {
	73	+ char *name;
	74	+ intc_enum force_enable;
	75	+ struct intc_hw_desc hw;
	76	+};
	77	+
65	78	#define DECLARE_INTC_DESC(symbol, chipname, vectors, groups, \
66	79	mask_regs, prio_regs, sense_regs) \
67	80	struct intc_desc symbol __initdata = { \
68		- _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
69		- _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
70		- _INTC_ARRAY(sense_regs), \
71		- chipname, \
	81	+ .name = chipname, \
	82	+ .hw = INTC_HW_DESC(vectors, groups, mask_regs, \
	83	+ prio_regs, sense_regs, NULL), \
72	84	}
73	85
74	86	#define DECLARE_INTC_DESC_ACK(symbol, chipname, vectors, groups, \
75	87	mask_regs, prio_regs, sense_regs, ack_regs) \
76	88	struct intc_desc symbol __initdata = { \
77		- _INTC_ARRAY(vectors), _INTC_ARRAY(groups), \
78		- _INTC_ARRAY(mask_regs), _INTC_ARRAY(prio_regs), \
79		- _INTC_ARRAY(sense_regs), \
80		- chipname, \
81		- _INTC_ARRAY(ack_regs), \
	89	+ .name = chipname, \
	90	+ .hw = INTC_HW_DESC(vectors, groups, mask_regs, \
	91	+ prio_regs, sense_regs, ack_regs), \
82	92	}
83	93
84	94	void __init register_intc_controller(struct intc_desc *desc);