powerpc/fsl-booke: Move loadcam_entry back to asm code to fix SMP ftrace

When we build with ftrace enabled its possible that loadcam_entry would have used the stack pointer (even though the code doesn't need it). We call loadcam_entry in __secondary_start before the stack is setup. To ensure that loadcam_entry doesn't use the stack pointer the easiest solution is to just have it in asm code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

powerpc/fsl-booke: Move loadcam_entry back to asm code to fix SMP ftrace
When we build with ftrace enabled its possible that loadcam_entry would have used the stack pointer (even though the code doesn't need it). We call loadcam_entry in __secondary_start before the stack is setup. To ensure that loadcam_entry doesn't use the stack pointer the easiest solution is to just have it in asm code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Kumar Gala
1 parent 78e2e68a2b
Showing 4 changed files with 48 additions and 23 deletions Side-by-side Diff
arch/powerpc/kernel/asm-offsets.c
arch/powerpc/mm/fsl_booke_mmu.c
arch/powerpc/mm/mmu_decl.h
arch/powerpc/mm/tlb_nohash_low.S
@@ -448,6 +448,14 @@
 	DEFINE(PGD_T_LOG2, PGD_T_LOG2);
 	DEFINE(PTE_T_LOG2, PTE_T_LOG2);
 #endif
+#ifdef CONFIG_FSL_BOOKE
+	DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
+	DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
+	DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
+	DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2));
+	DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3));
+	DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7));
+#endif
  
 #ifdef CONFIG_KVM_EXIT_TIMING
 	DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
@@ -2,7 +2,7 @@
  * Modifications by Kumar Gala (galak@kernel.crashing.org) to support
  * E500 Book E processors.
  *
- * Copyright 2004 Freescale Semiconductor, Inc
+ * Copyright 2004,2010 Freescale Semiconductor, Inc.
  *
  * This file contains the routines for initializing the MMU
  * on the 4xx series of chips.
  
@@ -56,19 +56,13 @@
  
 unsigned int tlbcam_index;
  
-#define NUM_TLBCAMS	(64)
  
 #if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
 #error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
 #endif
  
-struct tlbcam {
-	u32	MAS0;
-	u32	MAS1;
-	unsigned long	MAS2;
-	u32	MAS3;
-	u32	MAS7;
-} TLBCAM[NUM_TLBCAMS];
+#define NUM_TLBCAMS	(64)
+struct tlbcam TLBCAM[NUM_TLBCAMS];
  
 struct tlbcamrange {
 	unsigned long start;
@@ -107,19 +101,6 @@
 		              +tlbcam_addrs[b].phys)
 			return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys);
 	return 0;
-}
-
-void loadcam_entry(int idx)
-{
-	mtspr(SPRN_MAS0, TLBCAM[idx].MAS0);
-	mtspr(SPRN_MAS1, TLBCAM[idx].MAS1);
-	mtspr(SPRN_MAS2, TLBCAM[idx].MAS2);
-	mtspr(SPRN_MAS3, TLBCAM[idx].MAS3);
-
-	if (mmu_has_feature(MMU_FTR_BIG_PHYS))
-		mtspr(SPRN_MAS7, TLBCAM[idx].MAS7);
-
-	asm volatile("isync;tlbwe;isync" : : : "memory");
 }
  
 /*
@@ -144,7 +144,15 @@
 extern void MMU_init_hw(void);
 extern unsigned long mmu_mapin_ram(unsigned long top);
 extern void adjust_total_lowmem(void);
+extern void loadcam_entry(unsigned int index);
  
+struct tlbcam {
+	u32	MAS0;
+	u32	MAS1;
+	unsigned long	MAS2;
+	u32	MAS3;
+	u32	MAS7;
+};
 #elif defined(CONFIG_PPC32)
 /* anything 32-bit except 4xx or 8xx */
 extern void MMU_init_hw(void);
@@ -365,4 +365,32 @@
 #else
 #error Unsupported processor type !
 #endif
+
+#if defined(CONFIG_FSL_BOOKE)
+/*
+ * extern void loadcam_entry(unsigned int index)
+ *
+ * Load TLBCAM[index] entry in to the L2 CAM MMU
+ */
+_GLOBAL(loadcam_entry)
+	LOAD_REG_ADDR(r4, TLBCAM)
+	mulli	r5,r3,TLBCAM_SIZE
+	add	r3,r5,r4
+	lwz	r4,TLBCAM_MAS0(r3)
+	mtspr	SPRN_MAS0,r4
+	lwz	r4,TLBCAM_MAS1(r3)
+	mtspr	SPRN_MAS1,r4
+	PPC_LL	r4,TLBCAM_MAS2(r3)
+	mtspr	SPRN_MAS2,r4
+	lwz	r4,TLBCAM_MAS3(r3)
+	mtspr	SPRN_MAS3,r4
+BEGIN_MMU_FTR_SECTION
+	lwz	r4,TLBCAM_MAS7(r3)
+	mtspr	SPRN_MAS7,r4
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
+	isync
+	tlbwe
+	isync
+	blr
+#endif
...	...	@@ -448,6 +448,14 @@
448	448	DEFINE(PGD_T_LOG2, PGD_T_LOG2);
449	449	DEFINE(PTE_T_LOG2, PTE_T_LOG2);
450	450	#endif
	451	+#ifdef CONFIG_FSL_BOOKE
	452	+ DEFINE(TLBCAM_SIZE, sizeof(struct tlbcam));
	453	+ DEFINE(TLBCAM_MAS0, offsetof(struct tlbcam, MAS0));
	454	+ DEFINE(TLBCAM_MAS1, offsetof(struct tlbcam, MAS1));
	455	+ DEFINE(TLBCAM_MAS2, offsetof(struct tlbcam, MAS2));
	456	+ DEFINE(TLBCAM_MAS3, offsetof(struct tlbcam, MAS3));
	457	+ DEFINE(TLBCAM_MAS7, offsetof(struct tlbcam, MAS7));
	458	+#endif
451	459
452	460	#ifdef CONFIG_KVM_EXIT_TIMING
453	461	DEFINE(VCPU_TIMING_EXIT_TBU, offsetof(struct kvm_vcpu,
...	...	@@ -2,7 +2,7 @@
2	2	* Modifications by Kumar Gala (galak@kernel.crashing.org) to support
3	3	* E500 Book E processors.
4	4	*
5		- * Copyright 2004 Freescale Semiconductor, Inc
	5	+ * Copyright 2004,2010 Freescale Semiconductor, Inc.
6	6	*
7	7	* This file contains the routines for initializing the MMU
8	8	* on the 4xx series of chips.
9	9
...	...	@@ -56,19 +56,13 @@
56	56
57	57	unsigned int tlbcam_index;
58	58
59		-#define NUM_TLBCAMS (64)
60	59
61	60	#if defined(CONFIG_LOWMEM_CAM_NUM_BOOL) && (CONFIG_LOWMEM_CAM_NUM >= NUM_TLBCAMS)
62	61	#error "LOWMEM_CAM_NUM must be less than NUM_TLBCAMS"
63	62	#endif
64	63
65		-struct tlbcam {
66		- u32 MAS0;
67		- u32 MAS1;
68		- unsigned long MAS2;
69		- u32 MAS3;
70		- u32 MAS7;
71		-} TLBCAM[NUM_TLBCAMS];
	64	+#define NUM_TLBCAMS (64)
	65	+struct tlbcam TLBCAM[NUM_TLBCAMS];
72	66
73	67	struct tlbcamrange {
74	68	unsigned long start;
...	...	@@ -107,19 +101,6 @@
107	101	+tlbcam_addrs[b].phys)
108	102	return tlbcam_addrs[b].start+(pa-tlbcam_addrs[b].phys);
109	103	return 0;
110		-}
111		-
112		-void loadcam_entry(int idx)
113		-{
114		- mtspr(SPRN_MAS0, TLBCAM[idx].MAS0);
115		- mtspr(SPRN_MAS1, TLBCAM[idx].MAS1);
116		- mtspr(SPRN_MAS2, TLBCAM[idx].MAS2);
117		- mtspr(SPRN_MAS3, TLBCAM[idx].MAS3);
118		-
119		- if (mmu_has_feature(MMU_FTR_BIG_PHYS))
120		- mtspr(SPRN_MAS7, TLBCAM[idx].MAS7);
121		-
122		- asm volatile("isync;tlbwe;isync" : : : "memory");
123	104	}
124	105
125	106	/*
...	...	@@ -144,7 +144,15 @@
144	144	extern void MMU_init_hw(void);
145	145	extern unsigned long mmu_mapin_ram(unsigned long top);
146	146	extern void adjust_total_lowmem(void);
	147	+extern void loadcam_entry(unsigned int index);
147	148
	149	+struct tlbcam {
	150	+ u32 MAS0;
	151	+ u32 MAS1;
	152	+ unsigned long MAS2;
	153	+ u32 MAS3;
	154	+ u32 MAS7;
	155	+};
148	156	#elif defined(CONFIG_PPC32)
149	157	/* anything 32-bit except 4xx or 8xx */
150	158	extern void MMU_init_hw(void);
...	...	@@ -365,4 +365,32 @@
365	365	#else
366	366	#error Unsupported processor type !
367	367	#endif
	368	+
	369	+#if defined(CONFIG_FSL_BOOKE)
	370	+/*
	371	+ * extern void loadcam_entry(unsigned int index)
	372	+ *
	373	+ * Load TLBCAM[index] entry in to the L2 CAM MMU
	374	+ */
	375	+_GLOBAL(loadcam_entry)
	376	+ LOAD_REG_ADDR(r4, TLBCAM)
	377	+ mulli r5,r3,TLBCAM_SIZE
	378	+ add r3,r5,r4
	379	+ lwz r4,TLBCAM_MAS0(r3)
	380	+ mtspr SPRN_MAS0,r4
	381	+ lwz r4,TLBCAM_MAS1(r3)
	382	+ mtspr SPRN_MAS1,r4
	383	+ PPC_LL r4,TLBCAM_MAS2(r3)
	384	+ mtspr SPRN_MAS2,r4
	385	+ lwz r4,TLBCAM_MAS3(r3)
	386	+ mtspr SPRN_MAS3,r4
	387	+BEGIN_MMU_FTR_SECTION
	388	+ lwz r4,TLBCAM_MAS7(r3)
	389	+ mtspr SPRN_MAS7,r4
	390	+END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
	391	+ isync
	392	+ tlbwe
	393	+ isync
	394	+ blr
	395	+#endif