Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64

Pull arm64 patches from Catalin Marinas: - SMP support for the PSCI booting protocol (power state coordination interface). - Simple earlyprintk support. - Platform devices populated by default from the DT (SoC-agnostic). - CONTEXTIDR support (used by external trace tools). * tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: arm64: mm: update CONTEXTIDR register to contain PID of current process arm64: atomics: fix grossly inconsistent asm constraints for exclusives arm64: compat: use compat_uptr_t type for compat_ucontext.uc_link arm64: Select ARCH_WANT_FRAME_POINTERS arm64: Add kvm_para.h and xor.h generic headers arm64: SMP: enable PSCI boot method arm64: psci: add support for PSCI invocations from the kernel arm64: SMP: rework the SMP code to be enabling method agnostic arm64: perf: add guest vs host discrimination arm64: add COMPAT_PSR_*_BIT flags arm64: Add simple earlyprintk support arm64: Populate the platform devices

Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64
Pull arm64 patches from Catalin Marinas: - SMP support for the PSCI booting protocol (power state coordination interface). - Simple earlyprintk support. - Platform devices populated by default from the DT (SoC-agnostic). - CONTEXTIDR support (used by external trace tools). * tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/linux-aarch64: arm64: mm: update CONTEXTIDR register to contain PID of current process arm64: atomics: fix grossly inconsistent asm constraints for exclusives arm64: compat: use compat_uptr_t type for compat_ucontext.uc_link arm64: Select ARCH_WANT_FRAME_POINTERS arm64: Add kvm_para.h and xor.h generic headers arm64: SMP: enable PSCI boot method arm64: psci: add support for PSCI invocations from the kernel arm64: SMP: rework the SMP code to be enabling method agnostic arm64: perf: add guest vs host discrimination arm64: add COMPAT_PSR_*_BIT flags arm64: Add simple earlyprintk support arm64: Populate the platform devices
Linus Torvalds
2 parents 6db167dfc0 ec45d1cfd3
Showing 29 changed files Side-by-side Diff
Documentation/arm64/memory.txt
arch/arm64/Kconfig
arch/arm64/Kconfig.debug
arch/arm64/include/asm/Kbuild
arch/arm64/include/asm/atomic.h
arch/arm64/include/asm/cmpxchg.h
arch/arm64/include/asm/futex.h
arch/arm64/include/asm/io.h
arch/arm64/include/asm/memory.h
arch/arm64/include/asm/mmu.h
arch/arm64/include/asm/mmu_context.h
arch/arm64/include/asm/perf_event.h
arch/arm64/include/asm/psci.h
arch/arm64/include/asm/ptrace.h
arch/arm64/include/asm/smp.h
arch/arm64/include/asm/spinlock.h
arch/arm64/include/uapi/asm/Kbuild
arch/arm64/kernel/Makefile
arch/arm64/kernel/early_printk.c
arch/arm64/kernel/head.S
@@ -35,6 +35,8 @@
  
 ffffffbe00000000	ffffffbffbbfffff	  ~8GB		[guard, future vmmemap]
  
+ffffffbffbc00000	ffffffbffbdfffff	   2MB		earlyprintk device
+
 ffffffbffbe00000	ffffffbffbe0ffff	  64KB		PCI I/O space
  
 ffffffbbffff0000	ffffffbcffffffff	  ~2MB		[guard]
@@ -2,6 +2,7 @@
 	def_bool y
 	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
 	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
+	select ARCH_WANT_FRAME_POINTERS
 	select ARM_AMBA
 	select CLONE_BACKWARDS
 	select COMMON_CLK
@@ -24,5 +24,22 @@
 	  Enables the display of the minimum amount of free stack which each
 	  task has ever had available in the sysrq-T output.
  
+config EARLY_PRINTK
+	bool "Early printk support"
+	default y
+	help
+	  Say Y here if you want to have an early console using the
+	  earlyprintk=<name>[,<addr>][,<options>] kernel parameter. It
+	  is assumed that the early console device has been initialised
+	  by the boot loader prior to starting the Linux kernel.
+
+config PID_IN_CONTEXTIDR
+	bool "Write the current PID to the CONTEXTIDR register"
+	help
+	  Enabling this option causes the kernel to write the current PID to
+	  the CONTEXTIDR register, at the expense of some additional
+	  instructions during context switch. Say Y here only if you are
+	  planning to use hardware trace tools with this kernel.
+
 endmenu
@@ -19,6 +19,7 @@
 generic-y += irq_regs.h
 generic-y += kdebug.h
 generic-y += kmap_types.h
+generic-y += kvm_para.h
 generic-y += local.h
 generic-y += local64.h
 generic-y += mman.h
@@ -48,4 +49,5 @@
 generic-y += types.h
 generic-y += unaligned.h
 generic-y += user.h
+generic-y += xor.h
@@ -49,12 +49,12 @@
 	int result;
  
 	asm volatile("// atomic_add\n"
-"1:	ldxr	%w0, [%3]\n"
-"	add	%w0, %w0, %w4\n"
-"	stxr	%w1, %w0, [%3]\n"
+"1:	ldxr	%w0, %2\n"
+"	add	%w0, %w0, %w3\n"
+"	stxr	%w1, %w0, %2\n"
 "	cbnz	%w1, 1b"
-	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-	: "r" (&v->counter), "Ir" (i)
+	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+	: "Ir" (i)
 	: "cc");
 }
  
  
@@ -64,13 +64,13 @@
 	int result;
  
 	asm volatile("// atomic_add_return\n"
-"1:	ldaxr	%w0, [%3]\n"
-"	add	%w0, %w0, %w4\n"
-"	stlxr	%w1, %w0, [%3]\n"
+"1:	ldaxr	%w0, %2\n"
+"	add	%w0, %w0, %w3\n"
+"	stlxr	%w1, %w0, %2\n"
 "	cbnz	%w1, 1b"
-	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-	: "r" (&v->counter), "Ir" (i)
-	: "cc");
+	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+	: "Ir" (i)
+	: "cc", "memory");
  
 	return result;
 }
  
@@ -81,12 +81,12 @@
 	int result;
  
 	asm volatile("// atomic_sub\n"
-"1:	ldxr	%w0, [%3]\n"
-"	sub	%w0, %w0, %w4\n"
-"	stxr	%w1, %w0, [%3]\n"
+"1:	ldxr	%w0, %2\n"
+"	sub	%w0, %w0, %w3\n"
+"	stxr	%w1, %w0, %2\n"
 "	cbnz	%w1, 1b"
-	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-	: "r" (&v->counter), "Ir" (i)
+	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+	: "Ir" (i)
 	: "cc");
 }
  
  
@@ -96,13 +96,13 @@
 	int result;
  
 	asm volatile("// atomic_sub_return\n"
-"1:	ldaxr	%w0, [%3]\n"
-"	sub	%w0, %w0, %w4\n"
-"	stlxr	%w1, %w0, [%3]\n"
+"1:	ldaxr	%w0, %2\n"
+"	sub	%w0, %w0, %w3\n"
+"	stlxr	%w1, %w0, %2\n"
 "	cbnz	%w1, 1b"
-	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-	: "r" (&v->counter), "Ir" (i)
-	: "cc");
+	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+	: "Ir" (i)
+	: "cc", "memory");
  
 	return result;
 }
  
  
@@ -113,15 +113,15 @@
 	int oldval;
  
 	asm volatile("// atomic_cmpxchg\n"
-"1:	ldaxr	%w1, [%3]\n"
-"	cmp	%w1, %w4\n"
+"1:	ldaxr	%w1, %2\n"
+"	cmp	%w1, %w3\n"
 "	b.ne	2f\n"
-"	stlxr	%w0, %w5, [%3]\n"
+"	stlxr	%w0, %w4, %2\n"
 "	cbnz	%w0, 1b\n"
 "2:"
-	: "=&r" (tmp), "=&r" (oldval), "+o" (ptr->counter)
-	: "r" (&ptr->counter), "Ir" (old), "r" (new)
-	: "cc");
+	: "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
+	: "Ir" (old), "r" (new)
+	: "cc", "memory");
  
 	return oldval;
 }
  
@@ -131,12 +131,12 @@
 	unsigned long tmp, tmp2;
  
 	asm volatile("// atomic_clear_mask\n"
-"1:	ldxr	%0, [%3]\n"
-"	bic	%0, %0, %4\n"
-"	stxr	%w1, %0, [%3]\n"
+"1:	ldxr	%0, %2\n"
+"	bic	%0, %0, %3\n"
+"	stxr	%w1, %0, %2\n"
 "	cbnz	%w1, 1b"
-	: "=&r" (tmp), "=&r" (tmp2), "+o" (*addr)
-	: "r" (addr), "Ir" (mask)
+	: "=&r" (tmp), "=&r" (tmp2), "+Q" (*addr)
+	: "Ir" (mask)
 	: "cc");
 }
  
  
@@ -182,12 +182,12 @@
 	unsigned long tmp;
  
 	asm volatile("// atomic64_add\n"
-"1:	ldxr	%0, [%3]\n"
-"	add	%0, %0, %4\n"
-"	stxr	%w1, %0, [%3]\n"
+"1:	ldxr	%0, %2\n"
+"	add	%0, %0, %3\n"
+"	stxr	%w1, %0, %2\n"
 "	cbnz	%w1, 1b"
-	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-	: "r" (&v->counter), "Ir" (i)
+	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+	: "Ir" (i)
 	: "cc");
 }
  
  
@@ -197,13 +197,13 @@
 	unsigned long tmp;
  
 	asm volatile("// atomic64_add_return\n"
-"1:	ldaxr	%0, [%3]\n"
-"	add	%0, %0, %4\n"
-"	stlxr	%w1, %0, [%3]\n"
+"1:	ldaxr	%0, %2\n"
+"	add	%0, %0, %3\n"
+"	stlxr	%w1, %0, %2\n"
 "	cbnz	%w1, 1b"
-	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-	: "r" (&v->counter), "Ir" (i)
-	: "cc");
+	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+	: "Ir" (i)
+	: "cc", "memory");
  
 	return result;
 }
  
@@ -214,12 +214,12 @@
 	unsigned long tmp;
  
 	asm volatile("// atomic64_sub\n"
-"1:	ldxr	%0, [%3]\n"
-"	sub	%0, %0, %4\n"
-"	stxr	%w1, %0, [%3]\n"
+"1:	ldxr	%0, %2\n"
+"	sub	%0, %0, %3\n"
+"	stxr	%w1, %0, %2\n"
 "	cbnz	%w1, 1b"
-	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-	: "r" (&v->counter), "Ir" (i)
+	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+	: "Ir" (i)
 	: "cc");
 }
  
  
@@ -229,13 +229,13 @@
 	unsigned long tmp;
  
 	asm volatile("// atomic64_sub_return\n"
-"1:	ldaxr	%0, [%3]\n"
-"	sub	%0, %0, %4\n"
-"	stlxr	%w1, %0, [%3]\n"
+"1:	ldaxr	%0, %2\n"
+"	sub	%0, %0, %3\n"
+"	stlxr	%w1, %0, %2\n"
 "	cbnz	%w1, 1b"
-	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-	: "r" (&v->counter), "Ir" (i)
-	: "cc");
+	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+	: "Ir" (i)
+	: "cc", "memory");
  
 	return result;
 }
  
  
@@ -246,15 +246,15 @@
 	unsigned long res;
  
 	asm volatile("// atomic64_cmpxchg\n"
-"1:	ldaxr	%1, [%3]\n"
-"	cmp	%1, %4\n"
+"1:	ldaxr	%1, %2\n"
+"	cmp	%1, %3\n"
 "	b.ne	2f\n"
-"	stlxr	%w0, %5, [%3]\n"
+"	stlxr	%w0, %4, %2\n"
 "	cbnz	%w0, 1b\n"
 "2:"
-	: "=&r" (res), "=&r" (oldval), "+o" (ptr->counter)
-	: "r" (&ptr->counter), "Ir" (old), "r" (new)
-	: "cc");
+	: "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
+	: "Ir" (old), "r" (new)
+	: "cc", "memory");
  
 	return oldval;
 }
  
  
@@ -267,15 +267,15 @@
 	unsigned long tmp;
  
 	asm volatile("// atomic64_dec_if_positive\n"
-"1:	ldaxr	%0, [%3]\n"
+"1:	ldaxr	%0, %2\n"
 "	subs	%0, %0, #1\n"
 "	b.mi	2f\n"
-"	stlxr	%w1, %0, [%3]\n"
+"	stlxr	%w1, %0, %2\n"
 "	cbnz	%w1, 1b\n"
 "2:"
-	: "=&r" (result), "=&r" (tmp), "+o" (v->counter)
-	: "r" (&v->counter)
-	: "cc");
+	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
+	:
+	: "cc", "memory");
  
 	return result;
 }
@@ -29,39 +29,39 @@
 	switch (size) {
 	case 1:
 		asm volatile("//	__xchg1\n"
-		"1:	ldaxrb	%w0, [%3]\n"
-		"	stlxrb	%w1, %w2, [%3]\n"
+		"1:	ldaxrb	%w0, %2\n"
+		"	stlxrb	%w1, %w3, %2\n"
 		"	cbnz	%w1, 1b\n"
-			: "=&r" (ret), "=&r" (tmp)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
+			: "=&r" (ret), "=&r" (tmp), "+Q" (*(u8 *)ptr)
+			: "r" (x)
+			: "cc", "memory");
 		break;
 	case 2:
 		asm volatile("//	__xchg2\n"
-		"1:	ldaxrh	%w0, [%3]\n"
-		"	stlxrh	%w1, %w2, [%3]\n"
+		"1:	ldaxrh	%w0, %2\n"
+		"	stlxrh	%w1, %w3, %2\n"
 		"	cbnz	%w1, 1b\n"
-			: "=&r" (ret), "=&r" (tmp)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
+			: "=&r" (ret), "=&r" (tmp), "+Q" (*(u16 *)ptr)
+			: "r" (x)
+			: "cc", "memory");
 		break;
 	case 4:
 		asm volatile("//	__xchg4\n"
-		"1:	ldaxr	%w0, [%3]\n"
-		"	stlxr	%w1, %w2, [%3]\n"
+		"1:	ldaxr	%w0, %2\n"
+		"	stlxr	%w1, %w3, %2\n"
 		"	cbnz	%w1, 1b\n"
-			: "=&r" (ret), "=&r" (tmp)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
+			: "=&r" (ret), "=&r" (tmp), "+Q" (*(u32 *)ptr)
+			: "r" (x)
+			: "cc", "memory");
 		break;
 	case 8:
 		asm volatile("//	__xchg8\n"
-		"1:	ldaxr	%0, [%3]\n"
-		"	stlxr	%w1, %2, [%3]\n"
+		"1:	ldaxr	%0, %2\n"
+		"	stlxr	%w1, %3, %2\n"
 		"	cbnz	%w1, 1b\n"
-			: "=&r" (ret), "=&r" (tmp)
-			: "r" (x), "r" (ptr)
-			: "memory", "cc");
+			: "=&r" (ret), "=&r" (tmp), "+Q" (*(u64 *)ptr)
+			: "r" (x)
+			: "cc", "memory");
 		break;
 	default:
 		BUILD_BUG();
  
  
@@ -82,14 +82,14 @@
 	case 1:
 		do {
 			asm volatile("// __cmpxchg1\n"
-			"	ldxrb	%w1, [%2]\n"
+			"	ldxrb	%w1, %2\n"
 			"	mov	%w0, #0\n"
 			"	cmp	%w1, %w3\n"
 			"	b.ne	1f\n"
-			"	stxrb	%w0, %w4, [%2]\n"
+			"	stxrb	%w0, %w4, %2\n"
 			"1:\n"
-				: "=&r" (res), "=&r" (oldval)
-				: "r" (ptr), "Ir" (old), "r" (new)
+				: "=&r" (res), "=&r" (oldval), "+Q" (*(u8 *)ptr)
+				: "Ir" (old), "r" (new)
 				: "cc");
 		} while (res);
 		break;
  
  
  
  
  
@@ -97,29 +97,29 @@
 	case 2:
 		do {
 			asm volatile("// __cmpxchg2\n"
-			"	ldxrh	%w1, [%2]\n"
+			"	ldxrh	%w1, %2\n"
 			"	mov	%w0, #0\n"
 			"	cmp	%w1, %w3\n"
 			"	b.ne	1f\n"
-			"	stxrh	%w0, %w4, [%2]\n"
+			"	stxrh	%w0, %w4, %2\n"
 			"1:\n"
-				: "=&r" (res), "=&r" (oldval)
-				: "r" (ptr), "Ir" (old), "r" (new)
-				: "memory", "cc");
+				: "=&r" (res), "=&r" (oldval), "+Q" (*(u16 *)ptr)
+				: "Ir" (old), "r" (new)
+				: "cc");
 		} while (res);
 		break;
  
 	case 4:
 		do {
 			asm volatile("// __cmpxchg4\n"
-			"	ldxr	%w1, [%2]\n"
+			"	ldxr	%w1, %2\n"
 			"	mov	%w0, #0\n"
 			"	cmp	%w1, %w3\n"
 			"	b.ne	1f\n"
-			"	stxr	%w0, %w4, [%2]\n"
+			"	stxr	%w0, %w4, %2\n"
 			"1:\n"
-				: "=&r" (res), "=&r" (oldval)
-				: "r" (ptr), "Ir" (old), "r" (new)
+				: "=&r" (res), "=&r" (oldval), "+Q" (*(u32 *)ptr)
+				: "Ir" (old), "r" (new)
 				: "cc");
 		} while (res);
 		break;
  
  
@@ -127,14 +127,14 @@
 	case 8:
 		do {
 			asm volatile("// __cmpxchg8\n"
-			"	ldxr	%1, [%2]\n"
+			"	ldxr	%1, %2\n"
 			"	mov	%w0, #0\n"
 			"	cmp	%1, %3\n"
 			"	b.ne	1f\n"
-			"	stxr	%w0, %4, [%2]\n"
+			"	stxr	%w0, %4, %2\n"
 			"1:\n"
-				: "=&r" (res), "=&r" (oldval)
-				: "r" (ptr), "Ir" (old), "r" (new)
+				: "=&r" (res), "=&r" (oldval), "+Q" (*(u64 *)ptr)
+				: "Ir" (old), "r" (new)
 				: "cc");
 		} while (res);
 		break;
@@ -39,7 +39,7 @@
 "	.popsection\n"							\
 	: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp)	\
 	: "r" (oparg), "Ir" (-EFAULT)					\
-	: "cc")
+	: "cc", "memory")
  
 static inline int
 futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
@@ -230,6 +230,9 @@
 #define ioremap_wc(addr, size)		__ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
 #define iounmap				__iounmap
  
+#define PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF)
+#define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PTE_PXN | PTE_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
+
 #define ARCH_HAS_IOREMAP_WC
 #include <asm-generic/iomap.h>
  
@@ -43,6 +43,7 @@
 #define PAGE_OFFSET		UL(0xffffffc000000000)
 #define MODULES_END		(PAGE_OFFSET)
 #define MODULES_VADDR		(MODULES_END - SZ_64M)
+#define EARLYCON_IOBASE		(MODULES_VADDR - SZ_4M)
 #define VA_BITS			(39)
 #define TASK_SIZE_64		(UL(1) << VA_BITS)
  
@@ -26,6 +26,7 @@
  
 extern void paging_init(void);
 extern void setup_mm_for_reboot(void);
+extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
  
 #endif
@@ -35,6 +35,21 @@
 void __init_new_context(struct task_struct *tsk, struct mm_struct *mm);
 void __new_context(struct mm_struct *mm);
  
+#ifdef CONFIG_PID_IN_CONTEXTIDR
+static inline void contextidr_thread_switch(struct task_struct *next)
+{
+	asm(
+	"	msr	contextidr_el1, %0\n"
+	"	isb"
+	:
+	: "r" (task_pid_nr(next)));
+}
+#else
+static inline void contextidr_thread_switch(struct task_struct *next)
+{
+}
+#endif
+
 /*
  * Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
  */
@@ -17,7 +17,12 @@
 #ifndef __ASM_PERF_EVENT_H
 #define __ASM_PERF_EVENT_H
  
-/* It's quiet around here... */
+#ifdef CONFIG_HW_PERF_EVENTS
+struct pt_regs;
+extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
+extern unsigned long perf_misc_flags(struct pt_regs *regs);
+#define perf_misc_flags(regs)	perf_misc_flags(regs)
+#endif
  
 #endif
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 ARM Limited
+ */
+
+#ifndef __ASM_PSCI_H
+#define __ASM_PSCI_H
+
+#define PSCI_POWER_STATE_TYPE_STANDBY		0
+#define PSCI_POWER_STATE_TYPE_POWER_DOWN	1
+
+struct psci_power_state {
+	u16	id;
+	u8	type;
+	u8	affinity_level;
+};
+
+struct psci_operations {
+	int (*cpu_suspend)(struct psci_power_state state,
+			   unsigned long entry_point);
+	int (*cpu_off)(struct psci_power_state state);
+	int (*cpu_on)(unsigned long cpuid, unsigned long entry_point);
+	int (*migrate)(unsigned long cpuid);
+};
+
+extern struct psci_operations psci_ops;
+
+int psci_init(void);
+
+#endif /* __ASM_PSCI_H */
@@ -42,6 +42,16 @@
 #define COMPAT_PSR_MODE_UND	0x0000001b
 #define COMPAT_PSR_MODE_SYS	0x0000001f
 #define COMPAT_PSR_T_BIT	0x00000020
+#define COMPAT_PSR_F_BIT	0x00000040
+#define COMPAT_PSR_I_BIT	0x00000080
+#define COMPAT_PSR_A_BIT	0x00000100
+#define COMPAT_PSR_E_BIT	0x00000200
+#define COMPAT_PSR_J_BIT	0x01000000
+#define COMPAT_PSR_Q_BIT	0x08000000
+#define COMPAT_PSR_V_BIT	0x10000000
+#define COMPAT_PSR_C_BIT	0x20000000
+#define COMPAT_PSR_Z_BIT	0x40000000
+#define COMPAT_PSR_N_BIT	0x80000000
 #define COMPAT_PSR_IT_MASK	0x0600fc00	/* If-Then execution state mask */
 /*
  * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
@@ -66,5 +66,16 @@
 extern void arch_send_call_function_single_ipi(int cpu);
 extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
  
+struct device_node;
+
+struct smp_enable_ops {
+	const char	*name;
+	int		(*init_cpu)(struct device_node *, int);
+	int		(*prepare_cpu)(int);
+};
+
+extern const struct smp_enable_ops smp_spin_table_ops;
+extern const struct smp_enable_ops smp_psci_ops;
+
 #endif /* ifndef __ASM_SMP_H */
@@ -45,13 +45,13 @@
 	asm volatile(
 	"	sevl\n"
 	"1:	wfe\n"
-	"2:	ldaxr	%w0, [%1]\n"
+	"2:	ldaxr	%w0, %1\n"
 	"	cbnz	%w0, 1b\n"
-	"	stxr	%w0, %w2, [%1]\n"
+	"	stxr	%w0, %w2, %1\n"
 	"	cbnz	%w0, 2b\n"
-	: "=&r" (tmp)
-	: "r" (&lock->lock), "r" (1)
-	: "memory");
+	: "=&r" (tmp), "+Q" (lock->lock)
+	: "r" (1)
+	: "cc", "memory");
 }
  
 static inline int arch_spin_trylock(arch_spinlock_t *lock)
  
  
@@ -59,13 +59,13 @@
 	unsigned int tmp;
  
 	asm volatile(
-	"	ldaxr	%w0, [%1]\n"
+	"	ldaxr	%w0, %1\n"
 	"	cbnz	%w0, 1f\n"
-	"	stxr	%w0, %w2, [%1]\n"
+	"	stxr	%w0, %w2, %1\n"
 	"1:\n"
-	: "=&r" (tmp)
-	: "r" (&lock->lock), "r" (1)
-	: "memory");
+	: "=&r" (tmp), "+Q" (lock->lock)
+	: "r" (1)
+	: "cc", "memory");
  
 	return !tmp;
 }
@@ -73,8 +73,8 @@
 static inline void arch_spin_unlock(arch_spinlock_t *lock)
 {
 	asm volatile(
-	"	stlr	%w1, [%0]\n"
-	: : "r" (&lock->lock), "r" (0) : "memory");
+	"	stlr	%w1, %0\n"
+	: "=Q" (lock->lock) : "r" (0) : "memory");
 }
  
 /*
  
  
@@ -94,13 +94,13 @@
 	asm volatile(
 	"	sevl\n"
 	"1:	wfe\n"
-	"2:	ldaxr	%w0, [%1]\n"
+	"2:	ldaxr	%w0, %1\n"
 	"	cbnz	%w0, 1b\n"
-	"	stxr	%w0, %w2, [%1]\n"
+	"	stxr	%w0, %w2, %1\n"
 	"	cbnz	%w0, 2b\n"
-	: "=&r" (tmp)
-	: "r" (&rw->lock), "r" (0x80000000)
-	: "memory");
+	: "=&r" (tmp), "+Q" (rw->lock)
+	: "r" (0x80000000)
+	: "cc", "memory");
 }
  
 static inline int arch_write_trylock(arch_rwlock_t *rw)
  
  
@@ -108,13 +108,13 @@
 	unsigned int tmp;
  
 	asm volatile(
-	"	ldaxr	%w0, [%1]\n"
+	"	ldaxr	%w0, %1\n"
 	"	cbnz	%w0, 1f\n"
-	"	stxr	%w0, %w2, [%1]\n"
+	"	stxr	%w0, %w2, %1\n"
 	"1:\n"
-	: "=&r" (tmp)
-	: "r" (&rw->lock), "r" (0x80000000)
-	: "memory");
+	: "=&r" (tmp), "+Q" (rw->lock)
+	: "r" (0x80000000)
+	: "cc", "memory");
  
 	return !tmp;
 }
@@ -122,8 +122,8 @@
 static inline void arch_write_unlock(arch_rwlock_t *rw)
 {
 	asm volatile(
-	"	stlr	%w1, [%0]\n"
-	: : "r" (&rw->lock), "r" (0) : "memory");
+	"	stlr	%w1, %0\n"
+	: "=Q" (rw->lock) : "r" (0) : "memory");
 }
  
 /* write_can_lock - would write_trylock() succeed? */
  
  
@@ -148,14 +148,14 @@
 	asm volatile(
 	"	sevl\n"
 	"1:	wfe\n"
-	"2:	ldaxr	%w0, [%2]\n"
+	"2:	ldaxr	%w0, %2\n"
 	"	add	%w0, %w0, #1\n"
 	"	tbnz	%w0, #31, 1b\n"
-	"	stxr	%w1, %w0, [%2]\n"
+	"	stxr	%w1, %w0, %2\n"
 	"	cbnz	%w1, 2b\n"
-	: "=&r" (tmp), "=&r" (tmp2)
-	: "r" (&rw->lock)
-	: "memory");
+	: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
+	:
+	: "cc", "memory");
 }
  
 static inline void arch_read_unlock(arch_rwlock_t *rw)
  
  
@@ -163,13 +163,13 @@
 	unsigned int tmp, tmp2;
  
 	asm volatile(
-	"1:	ldxr	%w0, [%2]\n"
+	"1:	ldxr	%w0, %2\n"
 	"	sub	%w0, %w0, #1\n"
-	"	stlxr	%w1, %w0, [%2]\n"
+	"	stlxr	%w1, %w0, %2\n"
 	"	cbnz	%w1, 1b\n"
-	: "=&r" (tmp), "=&r" (tmp2)
-	: "r" (&rw->lock)
-	: "memory");
+	: "=&r" (tmp), "=&r" (tmp2), "+Q" (rw->lock)
+	:
+	: "cc", "memory");
 }
  
 static inline int arch_read_trylock(arch_rwlock_t *rw)
  
  
@@ -177,14 +177,14 @@
 	unsigned int tmp, tmp2 = 1;
  
 	asm volatile(
-	"	ldaxr	%w0, [%2]\n"
+	"	ldaxr	%w0, %2\n"
 	"	add	%w0, %w0, #1\n"
 	"	tbnz	%w0, #31, 1f\n"
-	"	stxr	%w1, %w0, [%2]\n"
+	"	stxr	%w1, %w0, %2\n"
 	"1:\n"
-	: "=&r" (tmp), "+r" (tmp2)
-	: "r" (&rw->lock)
-	: "memory");
+	: "=&r" (tmp), "+r" (tmp2), "+Q" (rw->lock)
+	:
+	: "cc", "memory");
  
 	return !tmp2;
 }
 # UAPI Header export list
 include include/uapi/asm-generic/Kbuild.asm
  
+generic-y += kvm_para.h
+
 header-y += auxvec.h
 header-y += bitsperlong.h
 header-y += byteorder.h
 header-y += fcntl.h
 header-y += hwcap.h
+header-y += kvm_para.h
 header-y += param.h
 header-y += ptrace.h
 header-y += setup.h
@@ -9,14 +9,15 @@
 arm64-obj-y		:= cputable.o debug-monitors.o entry.o irq.o fpsimd.o	\
 			   entry-fpsimd.o process.o ptrace.o setup.o signal.o	\
 			   sys.o stacktrace.o time.o traps.o io.o vdso.o	\
-			   hyp-stub.o
+			   hyp-stub.o psci.o
  
 arm64-obj-$(CONFIG_COMPAT)		+= sys32.o kuser32.o signal32.o 	\
 					   sys_compat.o
 arm64-obj-$(CONFIG_MODULES)		+= arm64ksyms.o module.o
-arm64-obj-$(CONFIG_SMP)			+= smp.o
+arm64-obj-$(CONFIG_SMP)			+= smp.o smp_spin_table.o smp_psci.o
 arm64-obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event.o
 arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT)+= hw_breakpoint.o
+arm64-obj-$(CONFIG_EARLY_PRINTK)	+= early_printk.o
  
 obj-y					+= $(arm64-obj-y) vdso/
 obj-m					+= $(arm64-obj-m)
+/*
+ * Earlyprintk support.
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Author: Catalin Marinas <catalin.marinas@arm.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/io.h>
+
+#include <linux/amba/serial.h>
+
+static void __iomem *early_base;
+static void (*printch)(char ch);
+
+/*
+ * PL011 single character TX.
+ */
+static void pl011_printch(char ch)
+{
+	while (readl_relaxed(early_base + UART01x_FR) & UART01x_FR_TXFF)
+		;
+	writeb_relaxed(ch, early_base + UART01x_DR);
+	while (readl_relaxed(early_base + UART01x_FR) & UART01x_FR_BUSY)
+		;
+}
+
+struct earlycon_match {
+	const char *name;
+	void (*printch)(char ch);
+};
+
+static const struct earlycon_match earlycon_match[] __initconst = {
+	{ .name = "pl011", .printch = pl011_printch, },
+	{}
+};
+
+static void early_write(struct console *con, const char *s, unsigned n)
+{
+	while (n-- > 0) {
+		if (*s == '\n')
+			printch('\r');
+		printch(*s);
+		s++;
+	}
+}
+
+static struct console early_console = {
+	.name =		"earlycon",
+	.write =	early_write,
+	.flags =	CON_PRINTBUFFER | CON_BOOT,
+	.index =	-1,
+};
+
+/*
+ * Parse earlyprintk=... parameter in the format:
+ *
+ *   <name>[,<addr>][,<options>]
+ *
+ * and register the early console. It is assumed that the UART has been
+ * initialised by the bootloader already.
+ */
+static int __init setup_early_printk(char *buf)
+{
+	const struct earlycon_match *match = earlycon_match;
+	phys_addr_t paddr = 0;
+
+	if (!buf) {
+		pr_warning("No earlyprintk arguments passed.\n");
+		return 0;
+	}
+
+	while (match->name) {
+		size_t len = strlen(match->name);
+		if (!strncmp(buf, match->name, len)) {
+			buf += len;
+			break;
+		}
+		match++;
+	}
+	if (!match->name) {
+		pr_warning("Unknown earlyprintk arguments: %s\n", buf);
+		return 0;
+	}
+
+	/* I/O address */
+	if (!strncmp(buf, ",0x", 3)) {
+		char *e;
+		paddr = simple_strtoul(buf + 1, &e, 16);
+		buf = e;
+	}
+	/* no options parsing yet */
+
+	if (paddr)
+		early_base = early_io_map(paddr, EARLYCON_IOBASE);
+
+	printch = match->printch;
+	register_console(&early_console);
+
+	return 0;
+}
+
+early_param("earlyprintk", setup_early_printk);
@@ -82,10 +82,8 @@
  
 #ifdef CONFIG_ARM64_64K_PAGES
 #define MM_MMUFLAGS	PTE_ATTRINDX(MT_NORMAL) | PTE_FLAGS
-#define IO_MMUFLAGS	PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_XN | PTE_FLAGS
 #else
 #define MM_MMUFLAGS	PMD_ATTRINDX(MT_NORMAL) | PMD_FLAGS
-#define IO_MMUFLAGS	PMD_ATTRINDX(MT_DEVICE_nGnRE) | PMD_SECT_XN | PMD_FLAGS
 #endif
  
 /*
@@ -368,6 +366,7 @@
  *   - identity mapping to enable the MMU (low address, TTBR0)
  *   - first few MB of the kernel linear mapping to jump to once the MMU has
  *     been enabled, including the FDT blob (TTBR1)
+ *   - UART mapping if CONFIG_EARLY_PRINTK is enabled (TTBR1)
  */
 __create_page_tables:
 	pgtbl	x25, x26, x24			// idmap_pg_dir and swapper_pg_dir addresses
@@ -420,6 +419,15 @@
 	sub	x6, x6, #1			// inclusive range
 	create_block_map x0, x7, x3, x5, x6
 1:
+#ifdef CONFIG_EARLY_PRINTK
+	/*
+	 * Create the pgd entry for the UART mapping. The full mapping is done
+	 * later based earlyprintk kernel parameter.
+	 */
+	ldr	x5, =EARLYCON_IOBASE		// UART virtual address
+	add	x0, x26, #2 * PAGE_SIZE		// section table address
+	create_pgd_entry x26, x0, x5, x6, x7
+#endif
 	ret
 ENDPROC(__create_page_tables)
 	.ltorg
@@ -1331,6 +1331,11 @@
 {
 	struct frame_tail __user *tail;
  
+	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+		/* We don't support guest os callchain now */
+		return;
+	}
+
 	tail = (struct frame_tail __user *)regs->regs[29];
  
 	while (entry->nr < PERF_MAX_STACK_DEPTH &&
  
@@ -1355,9 +1360,41 @@
 {
 	struct stackframe frame;
  
+	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+		/* We don't support guest os callchain now */
+		return;
+	}
+
 	frame.fp = regs->regs[29];
 	frame.sp = regs->sp;
 	frame.pc = regs->pc;
 	walk_stackframe(&frame, callchain_trace, entry);
+}
+
+unsigned long perf_instruction_pointer(struct pt_regs *regs)
+{
+	if (perf_guest_cbs && perf_guest_cbs->is_in_guest())
+		return perf_guest_cbs->get_guest_ip();
+
+	return instruction_pointer(regs);
+}
+
+unsigned long perf_misc_flags(struct pt_regs *regs)
+{
+	int misc = 0;
+
+	if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
+		if (perf_guest_cbs->is_user_mode())
+			misc |= PERF_RECORD_MISC_GUEST_USER;
+		else
+			misc |= PERF_RECORD_MISC_GUEST_KERNEL;
+	} else {
+		if (user_mode(regs))
+			misc |= PERF_RECORD_MISC_USER;
+		else
+			misc |= PERF_RECORD_MISC_KERNEL;
+	}
+
+	return misc;
 }
@@ -45,9 +45,10 @@
  
 #include <asm/compat.h>
 #include <asm/cacheflush.h>
+#include <asm/fpsimd.h>
+#include <asm/mmu_context.h>
 #include <asm/processor.h>
 #include <asm/stacktrace.h>
-#include <asm/fpsimd.h>
  
 static void setup_restart(void)
 {
@@ -314,6 +315,7 @@
 	/* the actual thread switch */
 	last = cpu_switch_to(prev, next);
  
+	contextidr_thread_switch(next);
 	return last;
 }
  
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2013 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+
+#define pr_fmt(fmt) "psci: " fmt
+
+#include <linux/init.h>
+#include <linux/of.h>
+
+#include <asm/compiler.h>
+#include <asm/errno.h>
+#include <asm/psci.h>
+
+struct psci_operations psci_ops;
+
+static int (*invoke_psci_fn)(u64, u64, u64, u64);
+
+enum psci_function {
+	PSCI_FN_CPU_SUSPEND,
+	PSCI_FN_CPU_ON,
+	PSCI_FN_CPU_OFF,
+	PSCI_FN_MIGRATE,
+	PSCI_FN_MAX,
+};
+
+static u32 psci_function_id[PSCI_FN_MAX];
+
+#define PSCI_RET_SUCCESS		0
+#define PSCI_RET_EOPNOTSUPP		-1
+#define PSCI_RET_EINVAL			-2
+#define PSCI_RET_EPERM			-3
+
+static int psci_to_linux_errno(int errno)
+{
+	switch (errno) {
+	case PSCI_RET_SUCCESS:
+		return 0;
+	case PSCI_RET_EOPNOTSUPP:
+		return -EOPNOTSUPP;
+	case PSCI_RET_EINVAL:
+		return -EINVAL;
+	case PSCI_RET_EPERM:
+		return -EPERM;
+	};
+
+	return -EINVAL;
+}
+
+#define PSCI_POWER_STATE_ID_MASK	0xffff
+#define PSCI_POWER_STATE_ID_SHIFT	0
+#define PSCI_POWER_STATE_TYPE_MASK	0x1
+#define PSCI_POWER_STATE_TYPE_SHIFT	16
+#define PSCI_POWER_STATE_AFFL_MASK	0x3
+#define PSCI_POWER_STATE_AFFL_SHIFT	24
+
+static u32 psci_power_state_pack(struct psci_power_state state)
+{
+	return	((state.id & PSCI_POWER_STATE_ID_MASK)
+			<< PSCI_POWER_STATE_ID_SHIFT)	|
+		((state.type & PSCI_POWER_STATE_TYPE_MASK)
+			<< PSCI_POWER_STATE_TYPE_SHIFT)	|
+		((state.affinity_level & PSCI_POWER_STATE_AFFL_MASK)
+			<< PSCI_POWER_STATE_AFFL_SHIFT);
+}
+
+/*
+ * The following two functions are invoked via the invoke_psci_fn pointer
+ * and will not be inlined, allowing us to piggyback on the AAPCS.
+ */
+static noinline int __invoke_psci_fn_hvc(u64 function_id, u64 arg0, u64 arg1,
+					 u64 arg2)
+{
+	asm volatile(
+			__asmeq("%0", "x0")
+			__asmeq("%1", "x1")
+			__asmeq("%2", "x2")
+			__asmeq("%3", "x3")
+			"hvc	#0\n"
+		: "+r" (function_id)
+		: "r" (arg0), "r" (arg1), "r" (arg2));
+
+	return function_id;
+}
+
+static noinline int __invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
+					 u64 arg2)
+{
+	asm volatile(
+			__asmeq("%0", "x0")
+			__asmeq("%1", "x1")
+			__asmeq("%2", "x2")
+			__asmeq("%3", "x3")
+			"smc	#0\n"
+		: "+r" (function_id)
+		: "r" (arg0), "r" (arg1), "r" (arg2));
+
+	return function_id;
+}
+
+static int psci_cpu_suspend(struct psci_power_state state,
+			    unsigned long entry_point)
+{
+	int err;
+	u32 fn, power_state;
+
+	fn = psci_function_id[PSCI_FN_CPU_SUSPEND];
+	power_state = psci_power_state_pack(state);
+	err = invoke_psci_fn(fn, power_state, entry_point, 0);
+	return psci_to_linux_errno(err);
+}
+
+static int psci_cpu_off(struct psci_power_state state)
+{
+	int err;
+	u32 fn, power_state;
+
+	fn = psci_function_id[PSCI_FN_CPU_OFF];
+	power_state = psci_power_state_pack(state);
+	err = invoke_psci_fn(fn, power_state, 0, 0);
+	return psci_to_linux_errno(err);
+}
+
+static int psci_cpu_on(unsigned long cpuid, unsigned long entry_point)
+{
+	int err;
+	u32 fn;
+
+	fn = psci_function_id[PSCI_FN_CPU_ON];
+	err = invoke_psci_fn(fn, cpuid, entry_point, 0);
+	return psci_to_linux_errno(err);
+}
+
+static int psci_migrate(unsigned long cpuid)
+{
+	int err;
+	u32 fn;
+
+	fn = psci_function_id[PSCI_FN_MIGRATE];
+	err = invoke_psci_fn(fn, cpuid, 0, 0);
+	return psci_to_linux_errno(err);
+}
+
+static const struct of_device_id psci_of_match[] __initconst = {
+	{ .compatible = "arm,psci",	},
+	{},
+};
+
+int __init psci_init(void)
+{
+	struct device_node *np;
+	const char *method;
+	u32 id;
+	int err = 0;
+
+	np = of_find_matching_node(NULL, psci_of_match);
+	if (!np)
+		return -ENODEV;
+
+	pr_info("probing function IDs from device-tree\n");
+
+	if (of_property_read_string(np, "method", &method)) {
+		pr_warning("missing \"method\" property\n");
+		err = -ENXIO;
+		goto out_put_node;
+	}
+
+	if (!strcmp("hvc", method)) {
+		invoke_psci_fn = __invoke_psci_fn_hvc;
+	} else if (!strcmp("smc", method)) {
+		invoke_psci_fn = __invoke_psci_fn_smc;
+	} else {
+		pr_warning("invalid \"method\" property: %s\n", method);
+		err = -EINVAL;
+		goto out_put_node;
+	}
+
+	if (!of_property_read_u32(np, "cpu_suspend", &id)) {
+		psci_function_id[PSCI_FN_CPU_SUSPEND] = id;
+		psci_ops.cpu_suspend = psci_cpu_suspend;
+	}
+
+	if (!of_property_read_u32(np, "cpu_off", &id)) {
+		psci_function_id[PSCI_FN_CPU_OFF] = id;
+		psci_ops.cpu_off = psci_cpu_off;
+	}
+
+	if (!of_property_read_u32(np, "cpu_on", &id)) {
+		psci_function_id[PSCI_FN_CPU_ON] = id;
+		psci_ops.cpu_on = psci_cpu_on;
+	}
+
+	if (!of_property_read_u32(np, "migrate", &id)) {
+		psci_function_id[PSCI_FN_MIGRATE] = id;
+		psci_ops.migrate = psci_migrate;
+	}
+
+out_put_node:
+	of_node_put(np);
+	return err;
+}
@@ -39,6 +39,7 @@
 #include <linux/proc_fs.h>
 #include <linux/memblock.h>
 #include <linux/of_fdt.h>
+#include <linux/of_platform.h>
  
 #include <asm/cputype.h>
 #include <asm/elf.h>
@@ -49,6 +50,7 @@
 #include <asm/tlbflush.h>
 #include <asm/traps.h>
 #include <asm/memblock.h>
+#include <asm/psci.h>
  
 unsigned int processor_id;
 EXPORT_SYMBOL(processor_id);
@@ -260,6 +262,8 @@
  
 	unflatten_device_tree();
  
+	psci_init();
+
 #ifdef CONFIG_SMP
 	smp_init_cpus();
 #endif
@@ -288,6 +292,13 @@
 	return 0;
 }
 subsys_initcall(topology_init);
+
+static int __init arm64_device_probe(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+	return 0;
+}
+device_initcall(arm64_device_probe);
  
 static const char *hwcap_str[] = {
 	"fp",
@@ -76,7 +76,7 @@
  
 struct compat_ucontext {
 	compat_ulong_t			uc_flags;
-	struct compat_ucontext		*uc_link;
+	compat_uptr_t			uc_link;
 	compat_stack_t			uc_stack;
 	struct compat_sigcontext	uc_mcontext;
 	compat_sigset_t			uc_sigmask;
@@ -703,7 +703,7 @@
 	err |= copy_siginfo_to_user32(&frame->info, info);
  
 	__put_user_error(0, &frame->sig.uc.uc_flags, err);
-	__put_user_error(NULL, &frame->sig.uc.uc_link, err);
+	__put_user_error(0, &frame->sig.uc.uc_link, err);
  
 	memset(&stack, 0, sizeof(stack));
 	stack.ss_sp = (compat_uptr_t)current->sas_ss_sp;
@@ -233,8 +233,29 @@
 }
  
 static void (*smp_cross_call)(const struct cpumask *, unsigned int);
-static phys_addr_t cpu_release_addr[NR_CPUS];
  
+static const struct smp_enable_ops *enable_ops[] __initconst = {
+	&smp_spin_table_ops,
+	&smp_psci_ops,
+	NULL,
+};
+
+static const struct smp_enable_ops *smp_enable_ops[NR_CPUS];
+
+static const struct smp_enable_ops * __init smp_get_enable_ops(const char *name)
+{
+	const struct smp_enable_ops *ops = enable_ops[0];
+
+	while (ops) {
+		if (!strcmp(name, ops->name))
+			return ops;
+
+		ops++;
+	}
+
+	return NULL;
+}
+
 /*
  * Enumerate the possible CPU set from the device tree.
  */
  
  
@@ -252,22 +273,22 @@
 		 * We currently support only the "spin-table" enable-method.
 		 */
 		enable_method = of_get_property(dn, "enable-method", NULL);
-		if (!enable_method || strcmp(enable_method, "spin-table")) {
-			pr_err("CPU %d: missing or invalid enable-method property: %s\n",
-			       cpu, enable_method);
+		if (!enable_method) {
+			pr_err("CPU %d: missing enable-method property\n", cpu);
 			goto next;
 		}
  
-		/*
-		 * Determine the address from which the CPU is polling.
-		 */
-		if (of_property_read_u64(dn, "cpu-release-addr",
-					 &cpu_release_addr[cpu])) {
-			pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
-			       cpu);
+		smp_enable_ops[cpu] = smp_get_enable_ops(enable_method);
+
+		if (!smp_enable_ops[cpu]) {
+			pr_err("CPU %d: invalid enable-method property: %s\n",
+			       cpu, enable_method);
 			goto next;
 		}
  
+		if (smp_enable_ops[cpu]->init_cpu(dn, cpu))
+			goto next;
+
 		set_cpu_possible(cpu, true);
 next:
 		cpu++;
@@ -281,8 +302,7 @@
  
 void __init smp_prepare_cpus(unsigned int max_cpus)
 {
-	int cpu;
-	void **release_addr;
+	int cpu, err;
 	unsigned int ncores = num_possible_cpus();
  
 	/*
  
  
  
  
  
  
@@ -291,30 +311,35 @@
 	if (max_cpus > ncores)
 		max_cpus = ncores;
  
+	/* Don't bother if we're effectively UP */
+	if (max_cpus <= 1)
+		return;
+
 	/*
 	 * Initialise the present map (which describes the set of CPUs
 	 * actually populated at the present time) and release the
 	 * secondaries from the bootloader.
+	 *
+	 * Make sure we online at most (max_cpus - 1) additional CPUs.
 	 */
+	max_cpus--;
 	for_each_possible_cpu(cpu) {
 		if (max_cpus == 0)
 			break;
  
-		if (!cpu_release_addr[cpu])
+		if (cpu == smp_processor_id())
 			continue;
  
-		release_addr = __va(cpu_release_addr[cpu]);
-		release_addr[0] = (void *)__pa(secondary_holding_pen);
-		__flush_dcache_area(release_addr, sizeof(release_addr[0]));
+		if (!smp_enable_ops[cpu])
+			continue;
  
+		err = smp_enable_ops[cpu]->prepare_cpu(cpu);
+		if (err)
+			continue;
+
 		set_cpu_present(cpu, true);
 		max_cpus--;
 	}
-
-	/*
-	 * Send an event to wake up the secondaries.
-	 */
-	sev();
 }
  
  
+/*
+ * PSCI SMP initialisation
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/smp.h>
+
+#include <asm/psci.h>
+
+static int __init smp_psci_init_cpu(struct device_node *dn, int cpu)
+{
+	return 0;
+}
+
+static int __init smp_psci_prepare_cpu(int cpu)
+{
+	int err;
+
+	if (!psci_ops.cpu_on) {
+		pr_err("psci: no cpu_on method, not booting CPU%d\n", cpu);
+		return -ENODEV;
+	}
+
+	err = psci_ops.cpu_on(cpu, __pa(secondary_holding_pen));
+	if (err) {
+		pr_err("psci: failed to boot CPU%d (%d)\n", cpu, err);
+		return err;
+	}
+
+	return 0;
+}
+
+const struct smp_enable_ops smp_psci_ops __initconst = {
+	.name		= "psci",
+	.init_cpu 	= smp_psci_init_cpu,
+	.prepare_cpu	= smp_psci_prepare_cpu,
+};
+/*
+ * Spin Table SMP initialisation
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/smp.h>
+
+#include <asm/cacheflush.h>
+
+static phys_addr_t cpu_release_addr[NR_CPUS];
+
+static int __init smp_spin_table_init_cpu(struct device_node *dn, int cpu)
+{
+	/*
+	 * Determine the address from which the CPU is polling.
+	 */
+	if (of_property_read_u64(dn, "cpu-release-addr",
+				 &cpu_release_addr[cpu])) {
+		pr_err("CPU %d: missing or invalid cpu-release-addr property\n",
+		       cpu);
+
+		return -1;
+	}
+
+	return 0;
+}
+
+static int __init smp_spin_table_prepare_cpu(int cpu)
+{
+	void **release_addr;
+
+	if (!cpu_release_addr[cpu])
+		return -ENODEV;
+
+	release_addr = __va(cpu_release_addr[cpu]);
+	release_addr[0] = (void *)__pa(secondary_holding_pen);
+	__flush_dcache_area(release_addr, sizeof(release_addr[0]));
+
+	/*
+	 * Send an event to wake up the secondary CPU.
+	 */
+	sev();
+
+	return 0;
+}
+
+const struct smp_enable_ops smp_spin_table_ops __initconst = {
+	.name		= "spin-table",
+	.init_cpu 	= smp_spin_table_init_cpu,
+	.prepare_cpu	= smp_spin_table_prepare_cpu,
+};
@@ -25,6 +25,7 @@
 #include <linux/nodemask.h>
 #include <linux/memblock.h>
 #include <linux/fs.h>
+#include <linux/io.h>
  
 #include <asm/cputype.h>
 #include <asm/sections.h>
@@ -250,6 +251,47 @@
 		phys += next - addr;
 	} while (pgd++, addr = next, addr != end);
 }
+
+#ifdef CONFIG_EARLY_PRINTK
+/*
+ * Create an early I/O mapping using the pgd/pmd entries already populated
+ * in head.S as this function is called too early to allocated any memory. The
+ * mapping size is 2MB with 4KB pages or 64KB or 64KB pages.
+ */
+void __iomem * __init early_io_map(phys_addr_t phys, unsigned long virt)
+{
+	unsigned long size, mask;
+	bool page64k = IS_ENABLED(ARM64_64K_PAGES);
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd;
+	pte_t *pte;
+
+	/*
+	 * No early pte entries with !ARM64_64K_PAGES configuration, so using
+	 * sections (pmd).
+	 */
+	size = page64k ? PAGE_SIZE : SECTION_SIZE;
+	mask = ~(size - 1);
+
+	pgd = pgd_offset_k(virt);
+	pud = pud_offset(pgd, virt);
+	if (pud_none(*pud))
+		return NULL;
+	pmd = pmd_offset(pud, virt);
+
+	if (page64k) {
+		if (pmd_none(*pmd))
+			return NULL;
+		pte = pte_offset_kernel(pmd, virt);
+		set_pte(pte, __pte((phys & mask) | PROT_DEVICE_nGnRE));
+	} else {
+		set_pmd(pmd, __pmd((phys & mask) | PROT_SECT_DEVICE_nGnRE));
+	}
+
+	return (void __iomem *)((virt & mask) + (phys & ~mask));
+}
+#endif
  
 static void __init map_mem(void)
 {
...	...	@@ -35,6 +35,8 @@
35	35
36	36	ffffffbe00000000 ffffffbffbbfffff ~8GB [guard, future vmmemap]
37	37
	38	+ffffffbffbc00000 ffffffbffbdfffff 2MB earlyprintk device
	39	+
38	40	ffffffbffbe00000 ffffffbffbe0ffff 64KB PCI I/O space
39	41
40	42	ffffffbbffff0000 ffffffbcffffffff ~2MB [guard]
...	...	@@ -2,6 +2,7 @@
2	2	def_bool y
3	3	select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
4	4	select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
	5	+ select ARCH_WANT_FRAME_POINTERS
5	6	select ARM_AMBA
6	7	select CLONE_BACKWARDS
7	8	select COMMON_CLK
...	...	@@ -24,5 +24,22 @@
24	24	Enables the display of the minimum amount of free stack which each
25	25	task has ever had available in the sysrq-T output.
26	26
	27	+config EARLY_PRINTK
	28	+ bool "Early printk support"
	29	+ default y
	30	+ help
	31	+ Say Y here if you want to have an early console using the
	32	+ earlyprintk=<name>[,<addr>][,<options>] kernel parameter. It
	33	+ is assumed that the early console device has been initialised
	34	+ by the boot loader prior to starting the Linux kernel.
	35	+
	36	+config PID_IN_CONTEXTIDR
	37	+ bool "Write the current PID to the CONTEXTIDR register"
	38	+ help
	39	+ Enabling this option causes the kernel to write the current PID to
	40	+ the CONTEXTIDR register, at the expense of some additional
	41	+ instructions during context switch. Say Y here only if you are
	42	+ planning to use hardware trace tools with this kernel.
	43	+
27	44	endmenu
...	...	@@ -19,6 +19,7 @@
19	19	generic-y += irq_regs.h
20	20	generic-y += kdebug.h
21	21	generic-y += kmap_types.h
	22	+generic-y += kvm_para.h
22	23	generic-y += local.h
23	24	generic-y += local64.h
24	25	generic-y += mman.h
...	...	@@ -48,4 +49,5 @@
48	49	generic-y += types.h
49	50	generic-y += unaligned.h
50	51	generic-y += user.h
	52	+generic-y += xor.h
...	...	@@ -49,12 +49,12 @@
49	49	int result;
50	50
51	51	asm volatile("// atomic_add\n"
52		-"1: ldxr %w0, [%3]\n"
53		-" add %w0, %w0, %w4\n"
54		-" stxr %w1, %w0, [%3]\n"
	52	+"1: ldxr %w0, %2\n"
	53	+" add %w0, %w0, %w3\n"
	54	+" stxr %w1, %w0, %2\n"
55	55	" cbnz %w1, 1b"
56		- : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
57		- : "r" (&v->counter), "Ir" (i)
	56	+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
	57	+ : "Ir" (i)
58	58	: "cc");
59	59	}
60	60
61	61
...	...	@@ -64,13 +64,13 @@
64	64	int result;
65	65
66	66	asm volatile("// atomic_add_return\n"
67		-"1: ldaxr %w0, [%3]\n"
68		-" add %w0, %w0, %w4\n"
69		-" stlxr %w1, %w0, [%3]\n"
	67	+"1: ldaxr %w0, %2\n"
	68	+" add %w0, %w0, %w3\n"
	69	+" stlxr %w1, %w0, %2\n"
70	70	" cbnz %w1, 1b"
71		- : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
72		- : "r" (&v->counter), "Ir" (i)
73		- : "cc");
	71	+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
	72	+ : "Ir" (i)
	73	+ : "cc", "memory");
74	74
75	75	return result;
76	76	}
77	77
...	...	@@ -81,12 +81,12 @@
81	81	int result;
82	82
83	83	asm volatile("// atomic_sub\n"
84		-"1: ldxr %w0, [%3]\n"
85		-" sub %w0, %w0, %w4\n"
86		-" stxr %w1, %w0, [%3]\n"
	84	+"1: ldxr %w0, %2\n"
	85	+" sub %w0, %w0, %w3\n"
	86	+" stxr %w1, %w0, %2\n"
87	87	" cbnz %w1, 1b"
88		- : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
89		- : "r" (&v->counter), "Ir" (i)
	88	+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
	89	+ : "Ir" (i)
90	90	: "cc");
91	91	}
92	92
93	93
...	...	@@ -96,13 +96,13 @@
96	96	int result;
97	97
98	98	asm volatile("// atomic_sub_return\n"
99		-"1: ldaxr %w0, [%3]\n"
100		-" sub %w0, %w0, %w4\n"
101		-" stlxr %w1, %w0, [%3]\n"
	99	+"1: ldaxr %w0, %2\n"
	100	+" sub %w0, %w0, %w3\n"
	101	+" stlxr %w1, %w0, %2\n"
102	102	" cbnz %w1, 1b"
103		- : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
104		- : "r" (&v->counter), "Ir" (i)
105		- : "cc");
	103	+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
	104	+ : "Ir" (i)
	105	+ : "cc", "memory");
106	106
107	107	return result;
108	108	}
109	109
110	110
...	...	@@ -113,15 +113,15 @@
113	113	int oldval;
114	114
115	115	asm volatile("// atomic_cmpxchg\n"
116		-"1: ldaxr %w1, [%3]\n"
117		-" cmp %w1, %w4\n"
	116	+"1: ldaxr %w1, %2\n"
	117	+" cmp %w1, %w3\n"
118	118	" b.ne 2f\n"
119		-" stlxr %w0, %w5, [%3]\n"
	119	+" stlxr %w0, %w4, %2\n"
120	120	" cbnz %w0, 1b\n"
121	121	"2:"
122		- : "=&r" (tmp), "=&r" (oldval), "+o" (ptr->counter)
123		- : "r" (&ptr->counter), "Ir" (old), "r" (new)
124		- : "cc");
	122	+ : "=&r" (tmp), "=&r" (oldval), "+Q" (ptr->counter)
	123	+ : "Ir" (old), "r" (new)
	124	+ : "cc", "memory");
125	125
126	126	return oldval;
127	127	}
128	128
...	...	@@ -131,12 +131,12 @@
131	131	unsigned long tmp, tmp2;
132	132
133	133	asm volatile("// atomic_clear_mask\n"
134		-"1: ldxr %0, [%3]\n"
135		-" bic %0, %0, %4\n"
136		-" stxr %w1, %0, [%3]\n"
	134	+"1: ldxr %0, %2\n"
	135	+" bic %0, %0, %3\n"
	136	+" stxr %w1, %0, %2\n"
137	137	" cbnz %w1, 1b"
138		- : "=&r" (tmp), "=&r" (tmp2), "+o" (*addr)
139		- : "r" (addr), "Ir" (mask)
	138	+ : "=&r" (tmp), "=&r" (tmp2), "+Q" (*addr)
	139	+ : "Ir" (mask)
140	140	: "cc");
141	141	}
142	142
143	143
...	...	@@ -182,12 +182,12 @@
182	182	unsigned long tmp;
183	183
184	184	asm volatile("// atomic64_add\n"
185		-"1: ldxr %0, [%3]\n"
186		-" add %0, %0, %4\n"
187		-" stxr %w1, %0, [%3]\n"
	185	+"1: ldxr %0, %2\n"
	186	+" add %0, %0, %3\n"
	187	+" stxr %w1, %0, %2\n"
188	188	" cbnz %w1, 1b"
189		- : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
190		- : "r" (&v->counter), "Ir" (i)
	189	+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
	190	+ : "Ir" (i)
191	191	: "cc");
192	192	}
193	193
194	194
...	...	@@ -197,13 +197,13 @@
197	197	unsigned long tmp;
198	198
199	199	asm volatile("// atomic64_add_return\n"
200		-"1: ldaxr %0, [%3]\n"
201		-" add %0, %0, %4\n"
202		-" stlxr %w1, %0, [%3]\n"
	200	+"1: ldaxr %0, %2\n"
	201	+" add %0, %0, %3\n"
	202	+" stlxr %w1, %0, %2\n"
203	203	" cbnz %w1, 1b"
204		- : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
205		- : "r" (&v->counter), "Ir" (i)
206		- : "cc");
	204	+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
	205	+ : "Ir" (i)
	206	+ : "cc", "memory");
207	207
208	208	return result;
209	209	}
210	210
...	...	@@ -214,12 +214,12 @@
214	214	unsigned long tmp;
215	215
216	216	asm volatile("// atomic64_sub\n"
217		-"1: ldxr %0, [%3]\n"
218		-" sub %0, %0, %4\n"
219		-" stxr %w1, %0, [%3]\n"
	217	+"1: ldxr %0, %2\n"
	218	+" sub %0, %0, %3\n"
	219	+" stxr %w1, %0, %2\n"
220	220	" cbnz %w1, 1b"
221		- : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
222		- : "r" (&v->counter), "Ir" (i)
	221	+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
	222	+ : "Ir" (i)
223	223	: "cc");
224	224	}
225	225
226	226
...	...	@@ -229,13 +229,13 @@
229	229	unsigned long tmp;
230	230
231	231	asm volatile("// atomic64_sub_return\n"
232		-"1: ldaxr %0, [%3]\n"
233		-" sub %0, %0, %4\n"
234		-" stlxr %w1, %0, [%3]\n"
	232	+"1: ldaxr %0, %2\n"
	233	+" sub %0, %0, %3\n"
	234	+" stlxr %w1, %0, %2\n"
235	235	" cbnz %w1, 1b"
236		- : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
237		- : "r" (&v->counter), "Ir" (i)
238		- : "cc");
	236	+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
	237	+ : "Ir" (i)
	238	+ : "cc", "memory");
239	239
240	240	return result;
241	241	}
242	242
243	243
...	...	@@ -246,15 +246,15 @@
246	246	unsigned long res;
247	247
248	248	asm volatile("// atomic64_cmpxchg\n"
249		-"1: ldaxr %1, [%3]\n"
250		-" cmp %1, %4\n"
	249	+"1: ldaxr %1, %2\n"
	250	+" cmp %1, %3\n"
251	251	" b.ne 2f\n"
252		-" stlxr %w0, %5, [%3]\n"
	252	+" stlxr %w0, %4, %2\n"
253	253	" cbnz %w0, 1b\n"
254	254	"2:"
255		- : "=&r" (res), "=&r" (oldval), "+o" (ptr->counter)
256		- : "r" (&ptr->counter), "Ir" (old), "r" (new)
257		- : "cc");
	255	+ : "=&r" (res), "=&r" (oldval), "+Q" (ptr->counter)
	256	+ : "Ir" (old), "r" (new)
	257	+ : "cc", "memory");
258	258
259	259	return oldval;
260	260	}
261	261
262	262
...	...	@@ -267,15 +267,15 @@
267	267	unsigned long tmp;
268	268
269	269	asm volatile("// atomic64_dec_if_positive\n"
270		-"1: ldaxr %0, [%3]\n"
	270	+"1: ldaxr %0, %2\n"
271	271	" subs %0, %0, #1\n"
272	272	" b.mi 2f\n"
273		-" stlxr %w1, %0, [%3]\n"
	273	+" stlxr %w1, %0, %2\n"
274	274	" cbnz %w1, 1b\n"
275	275	"2:"
276		- : "=&r" (result), "=&r" (tmp), "+o" (v->counter)
277		- : "r" (&v->counter)
278		- : "cc");
	276	+ : "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
	277	+ :
	278	+ : "cc", "memory");
279	279
280	280	return result;
281	281	}
...	...	@@ -29,39 +29,39 @@
29	29	switch (size) {
30	30	case 1:
31	31	asm volatile("// __xchg1\n"
32		- "1: ldaxrb %w0, [%3]\n"
33		- " stlxrb %w1, %w2, [%3]\n"
	32	+ "1: ldaxrb %w0, %2\n"
	33	+ " stlxrb %w1, %w3, %2\n"
34	34	" cbnz %w1, 1b\n"
35		- : "=&r" (ret), "=&r" (tmp)
36		- : "r" (x), "r" (ptr)
37		- : "memory", "cc");
	35	+ : "=&r" (ret), "=&r" (tmp), "+Q" ((u8 )ptr)
	36	+ : "r" (x)
	37	+ : "cc", "memory");
38	38	break;
39	39	case 2:
40	40	asm volatile("// __xchg2\n"
41		- "1: ldaxrh %w0, [%3]\n"
42		- " stlxrh %w1, %w2, [%3]\n"
	41	+ "1: ldaxrh %w0, %2\n"
	42	+ " stlxrh %w1, %w3, %2\n"
43	43	" cbnz %w1, 1b\n"
44		- : "=&r" (ret), "=&r" (tmp)
45		- : "r" (x), "r" (ptr)
46		- : "memory", "cc");
	44	+ : "=&r" (ret), "=&r" (tmp), "+Q" ((u16 )ptr)
	45	+ : "r" (x)
	46	+ : "cc", "memory");
47	47	break;
48	48	case 4:
49	49	asm volatile("// __xchg4\n"
50		- "1: ldaxr %w0, [%3]\n"
51		- " stlxr %w1, %w2, [%3]\n"
	50	+ "1: ldaxr %w0, %2\n"
	51	+ " stlxr %w1, %w3, %2\n"
52	52	" cbnz %w1, 1b\n"
53		- : "=&r" (ret), "=&r" (tmp)
54		- : "r" (x), "r" (ptr)
55		- : "memory", "cc");
	53	+ : "=&r" (ret), "=&r" (tmp), "+Q" ((u32 )ptr)
	54	+ : "r" (x)
	55	+ : "cc", "memory");
56	56	break;
57	57	case 8:
58	58	asm volatile("// __xchg8\n"
59		- "1: ldaxr %0, [%3]\n"
60		- " stlxr %w1, %2, [%3]\n"
	59	+ "1: ldaxr %0, %2\n"
	60	+ " stlxr %w1, %3, %2\n"
61	61	" cbnz %w1, 1b\n"
62		- : "=&r" (ret), "=&r" (tmp)
63		- : "r" (x), "r" (ptr)
64		- : "memory", "cc");
	62	+ : "=&r" (ret), "=&r" (tmp), "+Q" ((u64 )ptr)
	63	+ : "r" (x)
	64	+ : "cc", "memory");
65	65	break;
66	66	default:
67	67	BUILD_BUG();
68	68
69	69
...	...	@@ -82,14 +82,14 @@
82	82	case 1:
83	83	do {
84	84	asm volatile("// __cmpxchg1\n"
85		- " ldxrb %w1, [%2]\n"
	85	+ " ldxrb %w1, %2\n"
86	86	" mov %w0, #0\n"
87	87	" cmp %w1, %w3\n"
88	88	" b.ne 1f\n"
89		- " stxrb %w0, %w4, [%2]\n"
	89	+ " stxrb %w0, %w4, %2\n"
90	90	"1:\n"
91		- : "=&r" (res), "=&r" (oldval)
92		- : "r" (ptr), "Ir" (old), "r" (new)
	91	+ : "=&r" (res), "=&r" (oldval), "+Q" ((u8 )ptr)
	92	+ : "Ir" (old), "r" (new)
93	93	: "cc");
94	94	} while (res);
95	95	break;
96	96
97	97
98	98
99	99
100	100
...	...	@@ -97,29 +97,29 @@
97	97	case 2:
98	98	do {
99	99	asm volatile("// __cmpxchg2\n"
100		- " ldxrh %w1, [%2]\n"
	100	+ " ldxrh %w1, %2\n"
101	101	" mov %w0, #0\n"
102	102	" cmp %w1, %w3\n"
103	103	" b.ne 1f\n"
104		- " stxrh %w0, %w4, [%2]\n"
	104	+ " stxrh %w0, %w4, %2\n"
105	105	"1:\n"
106		- : "=&r" (res), "=&r" (oldval)
107		- : "r" (ptr), "Ir" (old), "r" (new)
108		- : "memory", "cc");
	106	+ : "=&r" (res), "=&r" (oldval), "+Q" ((u16 )ptr)
	107	+ : "Ir" (old), "r" (new)
	108	+ : "cc");
109	109	} while (res);
110	110	break;
111	111
112	112	case 4:
113	113	do {
114	114	asm volatile("// __cmpxchg4\n"
115		- " ldxr %w1, [%2]\n"
	115	+ " ldxr %w1, %2\n"
116	116	" mov %w0, #0\n"
117	117	" cmp %w1, %w3\n"
118	118	" b.ne 1f\n"
119		- " stxr %w0, %w4, [%2]\n"
	119	+ " stxr %w0, %w4, %2\n"
120	120	"1:\n"
121		- : "=&r" (res), "=&r" (oldval)
122		- : "r" (ptr), "Ir" (old), "r" (new)
	121	+ : "=&r" (res), "=&r" (oldval), "+Q" ((u32 )ptr)
	122	+ : "Ir" (old), "r" (new)
123	123	: "cc");
124	124	} while (res);
125	125	break;
126	126
127	127
...	...	@@ -127,14 +127,14 @@
127	127	case 8:
128	128	do {
129	129	asm volatile("// __cmpxchg8\n"
130		- " ldxr %1, [%2]\n"
	130	+ " ldxr %1, %2\n"
131	131	" mov %w0, #0\n"
132	132	" cmp %1, %3\n"
133	133	" b.ne 1f\n"
134		- " stxr %w0, %4, [%2]\n"
	134	+ " stxr %w0, %4, %2\n"
135	135	"1:\n"
136		- : "=&r" (res), "=&r" (oldval)
137		- : "r" (ptr), "Ir" (old), "r" (new)
	136	+ : "=&r" (res), "=&r" (oldval), "+Q" ((u64 )ptr)
	137	+ : "Ir" (old), "r" (new)
138	138	: "cc");
139	139	} while (res);
140	140	break;
...	...	@@ -39,7 +39,7 @@
39	39	" .popsection\n" \
40	40	: "=&r" (ret), "=&r" (oldval), "+Q" (*uaddr), "=&r" (tmp) \
41	41	: "r" (oparg), "Ir" (-EFAULT) \
42		- : "cc")
	42	+ : "cc", "memory")
43	43
44	44	static inline int
45	45	futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
...	...	@@ -230,6 +230,9 @@
230	230	#define ioremap_wc(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NC))
231	231	#define iounmap __iounmap
232	232
	233	+#define PROT_SECT_DEFAULT (PMD_TYPE_SECT \| PMD_SECT_AF)
	234	+#define PROT_SECT_DEVICE_nGnRE (PROT_SECT_DEFAULT \| PTE_PXN \| PTE_UXN \| PMD_ATTRINDX(MT_DEVICE_nGnRE))
	235	+
233	236	#define ARCH_HAS_IOREMAP_WC
234	237	#include <asm-generic/iomap.h>
235	238
...	...	@@ -43,6 +43,7 @@
43	43	#define PAGE_OFFSET UL(0xffffffc000000000)
44	44	#define MODULES_END (PAGE_OFFSET)
45	45	#define MODULES_VADDR (MODULES_END - SZ_64M)
	46	+#define EARLYCON_IOBASE (MODULES_VADDR - SZ_4M)
46	47	#define VA_BITS (39)
47	48	#define TASK_SIZE_64 (UL(1) << VA_BITS)
48	49
...	...	@@ -26,6 +26,7 @@
26	26
27	27	extern void paging_init(void);
28	28	extern void setup_mm_for_reboot(void);
	29	+extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
29	30
30	31	#endif