Commit 79b16641efabd14944dbfc2fde2ae1e8ae8413bc
Committed by
Mike Turquette
1 parent
fb72a0590b
Exists in
smarc-l5.0.0_1.0.0-ga
and in
5 other branches
clk: add device tree fixed-factor-clock binding support
Add support for DT "fixed-factor-clock" binding to the common fixed factor clock support. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Tested-by: Christian Ruppert <christian.ruppert@abilis.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
Showing 3 changed files with 62 additions and 0 deletions Inline Diff
Documentation/devicetree/bindings/clock/fixed-factor-clock.txt
File was created | 1 | Binding for simple fixed factor rate clock sources. | |
2 | |||
3 | This binding uses the common clock binding[1]. | ||
4 | |||
5 | [1] Documentation/devicetree/bindings/clock/clock-bindings.txt | ||
6 | |||
7 | Required properties: | ||
8 | - compatible : shall be "fixed-factor-clock". | ||
9 | - #clock-cells : from common clock binding; shall be set to 0. | ||
10 | - clock-div: fixed divider. | ||
11 | - clock-mult: fixed multiplier. | ||
12 | - clocks: parent clock. | ||
13 | |||
14 | Optional properties: | ||
15 | - clock-output-names : From common clock binding. | ||
16 | |||
17 | Example: | ||
18 | clock { | ||
19 | compatible = "fixed-factor-clock"; | ||
20 | clocks = <&parentclk>; | ||
21 | #clock-cells = <0>; | ||
22 | div = <2>; | ||
23 | mult = <1>; | ||
24 | }; | ||
25 |
drivers/clk/clk-fixed-factor.c
1 | /* | 1 | /* |
2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> | 2 | * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify | 4 | * This program is free software; you can redistribute it and/or modify |
5 | * it under the terms of the GNU General Public License version 2 as | 5 | * it under the terms of the GNU General Public License version 2 as |
6 | * published by the Free Software Foundation. | 6 | * published by the Free Software Foundation. |
7 | * | 7 | * |
8 | * Standard functionality for the common clock API. | 8 | * Standard functionality for the common clock API. |
9 | */ | 9 | */ |
10 | #include <linux/module.h> | 10 | #include <linux/module.h> |
11 | #include <linux/clk-provider.h> | 11 | #include <linux/clk-provider.h> |
12 | #include <linux/slab.h> | 12 | #include <linux/slab.h> |
13 | #include <linux/err.h> | 13 | #include <linux/err.h> |
14 | #include <linux/of.h> | ||
14 | 15 | ||
15 | /* | 16 | /* |
16 | * DOC: basic fixed multiplier and divider clock that cannot gate | 17 | * DOC: basic fixed multiplier and divider clock that cannot gate |
17 | * | 18 | * |
18 | * Traits of this clock: | 19 | * Traits of this clock: |
19 | * prepare - clk_prepare only ensures that parents are prepared | 20 | * prepare - clk_prepare only ensures that parents are prepared |
20 | * enable - clk_enable only ensures that parents are enabled | 21 | * enable - clk_enable only ensures that parents are enabled |
21 | * rate - rate is fixed. clk->rate = parent->rate / div * mult | 22 | * rate - rate is fixed. clk->rate = parent->rate / div * mult |
22 | * parent - fixed parent. No clk_set_parent support | 23 | * parent - fixed parent. No clk_set_parent support |
23 | */ | 24 | */ |
24 | 25 | ||
25 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) | 26 | #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) |
26 | 27 | ||
27 | static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, | 28 | static unsigned long clk_factor_recalc_rate(struct clk_hw *hw, |
28 | unsigned long parent_rate) | 29 | unsigned long parent_rate) |
29 | { | 30 | { |
30 | struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); | 31 | struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); |
31 | unsigned long long int rate; | 32 | unsigned long long int rate; |
32 | 33 | ||
33 | rate = (unsigned long long int)parent_rate * fix->mult; | 34 | rate = (unsigned long long int)parent_rate * fix->mult; |
34 | do_div(rate, fix->div); | 35 | do_div(rate, fix->div); |
35 | return (unsigned long)rate; | 36 | return (unsigned long)rate; |
36 | } | 37 | } |
37 | 38 | ||
38 | static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, | 39 | static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate, |
39 | unsigned long *prate) | 40 | unsigned long *prate) |
40 | { | 41 | { |
41 | struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); | 42 | struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); |
42 | 43 | ||
43 | if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { | 44 | if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) { |
44 | unsigned long best_parent; | 45 | unsigned long best_parent; |
45 | 46 | ||
46 | best_parent = (rate / fix->mult) * fix->div; | 47 | best_parent = (rate / fix->mult) * fix->div; |
47 | *prate = __clk_round_rate(__clk_get_parent(hw->clk), | 48 | *prate = __clk_round_rate(__clk_get_parent(hw->clk), |
48 | best_parent); | 49 | best_parent); |
49 | } | 50 | } |
50 | 51 | ||
51 | return (*prate / fix->div) * fix->mult; | 52 | return (*prate / fix->div) * fix->mult; |
52 | } | 53 | } |
53 | 54 | ||
54 | static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, | 55 | static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, |
55 | unsigned long parent_rate) | 56 | unsigned long parent_rate) |
56 | { | 57 | { |
57 | return 0; | 58 | return 0; |
58 | } | 59 | } |
59 | 60 | ||
60 | struct clk_ops clk_fixed_factor_ops = { | 61 | struct clk_ops clk_fixed_factor_ops = { |
61 | .round_rate = clk_factor_round_rate, | 62 | .round_rate = clk_factor_round_rate, |
62 | .set_rate = clk_factor_set_rate, | 63 | .set_rate = clk_factor_set_rate, |
63 | .recalc_rate = clk_factor_recalc_rate, | 64 | .recalc_rate = clk_factor_recalc_rate, |
64 | }; | 65 | }; |
65 | EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); | 66 | EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); |
66 | 67 | ||
67 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, | 68 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
68 | const char *parent_name, unsigned long flags, | 69 | const char *parent_name, unsigned long flags, |
69 | unsigned int mult, unsigned int div) | 70 | unsigned int mult, unsigned int div) |
70 | { | 71 | { |
71 | struct clk_fixed_factor *fix; | 72 | struct clk_fixed_factor *fix; |
72 | struct clk_init_data init; | 73 | struct clk_init_data init; |
73 | struct clk *clk; | 74 | struct clk *clk; |
74 | 75 | ||
75 | fix = kmalloc(sizeof(*fix), GFP_KERNEL); | 76 | fix = kmalloc(sizeof(*fix), GFP_KERNEL); |
76 | if (!fix) { | 77 | if (!fix) { |
77 | pr_err("%s: could not allocate fixed factor clk\n", __func__); | 78 | pr_err("%s: could not allocate fixed factor clk\n", __func__); |
78 | return ERR_PTR(-ENOMEM); | 79 | return ERR_PTR(-ENOMEM); |
79 | } | 80 | } |
80 | 81 | ||
81 | /* struct clk_fixed_factor assignments */ | 82 | /* struct clk_fixed_factor assignments */ |
82 | fix->mult = mult; | 83 | fix->mult = mult; |
83 | fix->div = div; | 84 | fix->div = div; |
84 | fix->hw.init = &init; | 85 | fix->hw.init = &init; |
85 | 86 | ||
86 | init.name = name; | 87 | init.name = name; |
87 | init.ops = &clk_fixed_factor_ops; | 88 | init.ops = &clk_fixed_factor_ops; |
88 | init.flags = flags | CLK_IS_BASIC; | 89 | init.flags = flags | CLK_IS_BASIC; |
89 | init.parent_names = &parent_name; | 90 | init.parent_names = &parent_name; |
90 | init.num_parents = 1; | 91 | init.num_parents = 1; |
91 | 92 | ||
92 | clk = clk_register(dev, &fix->hw); | 93 | clk = clk_register(dev, &fix->hw); |
93 | 94 | ||
94 | if (IS_ERR(clk)) | 95 | if (IS_ERR(clk)) |
95 | kfree(fix); | 96 | kfree(fix); |
96 | 97 | ||
97 | return clk; | 98 | return clk; |
98 | } | 99 | } |
100 | #ifdef CONFIG_OF | ||
101 | /** | ||
102 | * of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock | ||
103 | */ | ||
104 | void __init of_fixed_factor_clk_setup(struct device_node *node) | ||
105 | { | ||
106 | struct clk *clk; | ||
107 | const char *clk_name = node->name; | ||
108 | const char *parent_name; | ||
109 | u32 div, mult; | ||
110 | |||
111 | if (of_property_read_u32(node, "clock-div", &div)) { | ||
112 | pr_err("%s Fixed factor clock <%s> must have a clock-div property\n", | ||
113 | __func__, node->name); | ||
114 | return; | ||
115 | } | ||
116 | |||
117 | if (of_property_read_u32(node, "clock-mult", &mult)) { | ||
118 | pr_err("%s Fixed factor clock <%s> must have a clokc-mult property\n", | ||
119 | __func__, node->name); | ||
120 | return; | ||
121 | } | ||
122 | |||
123 | of_property_read_string(node, "clock-output-names", &clk_name); | ||
124 | parent_name = of_clk_get_parent_name(node, 0); | ||
125 | |||
126 | clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0, | ||
127 | mult, div); | ||
128 | if (!IS_ERR(clk)) | ||
129 | of_clk_add_provider(node, of_clk_src_simple_get, clk); | ||
130 | } | ||
131 | EXPORT_SYMBOL_GPL(of_fixed_factor_clk_setup); | ||
132 | CLK_OF_DECLARE(fixed_factor_clk, "fixed-factor-clock", | ||
133 | of_fixed_factor_clk_setup); | ||
134 | #endif | ||
99 | 135 |
include/linux/clk-provider.h
1 | /* | 1 | /* |
2 | * linux/include/linux/clk-provider.h | 2 | * linux/include/linux/clk-provider.h |
3 | * | 3 | * |
4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> | 4 | * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com> |
5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> | 5 | * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org> |
6 | * | 6 | * |
7 | * This program is free software; you can redistribute it and/or modify | 7 | * This program is free software; you can redistribute it and/or modify |
8 | * it under the terms of the GNU General Public License version 2 as | 8 | * it under the terms of the GNU General Public License version 2 as |
9 | * published by the Free Software Foundation. | 9 | * published by the Free Software Foundation. |
10 | */ | 10 | */ |
11 | #ifndef __LINUX_CLK_PROVIDER_H | 11 | #ifndef __LINUX_CLK_PROVIDER_H |
12 | #define __LINUX_CLK_PROVIDER_H | 12 | #define __LINUX_CLK_PROVIDER_H |
13 | 13 | ||
14 | #include <linux/clk.h> | 14 | #include <linux/clk.h> |
15 | 15 | ||
16 | #ifdef CONFIG_COMMON_CLK | 16 | #ifdef CONFIG_COMMON_CLK |
17 | 17 | ||
18 | /* | 18 | /* |
19 | * flags used across common struct clk. these flags should only affect the | 19 | * flags used across common struct clk. these flags should only affect the |
20 | * top-level framework. custom flags for dealing with hardware specifics | 20 | * top-level framework. custom flags for dealing with hardware specifics |
21 | * belong in struct clk_foo | 21 | * belong in struct clk_foo |
22 | */ | 22 | */ |
23 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ | 23 | #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */ |
24 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ | 24 | #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */ |
25 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ | 25 | #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */ |
26 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ | 26 | #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ |
27 | #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ | 27 | #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ |
28 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ | 28 | #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */ |
29 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ | 29 | #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */ |
30 | 30 | ||
31 | struct clk_hw; | 31 | struct clk_hw; |
32 | 32 | ||
33 | /** | 33 | /** |
34 | * struct clk_ops - Callback operations for hardware clocks; these are to | 34 | * struct clk_ops - Callback operations for hardware clocks; these are to |
35 | * be provided by the clock implementation, and will be called by drivers | 35 | * be provided by the clock implementation, and will be called by drivers |
36 | * through the clk_* api. | 36 | * through the clk_* api. |
37 | * | 37 | * |
38 | * @prepare: Prepare the clock for enabling. This must not return until | 38 | * @prepare: Prepare the clock for enabling. This must not return until |
39 | * the clock is fully prepared, and it's safe to call clk_enable. | 39 | * the clock is fully prepared, and it's safe to call clk_enable. |
40 | * This callback is intended to allow clock implementations to | 40 | * This callback is intended to allow clock implementations to |
41 | * do any initialisation that may sleep. Called with | 41 | * do any initialisation that may sleep. Called with |
42 | * prepare_lock held. | 42 | * prepare_lock held. |
43 | * | 43 | * |
44 | * @unprepare: Release the clock from its prepared state. This will typically | 44 | * @unprepare: Release the clock from its prepared state. This will typically |
45 | * undo any work done in the @prepare callback. Called with | 45 | * undo any work done in the @prepare callback. Called with |
46 | * prepare_lock held. | 46 | * prepare_lock held. |
47 | * | 47 | * |
48 | * @is_prepared: Queries the hardware to determine if the clock is prepared. | 48 | * @is_prepared: Queries the hardware to determine if the clock is prepared. |
49 | * This function is allowed to sleep. Optional, if this op is not | 49 | * This function is allowed to sleep. Optional, if this op is not |
50 | * set then the prepare count will be used. | 50 | * set then the prepare count will be used. |
51 | * | 51 | * |
52 | * @unprepare_unused: Unprepare the clock atomically. Only called from | 52 | * @unprepare_unused: Unprepare the clock atomically. Only called from |
53 | * clk_disable_unused for prepare clocks with special needs. | 53 | * clk_disable_unused for prepare clocks with special needs. |
54 | * Called with prepare mutex held. This function may sleep. | 54 | * Called with prepare mutex held. This function may sleep. |
55 | * | 55 | * |
56 | * @enable: Enable the clock atomically. This must not return until the | 56 | * @enable: Enable the clock atomically. This must not return until the |
57 | * clock is generating a valid clock signal, usable by consumer | 57 | * clock is generating a valid clock signal, usable by consumer |
58 | * devices. Called with enable_lock held. This function must not | 58 | * devices. Called with enable_lock held. This function must not |
59 | * sleep. | 59 | * sleep. |
60 | * | 60 | * |
61 | * @disable: Disable the clock atomically. Called with enable_lock held. | 61 | * @disable: Disable the clock atomically. Called with enable_lock held. |
62 | * This function must not sleep. | 62 | * This function must not sleep. |
63 | * | 63 | * |
64 | * @is_enabled: Queries the hardware to determine if the clock is enabled. | 64 | * @is_enabled: Queries the hardware to determine if the clock is enabled. |
65 | * This function must not sleep. Optional, if this op is not | 65 | * This function must not sleep. Optional, if this op is not |
66 | * set then the enable count will be used. | 66 | * set then the enable count will be used. |
67 | * | 67 | * |
68 | * @disable_unused: Disable the clock atomically. Only called from | 68 | * @disable_unused: Disable the clock atomically. Only called from |
69 | * clk_disable_unused for gate clocks with special needs. | 69 | * clk_disable_unused for gate clocks with special needs. |
70 | * Called with enable_lock held. This function must not | 70 | * Called with enable_lock held. This function must not |
71 | * sleep. | 71 | * sleep. |
72 | * | 72 | * |
73 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The | 73 | * @recalc_rate Recalculate the rate of this clock, by querying hardware. The |
74 | * parent rate is an input parameter. It is up to the caller to | 74 | * parent rate is an input parameter. It is up to the caller to |
75 | * ensure that the prepare_mutex is held across this call. | 75 | * ensure that the prepare_mutex is held across this call. |
76 | * Returns the calculated rate. Optional, but recommended - if | 76 | * Returns the calculated rate. Optional, but recommended - if |
77 | * this op is not set then clock rate will be initialized to 0. | 77 | * this op is not set then clock rate will be initialized to 0. |
78 | * | 78 | * |
79 | * @round_rate: Given a target rate as input, returns the closest rate actually | 79 | * @round_rate: Given a target rate as input, returns the closest rate actually |
80 | * supported by the clock. | 80 | * supported by the clock. |
81 | * | 81 | * |
82 | * @get_parent: Queries the hardware to determine the parent of a clock. The | 82 | * @get_parent: Queries the hardware to determine the parent of a clock. The |
83 | * return value is a u8 which specifies the index corresponding to | 83 | * return value is a u8 which specifies the index corresponding to |
84 | * the parent clock. This index can be applied to either the | 84 | * the parent clock. This index can be applied to either the |
85 | * .parent_names or .parents arrays. In short, this function | 85 | * .parent_names or .parents arrays. In short, this function |
86 | * translates the parent value read from hardware into an array | 86 | * translates the parent value read from hardware into an array |
87 | * index. Currently only called when the clock is initialized by | 87 | * index. Currently only called when the clock is initialized by |
88 | * __clk_init. This callback is mandatory for clocks with | 88 | * __clk_init. This callback is mandatory for clocks with |
89 | * multiple parents. It is optional (and unnecessary) for clocks | 89 | * multiple parents. It is optional (and unnecessary) for clocks |
90 | * with 0 or 1 parents. | 90 | * with 0 or 1 parents. |
91 | * | 91 | * |
92 | * @set_parent: Change the input source of this clock; for clocks with multiple | 92 | * @set_parent: Change the input source of this clock; for clocks with multiple |
93 | * possible parents specify a new parent by passing in the index | 93 | * possible parents specify a new parent by passing in the index |
94 | * as a u8 corresponding to the parent in either the .parent_names | 94 | * as a u8 corresponding to the parent in either the .parent_names |
95 | * or .parents arrays. This function in affect translates an | 95 | * or .parents arrays. This function in affect translates an |
96 | * array index into the value programmed into the hardware. | 96 | * array index into the value programmed into the hardware. |
97 | * Returns 0 on success, -EERROR otherwise. | 97 | * Returns 0 on success, -EERROR otherwise. |
98 | * | 98 | * |
99 | * @set_rate: Change the rate of this clock. The requested rate is specified | 99 | * @set_rate: Change the rate of this clock. The requested rate is specified |
100 | * by the second argument, which should typically be the return | 100 | * by the second argument, which should typically be the return |
101 | * of .round_rate call. The third argument gives the parent rate | 101 | * of .round_rate call. The third argument gives the parent rate |
102 | * which is likely helpful for most .set_rate implementation. | 102 | * which is likely helpful for most .set_rate implementation. |
103 | * Returns 0 on success, -EERROR otherwise. | 103 | * Returns 0 on success, -EERROR otherwise. |
104 | * | 104 | * |
105 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow | 105 | * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow |
106 | * implementations to split any work between atomic (enable) and sleepable | 106 | * implementations to split any work between atomic (enable) and sleepable |
107 | * (prepare) contexts. If enabling a clock requires code that might sleep, | 107 | * (prepare) contexts. If enabling a clock requires code that might sleep, |
108 | * this must be done in clk_prepare. Clock enable code that will never be | 108 | * this must be done in clk_prepare. Clock enable code that will never be |
109 | * called in a sleepable context may be implemented in clk_enable. | 109 | * called in a sleepable context may be implemented in clk_enable. |
110 | * | 110 | * |
111 | * Typically, drivers will call clk_prepare when a clock may be needed later | 111 | * Typically, drivers will call clk_prepare when a clock may be needed later |
112 | * (eg. when a device is opened), and clk_enable when the clock is actually | 112 | * (eg. when a device is opened), and clk_enable when the clock is actually |
113 | * required (eg. from an interrupt). Note that clk_prepare MUST have been | 113 | * required (eg. from an interrupt). Note that clk_prepare MUST have been |
114 | * called before clk_enable. | 114 | * called before clk_enable. |
115 | */ | 115 | */ |
116 | struct clk_ops { | 116 | struct clk_ops { |
117 | int (*prepare)(struct clk_hw *hw); | 117 | int (*prepare)(struct clk_hw *hw); |
118 | void (*unprepare)(struct clk_hw *hw); | 118 | void (*unprepare)(struct clk_hw *hw); |
119 | int (*is_prepared)(struct clk_hw *hw); | 119 | int (*is_prepared)(struct clk_hw *hw); |
120 | void (*unprepare_unused)(struct clk_hw *hw); | 120 | void (*unprepare_unused)(struct clk_hw *hw); |
121 | int (*enable)(struct clk_hw *hw); | 121 | int (*enable)(struct clk_hw *hw); |
122 | void (*disable)(struct clk_hw *hw); | 122 | void (*disable)(struct clk_hw *hw); |
123 | int (*is_enabled)(struct clk_hw *hw); | 123 | int (*is_enabled)(struct clk_hw *hw); |
124 | void (*disable_unused)(struct clk_hw *hw); | 124 | void (*disable_unused)(struct clk_hw *hw); |
125 | unsigned long (*recalc_rate)(struct clk_hw *hw, | 125 | unsigned long (*recalc_rate)(struct clk_hw *hw, |
126 | unsigned long parent_rate); | 126 | unsigned long parent_rate); |
127 | long (*round_rate)(struct clk_hw *hw, unsigned long, | 127 | long (*round_rate)(struct clk_hw *hw, unsigned long, |
128 | unsigned long *); | 128 | unsigned long *); |
129 | int (*set_parent)(struct clk_hw *hw, u8 index); | 129 | int (*set_parent)(struct clk_hw *hw, u8 index); |
130 | u8 (*get_parent)(struct clk_hw *hw); | 130 | u8 (*get_parent)(struct clk_hw *hw); |
131 | int (*set_rate)(struct clk_hw *hw, unsigned long, | 131 | int (*set_rate)(struct clk_hw *hw, unsigned long, |
132 | unsigned long); | 132 | unsigned long); |
133 | void (*init)(struct clk_hw *hw); | 133 | void (*init)(struct clk_hw *hw); |
134 | }; | 134 | }; |
135 | 135 | ||
136 | /** | 136 | /** |
137 | * struct clk_init_data - holds init data that's common to all clocks and is | 137 | * struct clk_init_data - holds init data that's common to all clocks and is |
138 | * shared between the clock provider and the common clock framework. | 138 | * shared between the clock provider and the common clock framework. |
139 | * | 139 | * |
140 | * @name: clock name | 140 | * @name: clock name |
141 | * @ops: operations this clock supports | 141 | * @ops: operations this clock supports |
142 | * @parent_names: array of string names for all possible parents | 142 | * @parent_names: array of string names for all possible parents |
143 | * @num_parents: number of possible parents | 143 | * @num_parents: number of possible parents |
144 | * @flags: framework-level hints and quirks | 144 | * @flags: framework-level hints and quirks |
145 | */ | 145 | */ |
146 | struct clk_init_data { | 146 | struct clk_init_data { |
147 | const char *name; | 147 | const char *name; |
148 | const struct clk_ops *ops; | 148 | const struct clk_ops *ops; |
149 | const char **parent_names; | 149 | const char **parent_names; |
150 | u8 num_parents; | 150 | u8 num_parents; |
151 | unsigned long flags; | 151 | unsigned long flags; |
152 | }; | 152 | }; |
153 | 153 | ||
154 | /** | 154 | /** |
155 | * struct clk_hw - handle for traversing from a struct clk to its corresponding | 155 | * struct clk_hw - handle for traversing from a struct clk to its corresponding |
156 | * hardware-specific structure. struct clk_hw should be declared within struct | 156 | * hardware-specific structure. struct clk_hw should be declared within struct |
157 | * clk_foo and then referenced by the struct clk instance that uses struct | 157 | * clk_foo and then referenced by the struct clk instance that uses struct |
158 | * clk_foo's clk_ops | 158 | * clk_foo's clk_ops |
159 | * | 159 | * |
160 | * @clk: pointer to the struct clk instance that points back to this struct | 160 | * @clk: pointer to the struct clk instance that points back to this struct |
161 | * clk_hw instance | 161 | * clk_hw instance |
162 | * | 162 | * |
163 | * @init: pointer to struct clk_init_data that contains the init data shared | 163 | * @init: pointer to struct clk_init_data that contains the init data shared |
164 | * with the common clock framework. | 164 | * with the common clock framework. |
165 | */ | 165 | */ |
166 | struct clk_hw { | 166 | struct clk_hw { |
167 | struct clk *clk; | 167 | struct clk *clk; |
168 | const struct clk_init_data *init; | 168 | const struct clk_init_data *init; |
169 | }; | 169 | }; |
170 | 170 | ||
171 | /* | 171 | /* |
172 | * DOC: Basic clock implementations common to many platforms | 172 | * DOC: Basic clock implementations common to many platforms |
173 | * | 173 | * |
174 | * Each basic clock hardware type is comprised of a structure describing the | 174 | * Each basic clock hardware type is comprised of a structure describing the |
175 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, | 175 | * clock hardware, implementations of the relevant callbacks in struct clk_ops, |
176 | * unique flags for that hardware type, a registration function and an | 176 | * unique flags for that hardware type, a registration function and an |
177 | * alternative macro for static initialization | 177 | * alternative macro for static initialization |
178 | */ | 178 | */ |
179 | 179 | ||
180 | /** | 180 | /** |
181 | * struct clk_fixed_rate - fixed-rate clock | 181 | * struct clk_fixed_rate - fixed-rate clock |
182 | * @hw: handle between common and hardware-specific interfaces | 182 | * @hw: handle between common and hardware-specific interfaces |
183 | * @fixed_rate: constant frequency of clock | 183 | * @fixed_rate: constant frequency of clock |
184 | */ | 184 | */ |
185 | struct clk_fixed_rate { | 185 | struct clk_fixed_rate { |
186 | struct clk_hw hw; | 186 | struct clk_hw hw; |
187 | unsigned long fixed_rate; | 187 | unsigned long fixed_rate; |
188 | u8 flags; | 188 | u8 flags; |
189 | }; | 189 | }; |
190 | 190 | ||
191 | extern const struct clk_ops clk_fixed_rate_ops; | 191 | extern const struct clk_ops clk_fixed_rate_ops; |
192 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, | 192 | struct clk *clk_register_fixed_rate(struct device *dev, const char *name, |
193 | const char *parent_name, unsigned long flags, | 193 | const char *parent_name, unsigned long flags, |
194 | unsigned long fixed_rate); | 194 | unsigned long fixed_rate); |
195 | 195 | ||
196 | void of_fixed_clk_setup(struct device_node *np); | 196 | void of_fixed_clk_setup(struct device_node *np); |
197 | 197 | ||
198 | /** | 198 | /** |
199 | * struct clk_gate - gating clock | 199 | * struct clk_gate - gating clock |
200 | * | 200 | * |
201 | * @hw: handle between common and hardware-specific interfaces | 201 | * @hw: handle between common and hardware-specific interfaces |
202 | * @reg: register controlling gate | 202 | * @reg: register controlling gate |
203 | * @bit_idx: single bit controlling gate | 203 | * @bit_idx: single bit controlling gate |
204 | * @flags: hardware-specific flags | 204 | * @flags: hardware-specific flags |
205 | * @lock: register lock | 205 | * @lock: register lock |
206 | * | 206 | * |
207 | * Clock which can gate its output. Implements .enable & .disable | 207 | * Clock which can gate its output. Implements .enable & .disable |
208 | * | 208 | * |
209 | * Flags: | 209 | * Flags: |
210 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to | 210 | * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to |
211 | * enable the clock. Setting this flag does the opposite: setting the bit | 211 | * enable the clock. Setting this flag does the opposite: setting the bit |
212 | * disable the clock and clearing it enables the clock | 212 | * disable the clock and clearing it enables the clock |
213 | */ | 213 | */ |
214 | struct clk_gate { | 214 | struct clk_gate { |
215 | struct clk_hw hw; | 215 | struct clk_hw hw; |
216 | void __iomem *reg; | 216 | void __iomem *reg; |
217 | u8 bit_idx; | 217 | u8 bit_idx; |
218 | u8 flags; | 218 | u8 flags; |
219 | spinlock_t *lock; | 219 | spinlock_t *lock; |
220 | }; | 220 | }; |
221 | 221 | ||
222 | #define CLK_GATE_SET_TO_DISABLE BIT(0) | 222 | #define CLK_GATE_SET_TO_DISABLE BIT(0) |
223 | 223 | ||
224 | extern const struct clk_ops clk_gate_ops; | 224 | extern const struct clk_ops clk_gate_ops; |
225 | struct clk *clk_register_gate(struct device *dev, const char *name, | 225 | struct clk *clk_register_gate(struct device *dev, const char *name, |
226 | const char *parent_name, unsigned long flags, | 226 | const char *parent_name, unsigned long flags, |
227 | void __iomem *reg, u8 bit_idx, | 227 | void __iomem *reg, u8 bit_idx, |
228 | u8 clk_gate_flags, spinlock_t *lock); | 228 | u8 clk_gate_flags, spinlock_t *lock); |
229 | 229 | ||
230 | struct clk_div_table { | 230 | struct clk_div_table { |
231 | unsigned int val; | 231 | unsigned int val; |
232 | unsigned int div; | 232 | unsigned int div; |
233 | }; | 233 | }; |
234 | 234 | ||
235 | /** | 235 | /** |
236 | * struct clk_divider - adjustable divider clock | 236 | * struct clk_divider - adjustable divider clock |
237 | * | 237 | * |
238 | * @hw: handle between common and hardware-specific interfaces | 238 | * @hw: handle between common and hardware-specific interfaces |
239 | * @reg: register containing the divider | 239 | * @reg: register containing the divider |
240 | * @shift: shift to the divider bit field | 240 | * @shift: shift to the divider bit field |
241 | * @width: width of the divider bit field | 241 | * @width: width of the divider bit field |
242 | * @table: array of value/divider pairs, last entry should have div = 0 | 242 | * @table: array of value/divider pairs, last entry should have div = 0 |
243 | * @lock: register lock | 243 | * @lock: register lock |
244 | * | 244 | * |
245 | * Clock with an adjustable divider affecting its output frequency. Implements | 245 | * Clock with an adjustable divider affecting its output frequency. Implements |
246 | * .recalc_rate, .set_rate and .round_rate | 246 | * .recalc_rate, .set_rate and .round_rate |
247 | * | 247 | * |
248 | * Flags: | 248 | * Flags: |
249 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the | 249 | * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the |
250 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is | 250 | * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is |
251 | * the raw value read from the register, with the value of zero considered | 251 | * the raw value read from the register, with the value of zero considered |
252 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. | 252 | * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set. |
253 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from | 253 | * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from |
254 | * the hardware register | 254 | * the hardware register |
255 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have | 255 | * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have |
256 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. | 256 | * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor. |
257 | * Some hardware implementations gracefully handle this case and allow a | 257 | * Some hardware implementations gracefully handle this case and allow a |
258 | * zero divisor by not modifying their input clock | 258 | * zero divisor by not modifying their input clock |
259 | * (divide by one / bypass). | 259 | * (divide by one / bypass). |
260 | */ | 260 | */ |
261 | struct clk_divider { | 261 | struct clk_divider { |
262 | struct clk_hw hw; | 262 | struct clk_hw hw; |
263 | void __iomem *reg; | 263 | void __iomem *reg; |
264 | u8 shift; | 264 | u8 shift; |
265 | u8 width; | 265 | u8 width; |
266 | u8 flags; | 266 | u8 flags; |
267 | const struct clk_div_table *table; | 267 | const struct clk_div_table *table; |
268 | spinlock_t *lock; | 268 | spinlock_t *lock; |
269 | }; | 269 | }; |
270 | 270 | ||
271 | #define CLK_DIVIDER_ONE_BASED BIT(0) | 271 | #define CLK_DIVIDER_ONE_BASED BIT(0) |
272 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) | 272 | #define CLK_DIVIDER_POWER_OF_TWO BIT(1) |
273 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) | 273 | #define CLK_DIVIDER_ALLOW_ZERO BIT(2) |
274 | 274 | ||
275 | extern const struct clk_ops clk_divider_ops; | 275 | extern const struct clk_ops clk_divider_ops; |
276 | struct clk *clk_register_divider(struct device *dev, const char *name, | 276 | struct clk *clk_register_divider(struct device *dev, const char *name, |
277 | const char *parent_name, unsigned long flags, | 277 | const char *parent_name, unsigned long flags, |
278 | void __iomem *reg, u8 shift, u8 width, | 278 | void __iomem *reg, u8 shift, u8 width, |
279 | u8 clk_divider_flags, spinlock_t *lock); | 279 | u8 clk_divider_flags, spinlock_t *lock); |
280 | struct clk *clk_register_divider_table(struct device *dev, const char *name, | 280 | struct clk *clk_register_divider_table(struct device *dev, const char *name, |
281 | const char *parent_name, unsigned long flags, | 281 | const char *parent_name, unsigned long flags, |
282 | void __iomem *reg, u8 shift, u8 width, | 282 | void __iomem *reg, u8 shift, u8 width, |
283 | u8 clk_divider_flags, const struct clk_div_table *table, | 283 | u8 clk_divider_flags, const struct clk_div_table *table, |
284 | spinlock_t *lock); | 284 | spinlock_t *lock); |
285 | 285 | ||
286 | /** | 286 | /** |
287 | * struct clk_mux - multiplexer clock | 287 | * struct clk_mux - multiplexer clock |
288 | * | 288 | * |
289 | * @hw: handle between common and hardware-specific interfaces | 289 | * @hw: handle between common and hardware-specific interfaces |
290 | * @reg: register controlling multiplexer | 290 | * @reg: register controlling multiplexer |
291 | * @shift: shift to multiplexer bit field | 291 | * @shift: shift to multiplexer bit field |
292 | * @width: width of mutliplexer bit field | 292 | * @width: width of mutliplexer bit field |
293 | * @flags: hardware-specific flags | 293 | * @flags: hardware-specific flags |
294 | * @lock: register lock | 294 | * @lock: register lock |
295 | * | 295 | * |
296 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent | 296 | * Clock with multiple selectable parents. Implements .get_parent, .set_parent |
297 | * and .recalc_rate | 297 | * and .recalc_rate |
298 | * | 298 | * |
299 | * Flags: | 299 | * Flags: |
300 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 | 300 | * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 |
301 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) | 301 | * CLK_MUX_INDEX_BIT - register index is a single bit (power of two) |
302 | */ | 302 | */ |
303 | struct clk_mux { | 303 | struct clk_mux { |
304 | struct clk_hw hw; | 304 | struct clk_hw hw; |
305 | void __iomem *reg; | 305 | void __iomem *reg; |
306 | u32 *table; | 306 | u32 *table; |
307 | u32 mask; | 307 | u32 mask; |
308 | u8 shift; | 308 | u8 shift; |
309 | u8 flags; | 309 | u8 flags; |
310 | spinlock_t *lock; | 310 | spinlock_t *lock; |
311 | }; | 311 | }; |
312 | 312 | ||
313 | #define CLK_MUX_INDEX_ONE BIT(0) | 313 | #define CLK_MUX_INDEX_ONE BIT(0) |
314 | #define CLK_MUX_INDEX_BIT BIT(1) | 314 | #define CLK_MUX_INDEX_BIT BIT(1) |
315 | 315 | ||
316 | extern const struct clk_ops clk_mux_ops; | 316 | extern const struct clk_ops clk_mux_ops; |
317 | 317 | ||
318 | struct clk *clk_register_mux(struct device *dev, const char *name, | 318 | struct clk *clk_register_mux(struct device *dev, const char *name, |
319 | const char **parent_names, u8 num_parents, unsigned long flags, | 319 | const char **parent_names, u8 num_parents, unsigned long flags, |
320 | void __iomem *reg, u8 shift, u8 width, | 320 | void __iomem *reg, u8 shift, u8 width, |
321 | u8 clk_mux_flags, spinlock_t *lock); | 321 | u8 clk_mux_flags, spinlock_t *lock); |
322 | 322 | ||
323 | struct clk *clk_register_mux_table(struct device *dev, const char *name, | 323 | struct clk *clk_register_mux_table(struct device *dev, const char *name, |
324 | const char **parent_names, u8 num_parents, unsigned long flags, | 324 | const char **parent_names, u8 num_parents, unsigned long flags, |
325 | void __iomem *reg, u8 shift, u32 mask, | 325 | void __iomem *reg, u8 shift, u32 mask, |
326 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); | 326 | u8 clk_mux_flags, u32 *table, spinlock_t *lock); |
327 | 327 | ||
328 | void of_fixed_factor_clk_setup(struct device_node *node); | ||
329 | |||
328 | /** | 330 | /** |
329 | * struct clk_fixed_factor - fixed multiplier and divider clock | 331 | * struct clk_fixed_factor - fixed multiplier and divider clock |
330 | * | 332 | * |
331 | * @hw: handle between common and hardware-specific interfaces | 333 | * @hw: handle between common and hardware-specific interfaces |
332 | * @mult: multiplier | 334 | * @mult: multiplier |
333 | * @div: divider | 335 | * @div: divider |
334 | * | 336 | * |
335 | * Clock with a fixed multiplier and divider. The output frequency is the | 337 | * Clock with a fixed multiplier and divider. The output frequency is the |
336 | * parent clock rate divided by div and multiplied by mult. | 338 | * parent clock rate divided by div and multiplied by mult. |
337 | * Implements .recalc_rate, .set_rate and .round_rate | 339 | * Implements .recalc_rate, .set_rate and .round_rate |
338 | */ | 340 | */ |
339 | 341 | ||
340 | struct clk_fixed_factor { | 342 | struct clk_fixed_factor { |
341 | struct clk_hw hw; | 343 | struct clk_hw hw; |
342 | unsigned int mult; | 344 | unsigned int mult; |
343 | unsigned int div; | 345 | unsigned int div; |
344 | }; | 346 | }; |
345 | 347 | ||
346 | extern struct clk_ops clk_fixed_factor_ops; | 348 | extern struct clk_ops clk_fixed_factor_ops; |
347 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, | 349 | struct clk *clk_register_fixed_factor(struct device *dev, const char *name, |
348 | const char *parent_name, unsigned long flags, | 350 | const char *parent_name, unsigned long flags, |
349 | unsigned int mult, unsigned int div); | 351 | unsigned int mult, unsigned int div); |
350 | 352 | ||
351 | /*** | 353 | /*** |
352 | * struct clk_composite - aggregate clock of mux, divider and gate clocks | 354 | * struct clk_composite - aggregate clock of mux, divider and gate clocks |
353 | * | 355 | * |
354 | * @hw: handle between common and hardware-specific interfaces | 356 | * @hw: handle between common and hardware-specific interfaces |
355 | * @mux_hw: handle between composite and hardware-specifix mux clock | 357 | * @mux_hw: handle between composite and hardware-specifix mux clock |
356 | * @div_hw: handle between composite and hardware-specifix divider clock | 358 | * @div_hw: handle between composite and hardware-specifix divider clock |
357 | * @gate_hw: handle between composite and hardware-specifix gate clock | 359 | * @gate_hw: handle between composite and hardware-specifix gate clock |
358 | * @mux_ops: clock ops for mux | 360 | * @mux_ops: clock ops for mux |
359 | * @div_ops: clock ops for divider | 361 | * @div_ops: clock ops for divider |
360 | * @gate_ops: clock ops for gate | 362 | * @gate_ops: clock ops for gate |
361 | */ | 363 | */ |
362 | struct clk_composite { | 364 | struct clk_composite { |
363 | struct clk_hw hw; | 365 | struct clk_hw hw; |
364 | struct clk_ops ops; | 366 | struct clk_ops ops; |
365 | 367 | ||
366 | struct clk_hw *mux_hw; | 368 | struct clk_hw *mux_hw; |
367 | struct clk_hw *div_hw; | 369 | struct clk_hw *div_hw; |
368 | struct clk_hw *gate_hw; | 370 | struct clk_hw *gate_hw; |
369 | 371 | ||
370 | const struct clk_ops *mux_ops; | 372 | const struct clk_ops *mux_ops; |
371 | const struct clk_ops *div_ops; | 373 | const struct clk_ops *div_ops; |
372 | const struct clk_ops *gate_ops; | 374 | const struct clk_ops *gate_ops; |
373 | }; | 375 | }; |
374 | 376 | ||
375 | struct clk *clk_register_composite(struct device *dev, const char *name, | 377 | struct clk *clk_register_composite(struct device *dev, const char *name, |
376 | const char **parent_names, int num_parents, | 378 | const char **parent_names, int num_parents, |
377 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, | 379 | struct clk_hw *mux_hw, const struct clk_ops *mux_ops, |
378 | struct clk_hw *div_hw, const struct clk_ops *div_ops, | 380 | struct clk_hw *div_hw, const struct clk_ops *div_ops, |
379 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, | 381 | struct clk_hw *gate_hw, const struct clk_ops *gate_ops, |
380 | unsigned long flags); | 382 | unsigned long flags); |
381 | 383 | ||
382 | /** | 384 | /** |
383 | * clk_register - allocate a new clock, register it and return an opaque cookie | 385 | * clk_register - allocate a new clock, register it and return an opaque cookie |
384 | * @dev: device that is registering this clock | 386 | * @dev: device that is registering this clock |
385 | * @hw: link to hardware-specific clock data | 387 | * @hw: link to hardware-specific clock data |
386 | * | 388 | * |
387 | * clk_register is the primary interface for populating the clock tree with new | 389 | * clk_register is the primary interface for populating the clock tree with new |
388 | * clock nodes. It returns a pointer to the newly allocated struct clk which | 390 | * clock nodes. It returns a pointer to the newly allocated struct clk which |
389 | * cannot be dereferenced by driver code but may be used in conjuction with the | 391 | * cannot be dereferenced by driver code but may be used in conjuction with the |
390 | * rest of the clock API. In the event of an error clk_register will return an | 392 | * rest of the clock API. In the event of an error clk_register will return an |
391 | * error code; drivers must test for an error code after calling clk_register. | 393 | * error code; drivers must test for an error code after calling clk_register. |
392 | */ | 394 | */ |
393 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); | 395 | struct clk *clk_register(struct device *dev, struct clk_hw *hw); |
394 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); | 396 | struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw); |
395 | 397 | ||
396 | void clk_unregister(struct clk *clk); | 398 | void clk_unregister(struct clk *clk); |
397 | void devm_clk_unregister(struct device *dev, struct clk *clk); | 399 | void devm_clk_unregister(struct device *dev, struct clk *clk); |
398 | 400 | ||
399 | /* helper functions */ | 401 | /* helper functions */ |
400 | const char *__clk_get_name(struct clk *clk); | 402 | const char *__clk_get_name(struct clk *clk); |
401 | struct clk_hw *__clk_get_hw(struct clk *clk); | 403 | struct clk_hw *__clk_get_hw(struct clk *clk); |
402 | u8 __clk_get_num_parents(struct clk *clk); | 404 | u8 __clk_get_num_parents(struct clk *clk); |
403 | struct clk *__clk_get_parent(struct clk *clk); | 405 | struct clk *__clk_get_parent(struct clk *clk); |
404 | unsigned int __clk_get_enable_count(struct clk *clk); | 406 | unsigned int __clk_get_enable_count(struct clk *clk); |
405 | unsigned int __clk_get_prepare_count(struct clk *clk); | 407 | unsigned int __clk_get_prepare_count(struct clk *clk); |
406 | unsigned long __clk_get_rate(struct clk *clk); | 408 | unsigned long __clk_get_rate(struct clk *clk); |
407 | unsigned long __clk_get_flags(struct clk *clk); | 409 | unsigned long __clk_get_flags(struct clk *clk); |
408 | bool __clk_is_prepared(struct clk *clk); | 410 | bool __clk_is_prepared(struct clk *clk); |
409 | bool __clk_is_enabled(struct clk *clk); | 411 | bool __clk_is_enabled(struct clk *clk); |
410 | struct clk *__clk_lookup(const char *name); | 412 | struct clk *__clk_lookup(const char *name); |
411 | 413 | ||
412 | /* | 414 | /* |
413 | * FIXME clock api without lock protection | 415 | * FIXME clock api without lock protection |
414 | */ | 416 | */ |
415 | int __clk_prepare(struct clk *clk); | 417 | int __clk_prepare(struct clk *clk); |
416 | void __clk_unprepare(struct clk *clk); | 418 | void __clk_unprepare(struct clk *clk); |
417 | void __clk_reparent(struct clk *clk, struct clk *new_parent); | 419 | void __clk_reparent(struct clk *clk, struct clk *new_parent); |
418 | unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); | 420 | unsigned long __clk_round_rate(struct clk *clk, unsigned long rate); |
419 | 421 | ||
420 | struct of_device_id; | 422 | struct of_device_id; |
421 | 423 | ||
422 | typedef void (*of_clk_init_cb_t)(struct device_node *); | 424 | typedef void (*of_clk_init_cb_t)(struct device_node *); |
423 | 425 | ||
424 | int of_clk_add_provider(struct device_node *np, | 426 | int of_clk_add_provider(struct device_node *np, |
425 | struct clk *(*clk_src_get)(struct of_phandle_args *args, | 427 | struct clk *(*clk_src_get)(struct of_phandle_args *args, |
426 | void *data), | 428 | void *data), |
427 | void *data); | 429 | void *data); |
428 | void of_clk_del_provider(struct device_node *np); | 430 | void of_clk_del_provider(struct device_node *np); |
429 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, | 431 | struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec, |
430 | void *data); | 432 | void *data); |
431 | struct clk_onecell_data { | 433 | struct clk_onecell_data { |
432 | struct clk **clks; | 434 | struct clk **clks; |
433 | unsigned int clk_num; | 435 | unsigned int clk_num; |
434 | }; | 436 | }; |
435 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); | 437 | struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data); |
436 | const char *of_clk_get_parent_name(struct device_node *np, int index); | 438 | const char *of_clk_get_parent_name(struct device_node *np, int index); |
437 | 439 | ||
438 | void of_clk_init(const struct of_device_id *matches); | 440 | void of_clk_init(const struct of_device_id *matches); |
439 | 441 | ||
440 | #define CLK_OF_DECLARE(name, compat, fn) \ | 442 | #define CLK_OF_DECLARE(name, compat, fn) \ |
441 | static const struct of_device_id __clk_of_table_##name \ | 443 | static const struct of_device_id __clk_of_table_##name \ |
442 | __used __section(__clk_of_table) \ | 444 | __used __section(__clk_of_table) \ |
443 | = { .compatible = compat, .data = fn }; | 445 | = { .compatible = compat, .data = fn }; |
444 | 446 | ||
445 | #endif /* CONFIG_COMMON_CLK */ | 447 | #endif /* CONFIG_COMMON_CLK */ |
446 | #endif /* CLK_PROVIDER_H */ | 448 | #endif /* CLK_PROVIDER_H */ |
447 | 449 |