[MIPS] IP28: switch to "normal" mode after PROM no longer needed

SGI-IP28 is running in so called slow mode, when kernel is started from the PROM. PROM calls must be done in slow mode otherwise the PROM will issue an error. To get better memory performance we now switch to normal mode, when the PROM is no longer needed. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

[MIPS] IP28: switch to "normal" mode after PROM no longer needed
SGI-IP28 is running in so called slow mode, when kernel is started from the PROM. PROM calls must be done in slow mode otherwise the PROM will issue an error. To get better memory performance we now switch to normal mode, when the PROM is no longer needed. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Thomas Bogendoerfer · Ralf Baechle
1 parent c3dd3de789
Showing 2 changed files with 40 additions and 0 deletions Side-by-side Diff
arch/mips/sgi-ip22/ip22-mc.c
include/asm-mips/barrier.h
@@ -208,5 +208,31 @@
 void __init prom_meminit(void) {}
 void __init prom_free_prom_memory(void)
 {
+#ifdef CONFIG_SGI_IP28
+	u32 mconfig1;
+	unsigned long flags;
+	spinlock_t lock;
+
+	/*
+	 * because ARCS accesses memory uncached we wait until ARCS
+	 * isn't needed any longer, before we switch from slow to
+	 * normal mode
+	 */
+	spin_lock_irqsave(&lock, flags);
+	mconfig1 = sgimc->mconfig1;
+	/* map ECC register */
+	sgimc->mconfig1 = (mconfig1 & 0xffff0000) | 0x2060;
+	iob();
+	/* switch to normal mode */
+	*(unsigned long *)PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;
+	iob();
+	/* reduce WR_COL */
+	sgimc->cmacc = (sgimc->cmacc & ~0xf) | 4;
+	iob();
+	/* restore old config */
+	sgimc->mconfig1 = mconfig1;
+	iob();
+	spin_unlock_irqrestore(&lock, flags);
+#endif
 }
@@ -92,11 +92,25 @@
 #define fast_wmb()	__sync()
 #define fast_rmb()	__sync()
 #define fast_mb()	__sync()
+#ifdef CONFIG_SGI_IP28
 #define fast_iob()				\
+	__asm__ __volatile__(			\
+		".set	push\n\t"		\
+		".set	noreorder\n\t"		\
+		"lw	$0,%0\n\t"		\
+		"sync\n\t"			\
+		"lw	$0,%0\n\t"		\
+		".set	pop"			\
+		: /* no output */		\
+		: "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
+		: "memory")
+#else
+#define fast_iob()				\
 	do {					\
 		__sync();			\
 		__fast_iob();			\
 	} while (0)
+#endif
  
 #ifdef CONFIG_CPU_HAS_WB
...	...	@@ -208,5 +208,31 @@
208	208	void __init prom_meminit(void) {}
209	209	void __init prom_free_prom_memory(void)
210	210	{
	211	+#ifdef CONFIG_SGI_IP28
	212	+ u32 mconfig1;
	213	+ unsigned long flags;
	214	+ spinlock_t lock;
	215	+
	216	+ /*
	217	+ * because ARCS accesses memory uncached we wait until ARCS
	218	+ * isn't needed any longer, before we switch from slow to
	219	+ * normal mode
	220	+ */
	221	+ spin_lock_irqsave(&lock, flags);
	222	+ mconfig1 = sgimc->mconfig1;
	223	+ /* map ECC register */
	224	+ sgimc->mconfig1 = (mconfig1 & 0xffff0000) \| 0x2060;
	225	+ iob();
	226	+ /* switch to normal mode */
	227	+ (unsigned long )PHYS_TO_XKSEG_UNCACHED(0x60000000) = 0;
	228	+ iob();
	229	+ /* reduce WR_COL */
	230	+ sgimc->cmacc = (sgimc->cmacc & ~0xf) \| 4;
	231	+ iob();
	232	+ /* restore old config */
	233	+ sgimc->mconfig1 = mconfig1;
	234	+ iob();
	235	+ spin_unlock_irqrestore(&lock, flags);
	236	+#endif
211	237	}
...	...	@@ -92,11 +92,25 @@
92	92	#define fast_wmb() __sync()
93	93	#define fast_rmb() __sync()
94	94	#define fast_mb() __sync()
	95	+#ifdef CONFIG_SGI_IP28
95	96	#define fast_iob() \
	97	+ __asm__ __volatile__( \
	98	+ ".set push\n\t" \
	99	+ ".set noreorder\n\t" \
	100	+ "lw $0,%0\n\t" \
	101	+ "sync\n\t" \
	102	+ "lw $0,%0\n\t" \
	103	+ ".set pop" \
	104	+ : /* no output */ \
	105	+ : "m" ((int )CKSEG1ADDR(0x1fa00004)) \
	106	+ : "memory")
	107	+#else
	108	+#define fast_iob() \
96	109	do { \
97	110	__sync(); \
98	111	__fast_iob(); \
99	112	} while (0)
	113	+#endif
100	114
101	115	#ifdef CONFIG_CPU_HAS_WB
102	116