Commit 7a7868326d77416018e8f3b4c4697a3c57444549

Authored by Michael Ellerman
Committed by Benjamin Herrenschmidt
1 parent 240686c136

powerpc/perf: Add an explict flag indicating presence of SLOT field

In perf_ip_adjust() we potentially use the MMCRA[SLOT] field to adjust
the reported IP of a sampled instruction.

Currently the logic is written so that if the backend does NOT have
the PPMU_ALT_SIPR flag set then we assume MMCRA[SLOT] exists.

However on power8 we do not want to set ALT_SIPR (it's in a third
location), and we also do not have MMCRA[SLOT].

So add a new flag which only indicates whether MMCRA[SLOT] exists.

Naively we'd set it on everything except power6/7, because they set
ALT_SIPR, and we've reversed the polarity of the flag. But it's more
complicated than that.

mpc7450 is 32-bit, and uses its own version of perf_ip_adjust()
which doesn't use MMCRA[SLOT], so it doesn't need the new flag set and
the behaviour is unchanged.

PPC970 (and I assume power4) don't have MMCRA[SLOT], so shouldn't have
the new flag set. This is a behaviour change on those cpus, though we
were probably getting lucky and the bits in question were 0.

power5 and power5+ set the new flag, behaviour unchanged.

power6 & power7 do not set the new flag, behaviour unchanged.

Signed-off-by: Michael Ellerman <michael@ellerman.id.au>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

Showing 4 changed files with 5 additions and 2 deletions Side-by-side Diff

arch/powerpc/include/asm/perf_event_server.h
... ... @@ -52,6 +52,7 @@
52 52 #define PPMU_NO_SIPR 0x00000004 /* no SIPR/HV in MMCRA at all */
53 53 #define PPMU_NO_CONT_SAMPLING 0x00000008 /* no continuous sampling */
54 54 #define PPMU_SIAR_VALID 0x00000010 /* Processor has SIAR Valid bit */
  55 +#define PPMU_HAS_SSLOT 0x00000020 /* Has sampled slot in MMCRA */
55 56  
56 57 /*
57 58 * Values for flags to get_alternatives()
arch/powerpc/perf/core-book3s.c
... ... @@ -98,11 +98,12 @@
98 98 {
99 99 unsigned long mmcra = regs->dsisr;
100 100  
101   - if ((mmcra & MMCRA_SAMPLE_ENABLE) && !(ppmu->flags & PPMU_ALT_SIPR)) {
  101 + if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
102 102 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
103 103 if (slot > 1)
104 104 return 4 * (slot - 1);
105 105 }
  106 +
106 107 return 0;
107 108 }
108 109  
arch/powerpc/perf/power5+-pmu.c
... ... @@ -671,7 +671,7 @@
671 671 .get_alternatives = power5p_get_alternatives,
672 672 .disable_pmc = power5p_disable_pmc,
673 673 .limited_pmc_event = power5p_limited_pmc_event,
674   - .flags = PPMU_LIMITED_PMC5_6,
  674 + .flags = PPMU_LIMITED_PMC5_6 | PPMU_HAS_SSLOT,
675 675 .n_generic = ARRAY_SIZE(power5p_generic_events),
676 676 .generic_events = power5p_generic_events,
677 677 .cache_events = &power5p_cache_events,
arch/powerpc/perf/power5-pmu.c
... ... @@ -615,6 +615,7 @@
615 615 .n_generic = ARRAY_SIZE(power5_generic_events),
616 616 .generic_events = power5_generic_events,
617 617 .cache_events = &power5_cache_events,
  618 + .flags = PPMU_HAS_SSLOT,
618 619 };
619 620  
620 621 static int __init init_power5_pmu(void)