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Commit 7ca5dc145bc7daddd8aed8bbda46b74af9cebefc

Authored by Florian Fainelli
Committed by Ralf Baechle
1 parent 7c5371c403
Exists in master and in 7 other branches imx_3.0.35_4.1.0, imx_3.10.17_1.0.1_ga, imx_3.10.53_1.1.0_ga, imx_3.14.28_1.0.0_ga, smarc-imx_3.10.53_1.1.0_ga, smarc-imx_3.14.28_1.0.0_ga, smarc-l5.0.0_1.0.0-ga

MIPS: Add support for Texas Instruments AR7 System-on-a-Chip 

This patch adds support for the Texas Instruments AR7 System-on-a-Chip.
It supports the TNETD7100, 7200 and 7300 versions of the SoC.

Signed-off-by: Matteo Croce <matteo@openwrt.org>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
Signed-off-by: Eugene Konev <ejka@openwrt.org>
Signed-off-by: Nicolas Thill <nico@openwrt.org>
Signed-off-by: Florian Fainelli <florian@openwrt.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

Showing 18 changed files with 3307 additions and 0 deletions Side-by-side Diff

... ... @@ -22,6 +22,26 @@
22 22 config MACH_ALCHEMY
23 23 bool "Alchemy processor based machines"
24 24  
  25 +config AR7
  26 + bool "Texas Instruments AR7"
  27 + select BOOT_ELF32
  28 + select DMA_NONCOHERENT
  29 + select CEVT_R4K
  30 + select CSRC_R4K
  31 + select IRQ_CPU
  32 + select NO_EXCEPT_FILL
  33 + select SWAP_IO_SPACE
  34 + select SYS_HAS_CPU_MIPS32_R1
  35 + select SYS_HAS_EARLY_PRINTK
  36 + select SYS_SUPPORTS_32BIT_KERNEL
  37 + select SYS_SUPPORTS_LITTLE_ENDIAN
  38 + select GENERIC_GPIO
  39 + select GCD
  40 + select VLYNQ
  41 + help
  42 + Support for the Texas Instruments AR7 System-on-a-Chip
  43 + family: TNETD7100, 7200 and 7300.
  44 +
25 45 config BASLER_EXCITE
26 46 bool "Basler eXcite smart camera"
27 47 select CEVT_R4K
... ... @@ -173,6 +173,13 @@
173 173 #
174 174  
175 175 #
  176 +# Texas Instruments AR7
  177 +#
  178 +core-$(CONFIG_AR7) += arch/mips/ar7/
  179 +cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7
  180 +load-$(CONFIG_AR7) += 0xffffffff94100000
  181 +
  182 +#
176 183 # Acer PICA 61, Mips Magnum 4000 and Olivetti M700.
177 184 #
178 185 core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/
arch/mips/ar7/Makefile
Diff comments   View file @ 7ca5dc1
  1 +
  2 +obj-y := \
  3 + prom.o \
  4 + setup.o \
  5 + memory.o \
  6 + irq.o \
  7 + time.o \
  8 + platform.o \
  9 + gpio.o \
  10 + clock.o
arch/mips/ar7/clock.c
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  3 + * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
  4 + *
  5 + * This program is free software; you can redistribute it and/or modify
  6 + * it under the terms of the GNU General Public License as published by
  7 + * the Free Software Foundation; either version 2 of the License, or
  8 + * (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18 + */
  19 +
  20 +#include <linux/kernel.h>
  21 +#include <linux/init.h>
  22 +#include <linux/types.h>
  23 +#include <linux/module.h>
  24 +#include <linux/delay.h>
  25 +#include <linux/gcd.h>
  26 +#include <linux/io.h>
  27 +
  28 +#include <asm/addrspace.h>
  29 +#include <asm/mach-ar7/ar7.h>
  30 +
  31 +#define BOOT_PLL_SOURCE_MASK 0x3
  32 +#define CPU_PLL_SOURCE_SHIFT 16
  33 +#define BUS_PLL_SOURCE_SHIFT 14
  34 +#define USB_PLL_SOURCE_SHIFT 18
  35 +#define DSP_PLL_SOURCE_SHIFT 22
  36 +#define BOOT_PLL_SOURCE_AFE 0
  37 +#define BOOT_PLL_SOURCE_BUS 0
  38 +#define BOOT_PLL_SOURCE_REF 1
  39 +#define BOOT_PLL_SOURCE_XTAL 2
  40 +#define BOOT_PLL_SOURCE_CPU 3
  41 +#define BOOT_PLL_BYPASS 0x00000020
  42 +#define BOOT_PLL_ASYNC_MODE 0x02000000
  43 +#define BOOT_PLL_2TO1_MODE 0x00008000
  44 +
  45 +#define TNETD7200_CLOCK_ID_CPU 0
  46 +#define TNETD7200_CLOCK_ID_DSP 1
  47 +#define TNETD7200_CLOCK_ID_USB 2
  48 +
  49 +#define TNETD7200_DEF_CPU_CLK 211000000
  50 +#define TNETD7200_DEF_DSP_CLK 125000000
  51 +#define TNETD7200_DEF_USB_CLK 48000000
  52 +
  53 +struct tnetd7300_clock {
  54 + u32 ctrl;
  55 +#define PREDIV_MASK 0x001f0000
  56 +#define PREDIV_SHIFT 16
  57 +#define POSTDIV_MASK 0x0000001f
  58 + u32 unused1[3];
  59 + u32 pll;
  60 +#define MUL_MASK 0x0000f000
  61 +#define MUL_SHIFT 12
  62 +#define PLL_MODE_MASK 0x00000001
  63 +#define PLL_NDIV 0x00000800
  64 +#define PLL_DIV 0x00000002
  65 +#define PLL_STATUS 0x00000001
  66 + u32 unused2[3];
  67 +};
  68 +
  69 +struct tnetd7300_clocks {
  70 + struct tnetd7300_clock bus;
  71 + struct tnetd7300_clock cpu;
  72 + struct tnetd7300_clock usb;
  73 + struct tnetd7300_clock dsp;
  74 +};
  75 +
  76 +struct tnetd7200_clock {
  77 + u32 ctrl;
  78 + u32 unused1[3];
  79 +#define DIVISOR_ENABLE_MASK 0x00008000
  80 + u32 mul;
  81 + u32 prediv;
  82 + u32 postdiv;
  83 + u32 postdiv2;
  84 + u32 unused2[6];
  85 + u32 cmd;
  86 + u32 status;
  87 + u32 cmden;
  88 + u32 padding[15];
  89 +};
  90 +
  91 +struct tnetd7200_clocks {
  92 + struct tnetd7200_clock cpu;
  93 + struct tnetd7200_clock dsp;
  94 + struct tnetd7200_clock usb;
  95 +};
  96 +
  97 +int ar7_cpu_clock = 150000000;
  98 +EXPORT_SYMBOL(ar7_cpu_clock);
  99 +int ar7_bus_clock = 125000000;
  100 +EXPORT_SYMBOL(ar7_bus_clock);
  101 +int ar7_dsp_clock;
  102 +EXPORT_SYMBOL(ar7_dsp_clock);
  103 +
  104 +static void approximate(int base, int target, int *prediv,
  105 + int *postdiv, int *mul)
  106 +{
  107 + int i, j, k, freq, res = target;
  108 + for (i = 1; i <= 16; i++)
  109 + for (j = 1; j <= 32; j++)
  110 + for (k = 1; k <= 32; k++) {
  111 + freq = abs(base / j * i / k - target);
  112 + if (freq < res) {
  113 + res = freq;
  114 + *mul = i;
  115 + *prediv = j;
  116 + *postdiv = k;
  117 + }
  118 + }
  119 +}
  120 +
  121 +static void calculate(int base, int target, int *prediv, int *postdiv,
  122 + int *mul)
  123 +{
  124 + int tmp_gcd, tmp_base, tmp_freq;
  125 +
  126 + for (*prediv = 1; *prediv <= 32; (*prediv)++) {
  127 + tmp_base = base / *prediv;
  128 + tmp_gcd = gcd(target, tmp_base);
  129 + *mul = target / tmp_gcd;
  130 + *postdiv = tmp_base / tmp_gcd;
  131 + if ((*mul < 1) || (*mul >= 16))
  132 + continue;
  133 + if ((*postdiv > 0) & (*postdiv <= 32))
  134 + break;
  135 + }
  136 +
  137 + if (base / *prediv * *mul / *postdiv != target) {
  138 + approximate(base, target, prediv, postdiv, mul);
  139 + tmp_freq = base / *prediv * *mul / *postdiv;
  140 + printk(KERN_WARNING
  141 + "Adjusted requested frequency %d to %d\n",
  142 + target, tmp_freq);
  143 + }
  144 +
  145 + printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n",
  146 + *prediv, *postdiv, *mul);
  147 +}
  148 +
  149 +static int tnetd7300_dsp_clock(void)
  150 +{
  151 + u32 didr1, didr2;
  152 + u8 rev = ar7_chip_rev();
  153 + didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18));
  154 + didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c));
  155 + if (didr2 & (1 << 23))
  156 + return 0;
  157 + if ((rev >= 0x23) && (rev != 0x57))
  158 + return 250000000;
  159 + if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22))
  160 + > 4208000)
  161 + return 250000000;
  162 + return 0;
  163 +}
  164 +
  165 +static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock,
  166 + u32 *bootcr, u32 bus_clock)
  167 +{
  168 + int product;
  169 + int base_clock = AR7_REF_CLOCK;
  170 + u32 ctrl = readl(&clock->ctrl);
  171 + u32 pll = readl(&clock->pll);
  172 + int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1;
  173 + int postdiv = (ctrl & POSTDIV_MASK) + 1;
  174 + int divisor = prediv * postdiv;
  175 + int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1;
  176 +
  177 + switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
  178 + case BOOT_PLL_SOURCE_BUS:
  179 + base_clock = bus_clock;
  180 + break;
  181 + case BOOT_PLL_SOURCE_REF:
  182 + base_clock = AR7_REF_CLOCK;
  183 + break;
  184 + case BOOT_PLL_SOURCE_XTAL:
  185 + base_clock = AR7_XTAL_CLOCK;
  186 + break;
  187 + case BOOT_PLL_SOURCE_CPU:
  188 + base_clock = ar7_cpu_clock;
  189 + break;
  190 + }
  191 +
  192 + if (*bootcr & BOOT_PLL_BYPASS)
  193 + return base_clock / divisor;
  194 +
  195 + if ((pll & PLL_MODE_MASK) == 0)
  196 + return (base_clock >> (mul / 16 + 1)) / divisor;
  197 +
  198 + if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) {
  199 + product = (mul & 1) ?
  200 + (base_clock * mul) >> 1 :
  201 + (base_clock * (mul - 1)) >> 2;
  202 + return product / divisor;
  203 + }
  204 +
  205 + if (mul == 16)
  206 + return base_clock / divisor;
  207 +
  208 + return base_clock * mul / divisor;
  209 +}
  210 +
  211 +static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock,
  212 + u32 *bootcr, u32 frequency)
  213 +{
  214 + int prediv, postdiv, mul;
  215 + int base_clock = ar7_bus_clock;
  216 +
  217 + switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) {
  218 + case BOOT_PLL_SOURCE_BUS:
  219 + base_clock = ar7_bus_clock;
  220 + break;
  221 + case BOOT_PLL_SOURCE_REF:
  222 + base_clock = AR7_REF_CLOCK;
  223 + break;
  224 + case BOOT_PLL_SOURCE_XTAL:
  225 + base_clock = AR7_XTAL_CLOCK;
  226 + break;
  227 + case BOOT_PLL_SOURCE_CPU:
  228 + base_clock = ar7_cpu_clock;
  229 + break;
  230 + }
  231 +
  232 + calculate(base_clock, frequency, &prediv, &postdiv, &mul);
  233 +
  234 + writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl);
  235 + msleep(1);
  236 + writel(4, &clock->pll);
  237 + while (readl(&clock->pll) & PLL_STATUS)
  238 + ;
  239 + writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll);
  240 + msleep(75);
  241 +}
  242 +
  243 +static void __init tnetd7300_init_clocks(void)
  244 +{
  245 + u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
  246 + struct tnetd7300_clocks *clocks =
  247 + ioremap_nocache(UR8_REGS_CLOCKS,
  248 + sizeof(struct tnetd7300_clocks));
  249 +
  250 + ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT,
  251 + &clocks->bus, bootcr, AR7_AFE_CLOCK);
  252 +
  253 + if (*bootcr & BOOT_PLL_ASYNC_MODE)
  254 + ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT,
  255 + &clocks->cpu, bootcr, AR7_AFE_CLOCK);
  256 + else
  257 + ar7_cpu_clock = ar7_bus_clock;
  258 +
  259 + if (ar7_dsp_clock == 250000000)
  260 + tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp,
  261 + bootcr, ar7_dsp_clock);
  262 +
  263 + iounmap(clocks);
  264 + iounmap(bootcr);
  265 +}
  266 +
  267 +static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock,
  268 + u32 *bootcr, u32 bus_clock)
  269 +{
  270 + int divisor = ((readl(&clock->prediv) & 0x1f) + 1) *
  271 + ((readl(&clock->postdiv) & 0x1f) + 1);
  272 +
  273 + if (*bootcr & BOOT_PLL_BYPASS)
  274 + return base / divisor;
  275 +
  276 + return base * ((readl(&clock->mul) & 0xf) + 1) / divisor;
  277 +}
  278 +
  279 +
  280 +static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock,
  281 + int prediv, int postdiv, int postdiv2, int mul, u32 frequency)
  282 +{
  283 + printk(KERN_INFO
  284 + "Clocks: base = %d, frequency = %u, prediv = %d, "
  285 + "postdiv = %d, postdiv2 = %d, mul = %d\n",
  286 + base, frequency, prediv, postdiv, postdiv2, mul);
  287 +
  288 + writel(0, &clock->ctrl);
  289 + writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv);
  290 + writel((mul - 1) & 0xF, &clock->mul);
  291 +
  292 + while (readl(&clock->status) & 0x1)
  293 + ; /* nop */
  294 +
  295 + writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv);
  296 +
  297 + writel(readl(&clock->cmden) | 1, &clock->cmden);
  298 + writel(readl(&clock->cmd) | 1, &clock->cmd);
  299 +
  300 + while (readl(&clock->status) & 0x1)
  301 + ; /* nop */
  302 +
  303 + writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2);
  304 +
  305 + writel(readl(&clock->cmden) | 1, &clock->cmden);
  306 + writel(readl(&clock->cmd) | 1, &clock->cmd);
  307 +
  308 + while (readl(&clock->status) & 0x1)
  309 + ; /* nop */
  310 +
  311 + writel(readl(&clock->ctrl) | 1, &clock->ctrl);
  312 +}
  313 +
  314 +static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr)
  315 +{
  316 + if (*bootcr & BOOT_PLL_ASYNC_MODE)
  317 + /* Async */
  318 + switch (clock_id) {
  319 + case TNETD7200_CLOCK_ID_DSP:
  320 + return AR7_REF_CLOCK;
  321 + default:
  322 + return AR7_AFE_CLOCK;
  323 + }
  324 + else
  325 + /* Sync */
  326 + if (*bootcr & BOOT_PLL_2TO1_MODE)
  327 + /* 2:1 */
  328 + switch (clock_id) {
  329 + case TNETD7200_CLOCK_ID_DSP:
  330 + return AR7_REF_CLOCK;
  331 + default:
  332 + return AR7_AFE_CLOCK;
  333 + }
  334 + else
  335 + /* 1:1 */
  336 + return AR7_REF_CLOCK;
  337 +}
  338 +
  339 +
  340 +static void __init tnetd7200_init_clocks(void)
  341 +{
  342 + u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4);
  343 + struct tnetd7200_clocks *clocks =
  344 + ioremap_nocache(AR7_REGS_CLOCKS,
  345 + sizeof(struct tnetd7200_clocks));
  346 + int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv;
  347 + int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv;
  348 + int usb_base, usb_mul, usb_prediv, usb_postdiv;
  349 +
  350 + cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr);
  351 + dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr);
  352 +
  353 + if (*bootcr & BOOT_PLL_ASYNC_MODE) {
  354 + printk(KERN_INFO "Clocks: Async mode\n");
  355 +
  356 + printk(KERN_INFO "Clocks: Setting DSP clock\n");
  357 + calculate(dsp_base, TNETD7200_DEF_DSP_CLK,
  358 + &dsp_prediv, &dsp_postdiv, &dsp_mul);
  359 + ar7_bus_clock =
  360 + ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv;
  361 + tnetd7200_set_clock(dsp_base, &clocks->dsp,
  362 + dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2,
  363 + ar7_bus_clock);
  364 +
  365 + printk(KERN_INFO "Clocks: Setting CPU clock\n");
  366 + calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
  367 + &cpu_postdiv, &cpu_mul);
  368 + ar7_cpu_clock =
  369 + ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv;
  370 + tnetd7200_set_clock(cpu_base, &clocks->cpu,
  371 + cpu_prediv, cpu_postdiv, -1, cpu_mul,
  372 + ar7_cpu_clock);
  373 +
  374 + } else
  375 + if (*bootcr & BOOT_PLL_2TO1_MODE) {
  376 + printk(KERN_INFO "Clocks: Sync 2:1 mode\n");
  377 +
  378 + printk(KERN_INFO "Clocks: Setting CPU clock\n");
  379 + calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv,
  380 + &cpu_postdiv, &cpu_mul);
  381 + ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul)
  382 + / cpu_postdiv;
  383 + tnetd7200_set_clock(cpu_base, &clocks->cpu,
  384 + cpu_prediv, cpu_postdiv, -1, cpu_mul,
  385 + ar7_cpu_clock);
  386 +
  387 + printk(KERN_INFO "Clocks: Setting DSP clock\n");
  388 + calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
  389 + &dsp_postdiv, &dsp_mul);
  390 + ar7_bus_clock = ar7_cpu_clock / 2;
  391 + tnetd7200_set_clock(dsp_base, &clocks->dsp,
  392 + dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
  393 + dsp_mul * 2, ar7_bus_clock);
  394 + } else {
  395 + printk(KERN_INFO "Clocks: Sync 1:1 mode\n");
  396 +
  397 + printk(KERN_INFO "Clocks: Setting DSP clock\n");
  398 + calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv,
  399 + &dsp_postdiv, &dsp_mul);
  400 + ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul)
  401 + / dsp_postdiv;
  402 + tnetd7200_set_clock(dsp_base, &clocks->dsp,
  403 + dsp_prediv, dsp_postdiv * 2, dsp_postdiv,
  404 + dsp_mul * 2, ar7_bus_clock);
  405 +
  406 + ar7_cpu_clock = ar7_bus_clock;
  407 + }
  408 +
  409 + printk(KERN_INFO "Clocks: Setting USB clock\n");
  410 + usb_base = ar7_bus_clock;
  411 + calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv,
  412 + &usb_postdiv, &usb_mul);
  413 + tnetd7200_set_clock(usb_base, &clocks->usb,
  414 + usb_prediv, usb_postdiv, -1, usb_mul,
  415 + TNETD7200_DEF_USB_CLK);
  416 +
  417 + ar7_dsp_clock = ar7_cpu_clock;
  418 +
  419 + iounmap(clocks);
  420 + iounmap(bootcr);
  421 +}
  422 +
  423 +int __init ar7_init_clocks(void)
  424 +{
  425 + switch (ar7_chip_id()) {
  426 + case AR7_CHIP_7100:
  427 + case AR7_CHIP_7200:
  428 + tnetd7200_init_clocks();
  429 + break;
  430 + case AR7_CHIP_7300:
  431 + ar7_dsp_clock = tnetd7300_dsp_clock();
  432 + tnetd7300_init_clocks();
  433 + break;
  434 + default:
  435 + break;
  436 + }
  437 +
  438 + return 0;
  439 +}
  440 +arch_initcall(ar7_init_clocks);
arch/mips/ar7/gpio.c
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  3 + * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
  4 + *
  5 + * This program is free software; you can redistribute it and/or modify
  6 + * it under the terms of the GNU General Public License as published by
  7 + * the Free Software Foundation; either version 2 of the License, or
  8 + * (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18 + */
  19 +
  20 +#include <linux/module.h>
  21 +
  22 +#include <asm/mach-ar7/gpio.h>
  23 +
  24 +static const char *ar7_gpio_list[AR7_GPIO_MAX];
  25 +
  26 +int gpio_request(unsigned gpio, const char *label)
  27 +{
  28 + if (gpio >= AR7_GPIO_MAX)
  29 + return -EINVAL;
  30 +
  31 + if (ar7_gpio_list[gpio])
  32 + return -EBUSY;
  33 +
  34 + if (label)
  35 + ar7_gpio_list[gpio] = label;
  36 + else
  37 + ar7_gpio_list[gpio] = "busy";
  38 +
  39 + return 0;
  40 +}
  41 +EXPORT_SYMBOL(gpio_request);
  42 +
  43 +void gpio_free(unsigned gpio)
  44 +{
  45 + BUG_ON(!ar7_gpio_list[gpio]);
  46 + ar7_gpio_list[gpio] = NULL;
  47 +}
  48 +EXPORT_SYMBOL(gpio_free);
  1 +/*
  2 + * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
  3 + * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
  4 + *
  5 + * This program is free software; you can redistribute it and/or modify
  6 + * it under the terms of the GNU General Public License as published by
  7 + * the Free Software Foundation; either version 2 of the License, or
  8 + * (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18 + */
  19 +
  20 +#include <linux/interrupt.h>
  21 +#include <linux/io.h>
  22 +
  23 +#include <asm/irq_cpu.h>
  24 +#include <asm/mipsregs.h>
  25 +#include <asm/mach-ar7/ar7.h>
  26 +
  27 +#define EXCEPT_OFFSET 0x80
  28 +#define PACE_OFFSET 0xA0
  29 +#define CHNLS_OFFSET 0x200
  30 +
  31 +#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10)
  32 +#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8)
  33 +#define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */
  34 +#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */
  35 +#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */
  36 +#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */
  37 +#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */
  38 +#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */
  39 +#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */
  40 +#define PIR_OFFSET (0x40)
  41 +#define MSR_OFFSET (0x44)
  42 +#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */
  43 +#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */
  44 +
  45 +#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr))
  46 +
  47 +#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4))
  48 +
  49 +static int ar7_irq_base;
  50 +
  51 +static void ar7_unmask_irq(unsigned int irq)
  52 +{
  53 + writel(1 << ((irq - ar7_irq_base) % 32),
  54 + REG(ESR_OFFSET(irq - ar7_irq_base)));
  55 +}
  56 +
  57 +static void ar7_mask_irq(unsigned int irq)
  58 +{
  59 + writel(1 << ((irq - ar7_irq_base) % 32),
  60 + REG(ECR_OFFSET(irq - ar7_irq_base)));
  61 +}
  62 +
  63 +static void ar7_ack_irq(unsigned int irq)
  64 +{
  65 + writel(1 << ((irq - ar7_irq_base) % 32),
  66 + REG(CR_OFFSET(irq - ar7_irq_base)));
  67 +}
  68 +
  69 +static void ar7_unmask_sec_irq(unsigned int irq)
  70 +{
  71 + writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));
  72 +}
  73 +
  74 +static void ar7_mask_sec_irq(unsigned int irq)
  75 +{
  76 + writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));
  77 +}
  78 +
  79 +static void ar7_ack_sec_irq(unsigned int irq)
  80 +{
  81 + writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));
  82 +}
  83 +
  84 +static struct irq_chip ar7_irq_type = {
  85 + .name = "AR7",
  86 + .unmask = ar7_unmask_irq,
  87 + .mask = ar7_mask_irq,
  88 + .ack = ar7_ack_irq
  89 +};
  90 +
  91 +static struct irq_chip ar7_sec_irq_type = {
  92 + .name = "AR7",
  93 + .unmask = ar7_unmask_sec_irq,
  94 + .mask = ar7_mask_sec_irq,
  95 + .ack = ar7_ack_sec_irq,
  96 +};
  97 +
  98 +static struct irqaction ar7_cascade_action = {
  99 + .handler = no_action,
  100 + .name = "AR7 cascade interrupt"
  101 +};
  102 +
  103 +static void __init ar7_irq_init(int base)
  104 +{
  105 + int i;
  106 + /*
  107 + * Disable interrupts and clear pending
  108 + */
  109 + writel(0xffffffff, REG(ECR_OFFSET(0)));
  110 + writel(0xff, REG(ECR_OFFSET(32)));
  111 + writel(0xffffffff, REG(SEC_ECR_OFFSET));
  112 + writel(0xffffffff, REG(CR_OFFSET(0)));
  113 + writel(0xff, REG(CR_OFFSET(32)));
  114 + writel(0xffffffff, REG(SEC_CR_OFFSET));
  115 +
  116 + ar7_irq_base = base;
  117 +
  118 + for (i = 0; i < 40; i++) {
  119 + writel(i, REG(CHNL_OFFSET(i)));
  120 + /* Primary IRQ's */
  121 + set_irq_chip_and_handler(base + i, &ar7_irq_type,
  122 + handle_level_irq);
  123 + /* Secondary IRQ's */
  124 + if (i < 32)
  125 + set_irq_chip_and_handler(base + i + 40,
  126 + &ar7_sec_irq_type,
  127 + handle_level_irq);
  128 + }
  129 +
  130 + setup_irq(2, &ar7_cascade_action);
  131 + setup_irq(ar7_irq_base, &ar7_cascade_action);
  132 + set_c0_status(IE_IRQ0);
  133 +}
  134 +
  135 +void __init arch_init_irq(void)
  136 +{
  137 + mips_cpu_irq_init();
  138 + ar7_irq_init(8);
  139 +}
  140 +
  141 +static void ar7_cascade(void)
  142 +{
  143 + u32 status;
  144 + int i, irq;
  145 +
  146 + /* Primary IRQ's */
  147 + irq = readl(REG(PIR_OFFSET)) & 0x3f;
  148 + if (irq) {
  149 + do_IRQ(ar7_irq_base + irq);
  150 + return;
  151 + }
  152 +
  153 + /* Secondary IRQ's are cascaded through primary '0' */
  154 + writel(1, REG(CR_OFFSET(irq)));
  155 + status = readl(REG(SEC_SR_OFFSET));
  156 + for (i = 0; i < 32; i++) {
  157 + if (status & 1) {
  158 + do_IRQ(ar7_irq_base + i + 40);
  159 + return;
  160 + }
  161 + status >>= 1;
  162 + }
  163 +
  164 + spurious_interrupt();
  165 +}
  166 +
  167 +asmlinkage void plat_irq_dispatch(void)
  168 +{
  169 + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
  170 + if (pending & STATUSF_IP7) /* cpu timer */
  171 + do_IRQ(7);
  172 + else if (pending & STATUSF_IP2) /* int0 hardware line */
  173 + ar7_cascade();
  174 + else
  175 + spurious_interrupt();
  176 +}
arch/mips/ar7/memory.c
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
  3 + * Copyright (C) 2007 Eugene Konev <ejka@openwrt.org>
  4 + *
  5 + * This program is free software; you can redistribute it and/or modify
  6 + * it under the terms of the GNU General Public License as published by
  7 + * the Free Software Foundation; either version 2 of the License, or
  8 + * (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18 + */
  19 +#include <linux/bootmem.h>
  20 +#include <linux/init.h>
  21 +#include <linux/mm.h>
  22 +#include <linux/module.h>
  23 +#include <linux/pfn.h>
  24 +#include <linux/proc_fs.h>
  25 +#include <linux/string.h>
  26 +#include <linux/swap.h>
  27 +
  28 +#include <asm/bootinfo.h>
  29 +#include <asm/page.h>
  30 +#include <asm/sections.h>
  31 +
  32 +#include <asm/mach-ar7/ar7.h>
  33 +#include <asm/mips-boards/prom.h>
  34 +
  35 +static int __init memsize(void)
  36 +{
  37 + u32 size = (64 << 20);
  38 + u32 *addr = (u32 *)KSEG1ADDR(AR7_SDRAM_BASE + size - 4);
  39 + u32 *kernel_end = (u32 *)KSEG1ADDR(CPHYSADDR((u32)&_end));
  40 + u32 *tmpaddr = addr;
  41 +
  42 + while (tmpaddr > kernel_end) {
  43 + *tmpaddr = (u32)tmpaddr;
  44 + size >>= 1;
  45 + tmpaddr -= size >> 2;
  46 + }
  47 +
  48 + do {
  49 + tmpaddr += size >> 2;
  50 + if (*tmpaddr != (u32)tmpaddr)
  51 + break;
  52 + size <<= 1;
  53 + } while (size < (64 << 20));
  54 +
  55 + writel(tmpaddr, &addr);
  56 +
  57 + return size;
  58 +}
  59 +
  60 +void __init prom_meminit(void)
  61 +{
  62 + unsigned long pages;
  63 +
  64 + pages = memsize() >> PAGE_SHIFT;
  65 + add_memory_region(PHYS_OFFSET, pages << PAGE_SHIFT,
  66 + BOOT_MEM_RAM);
  67 +}
  68 +
  69 +void __init prom_free_prom_memory(void)
  70 +{
  71 + /* Nothing to free */
  72 +}
arch/mips/ar7/platform.c
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
  3 + * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
  4 + *
  5 + * This program is free software; you can redistribute it and/or modify
  6 + * it under the terms of the GNU General Public License as published by
  7 + * the Free Software Foundation; either version 2 of the License, or
  8 + * (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18 + */
  19 +
  20 +#include <linux/init.h>
  21 +#include <linux/types.h>
  22 +#include <linux/module.h>
  23 +#include <linux/delay.h>
  24 +#include <linux/dma-mapping.h>
  25 +#include <linux/platform_device.h>
  26 +#include <linux/mtd/physmap.h>
  27 +#include <linux/serial.h>
  28 +#include <linux/serial_8250.h>
  29 +#include <linux/ioport.h>
  30 +#include <linux/io.h>
  31 +#include <linux/version.h>
  32 +#include <linux/vlynq.h>
  33 +#include <linux/leds.h>
  34 +#include <linux/string.h>
  35 +#include <linux/etherdevice.h>
  36 +
  37 +#include <asm/addrspace.h>
  38 +#include <asm/mach-ar7/ar7.h>
  39 +#include <asm/mach-ar7/gpio.h>
  40 +#include <asm/mach-ar7/prom.h>
  41 +
  42 +struct plat_vlynq_data {
  43 + struct plat_vlynq_ops ops;
  44 + int gpio_bit;
  45 + int reset_bit;
  46 +};
  47 +
  48 +
  49 +static int vlynq_on(struct vlynq_device *dev)
  50 +{
  51 + int result;
  52 + struct plat_vlynq_data *pdata = dev->dev.platform_data;
  53 +
  54 + result = gpio_request(pdata->gpio_bit, "vlynq");
  55 + if (result)
  56 + goto out;
  57 +
  58 + ar7_device_reset(pdata->reset_bit);
  59 +
  60 + result = ar7_gpio_disable(pdata->gpio_bit);
  61 + if (result)
  62 + goto out_enabled;
  63 +
  64 + result = ar7_gpio_enable(pdata->gpio_bit);
  65 + if (result)
  66 + goto out_enabled;
  67 +
  68 + result = gpio_direction_output(pdata->gpio_bit, 0);
  69 + if (result)
  70 + goto out_gpio_enabled;
  71 +
  72 + msleep(50);
  73 +
  74 + gpio_set_value(pdata->gpio_bit, 1);
  75 + msleep(50);
  76 +
  77 + return 0;
  78 +
  79 +out_gpio_enabled:
  80 + ar7_gpio_disable(pdata->gpio_bit);
  81 +out_enabled:
  82 + ar7_device_disable(pdata->reset_bit);
  83 + gpio_free(pdata->gpio_bit);
  84 +out:
  85 + return result;
  86 +}
  87 +
  88 +static void vlynq_off(struct vlynq_device *dev)
  89 +{
  90 + struct plat_vlynq_data *pdata = dev->dev.platform_data;
  91 + ar7_gpio_disable(pdata->gpio_bit);
  92 + gpio_free(pdata->gpio_bit);
  93 + ar7_device_disable(pdata->reset_bit);
  94 +}
  95 +
  96 +static struct resource physmap_flash_resource = {
  97 + .name = "mem",
  98 + .flags = IORESOURCE_MEM,
  99 + .start = 0x10000000,
  100 + .end = 0x107fffff,
  101 +};
  102 +
  103 +static struct resource cpmac_low_res[] = {
  104 + {
  105 + .name = "regs",
  106 + .flags = IORESOURCE_MEM,
  107 + .start = AR7_REGS_MAC0,
  108 + .end = AR7_REGS_MAC0 + 0x7ff,
  109 + },
  110 + {
  111 + .name = "irq",
  112 + .flags = IORESOURCE_IRQ,
  113 + .start = 27,
  114 + .end = 27,
  115 + },
  116 +};
  117 +
  118 +static struct resource cpmac_high_res[] = {
  119 + {
  120 + .name = "regs",
  121 + .flags = IORESOURCE_MEM,
  122 + .start = AR7_REGS_MAC1,
  123 + .end = AR7_REGS_MAC1 + 0x7ff,
  124 + },
  125 + {
  126 + .name = "irq",
  127 + .flags = IORESOURCE_IRQ,
  128 + .start = 41,
  129 + .end = 41,
  130 + },
  131 +};
  132 +
  133 +static struct resource vlynq_low_res[] = {
  134 + {
  135 + .name = "regs",
  136 + .flags = IORESOURCE_MEM,
  137 + .start = AR7_REGS_VLYNQ0,
  138 + .end = AR7_REGS_VLYNQ0 + 0xff,
  139 + },
  140 + {
  141 + .name = "irq",
  142 + .flags = IORESOURCE_IRQ,
  143 + .start = 29,
  144 + .end = 29,
  145 + },
  146 + {
  147 + .name = "mem",
  148 + .flags = IORESOURCE_MEM,
  149 + .start = 0x04000000,
  150 + .end = 0x04ffffff,
  151 + },
  152 + {
  153 + .name = "devirq",
  154 + .flags = IORESOURCE_IRQ,
  155 + .start = 80,
  156 + .end = 111,
  157 + },
  158 +};
  159 +
  160 +static struct resource vlynq_high_res[] = {
  161 + {
  162 + .name = "regs",
  163 + .flags = IORESOURCE_MEM,
  164 + .start = AR7_REGS_VLYNQ1,
  165 + .end = AR7_REGS_VLYNQ1 + 0xff,
  166 + },
  167 + {
  168 + .name = "irq",
  169 + .flags = IORESOURCE_IRQ,
  170 + .start = 33,
  171 + .end = 33,
  172 + },
  173 + {
  174 + .name = "mem",
  175 + .flags = IORESOURCE_MEM,
  176 + .start = 0x0c000000,
  177 + .end = 0x0cffffff,
  178 + },
  179 + {
  180 + .name = "devirq",
  181 + .flags = IORESOURCE_IRQ,
  182 + .start = 112,
  183 + .end = 143,
  184 + },
  185 +};
  186 +
  187 +static struct resource usb_res[] = {
  188 + {
  189 + .name = "regs",
  190 + .flags = IORESOURCE_MEM,
  191 + .start = AR7_REGS_USB,
  192 + .end = AR7_REGS_USB + 0xff,
  193 + },
  194 + {
  195 + .name = "irq",
  196 + .flags = IORESOURCE_IRQ,
  197 + .start = 32,
  198 + .end = 32,
  199 + },
  200 + {
  201 + .name = "mem",
  202 + .flags = IORESOURCE_MEM,
  203 + .start = 0x03400000,
  204 + .end = 0x034001fff,
  205 + },
  206 +};
  207 +
  208 +static struct physmap_flash_data physmap_flash_data = {
  209 + .width = 2,
  210 +};
  211 +
  212 +static struct plat_cpmac_data cpmac_low_data = {
  213 + .reset_bit = 17,
  214 + .power_bit = 20,
  215 + .phy_mask = 0x80000000,
  216 +};
  217 +
  218 +static struct plat_cpmac_data cpmac_high_data = {
  219 + .reset_bit = 21,
  220 + .power_bit = 22,
  221 + .phy_mask = 0x7fffffff,
  222 +};
  223 +
  224 +static struct plat_vlynq_data vlynq_low_data = {
  225 + .ops.on = vlynq_on,
  226 + .ops.off = vlynq_off,
  227 + .reset_bit = 20,
  228 + .gpio_bit = 18,
  229 +};
  230 +
  231 +static struct plat_vlynq_data vlynq_high_data = {
  232 + .ops.on = vlynq_on,
  233 + .ops.off = vlynq_off,
  234 + .reset_bit = 16,
  235 + .gpio_bit = 19,
  236 +};
  237 +
  238 +static struct platform_device physmap_flash = {
  239 + .id = 0,
  240 + .name = "physmap-flash",
  241 + .dev.platform_data = &physmap_flash_data,
  242 + .resource = &physmap_flash_resource,
  243 + .num_resources = 1,
  244 +};
  245 +
  246 +static u64 cpmac_dma_mask = DMA_32BIT_MASK;
  247 +static struct platform_device cpmac_low = {
  248 + .id = 0,
  249 + .name = "cpmac",
  250 + .dev = {
  251 + .dma_mask = &cpmac_dma_mask,
  252 + .coherent_dma_mask = DMA_32BIT_MASK,
  253 + .platform_data = &cpmac_low_data,
  254 + },
  255 + .resource = cpmac_low_res,
  256 + .num_resources = ARRAY_SIZE(cpmac_low_res),
  257 +};
  258 +
  259 +static struct platform_device cpmac_high = {
  260 + .id = 1,
  261 + .name = "cpmac",
  262 + .dev = {
  263 + .dma_mask = &cpmac_dma_mask,
  264 + .coherent_dma_mask = DMA_32BIT_MASK,
  265 + .platform_data = &cpmac_high_data,
  266 + },
  267 + .resource = cpmac_high_res,
  268 + .num_resources = ARRAY_SIZE(cpmac_high_res),
  269 +};
  270 +
  271 +static struct platform_device vlynq_low = {
  272 + .id = 0,
  273 + .name = "vlynq",
  274 + .dev.platform_data = &vlynq_low_data,
  275 + .resource = vlynq_low_res,
  276 + .num_resources = ARRAY_SIZE(vlynq_low_res),
  277 +};
  278 +
  279 +static struct platform_device vlynq_high = {
  280 + .id = 1,
  281 + .name = "vlynq",
  282 + .dev.platform_data = &vlynq_high_data,
  283 + .resource = vlynq_high_res,
  284 + .num_resources = ARRAY_SIZE(vlynq_high_res),
  285 +};
  286 +
  287 +
  288 +static struct gpio_led default_leds[] = {
  289 + {
  290 + .name = "status",
  291 + .gpio = 8,
  292 + .active_low = 1,
  293 + },
  294 +};
  295 +
  296 +static struct gpio_led dsl502t_leds[] = {
  297 + {
  298 + .name = "status",
  299 + .gpio = 9,
  300 + .active_low = 1,
  301 + },
  302 + {
  303 + .name = "ethernet",
  304 + .gpio = 7,
  305 + .active_low = 1,
  306 + },
  307 + {
  308 + .name = "usb",
  309 + .gpio = 12,
  310 + .active_low = 1,
  311 + },
  312 +};
  313 +
  314 +static struct gpio_led dg834g_leds[] = {
  315 + {
  316 + .name = "ppp",
  317 + .gpio = 6,
  318 + .active_low = 1,
  319 + },
  320 + {
  321 + .name = "status",
  322 + .gpio = 7,
  323 + .active_low = 1,
  324 + },
  325 + {
  326 + .name = "adsl",
  327 + .gpio = 8,
  328 + .active_low = 1,
  329 + },
  330 + {
  331 + .name = "wifi",
  332 + .gpio = 12,
  333 + .active_low = 1,
  334 + },
  335 + {
  336 + .name = "power",
  337 + .gpio = 14,
  338 + .active_low = 1,
  339 + .default_trigger = "default-on",
  340 + },
  341 +};
  342 +
  343 +static struct gpio_led fb_sl_leds[] = {
  344 + {
  345 + .name = "1",
  346 + .gpio = 7,
  347 + },
  348 + {
  349 + .name = "2",
  350 + .gpio = 13,
  351 + .active_low = 1,
  352 + },
  353 + {
  354 + .name = "3",
  355 + .gpio = 10,
  356 + .active_low = 1,
  357 + },
  358 + {
  359 + .name = "4",
  360 + .gpio = 12,
  361 + .active_low = 1,
  362 + },
  363 + {
  364 + .name = "5",
  365 + .gpio = 9,
  366 + .active_low = 1,
  367 + },
  368 +};
  369 +
  370 +static struct gpio_led fb_fon_leds[] = {
  371 + {
  372 + .name = "1",
  373 + .gpio = 8,
  374 + },
  375 + {
  376 + .name = "2",
  377 + .gpio = 3,
  378 + .active_low = 1,
  379 + },
  380 + {
  381 + .name = "3",
  382 + .gpio = 5,
  383 + },
  384 + {
  385 + .name = "4",
  386 + .gpio = 4,
  387 + .active_low = 1,
  388 + },
  389 + {
  390 + .name = "5",
  391 + .gpio = 11,
  392 + .active_low = 1,
  393 + },
  394 +};
  395 +
  396 +static struct gpio_led_platform_data ar7_led_data;
  397 +
  398 +static struct platform_device ar7_gpio_leds = {
  399 + .name = "leds-gpio",
  400 + .id = -1,
  401 + .dev = {
  402 + .platform_data = &ar7_led_data,
  403 + }
  404 +};
  405 +
  406 +static struct platform_device ar7_udc = {
  407 + .id = -1,
  408 + .name = "ar7_udc",
  409 + .resource = usb_res,
  410 + .num_resources = ARRAY_SIZE(usb_res),
  411 +};
  412 +
  413 +static inline unsigned char char2hex(char h)
  414 +{
  415 + switch (h) {
  416 + case '0': case '1': case '2': case '3': case '4':
  417 + case '5': case '6': case '7': case '8': case '9':
  418 + return h - '0';
  419 + case 'A': case 'B': case 'C': case 'D': case 'E': case 'F':
  420 + return h - 'A' + 10;
  421 + case 'a': case 'b': case 'c': case 'd': case 'e': case 'f':
  422 + return h - 'a' + 10;
  423 + default:
  424 + return 0;
  425 + }
  426 +}
  427 +
  428 +static void cpmac_get_mac(int instance, unsigned char *dev_addr)
  429 +{
  430 + int i;
  431 + char name[5], default_mac[ETH_ALEN], *mac;
  432 +
  433 + mac = NULL;
  434 + sprintf(name, "mac%c", 'a' + instance);
  435 + mac = prom_getenv(name);
  436 + if (!mac) {
  437 + sprintf(name, "mac%c", 'a');
  438 + mac = prom_getenv(name);
  439 + }
  440 + if (!mac) {
  441 + random_ether_addr(default_mac);
  442 + mac = default_mac;
  443 + }
  444 + for (i = 0; i < 6; i++)
  445 + dev_addr[i] = (char2hex(mac[i * 3]) << 4) +
  446 + char2hex(mac[i * 3 + 1]);
  447 +}
  448 +
  449 +static void __init detect_leds(void)
  450 +{
  451 + char *prid, *usb_prod;
  452 +
  453 + /* Default LEDs */
  454 + ar7_led_data.num_leds = ARRAY_SIZE(default_leds);
  455 + ar7_led_data.leds = default_leds;
  456 +
  457 + /* FIXME: the whole thing is unreliable */
  458 + prid = prom_getenv("ProductID");
  459 + usb_prod = prom_getenv("usb_prod");
  460 +
  461 + /* If we can't get the product id from PROM, use the default LEDs */
  462 + if (!prid)
  463 + return;
  464 +
  465 + if (strstr(prid, "Fritz_Box_FON")) {
  466 + ar7_led_data.num_leds = ARRAY_SIZE(fb_fon_leds);
  467 + ar7_led_data.leds = fb_fon_leds;
  468 + } else if (strstr(prid, "Fritz_Box_")) {
  469 + ar7_led_data.num_leds = ARRAY_SIZE(fb_sl_leds);
  470 + ar7_led_data.leds = fb_sl_leds;
  471 + } else if ((!strcmp(prid, "AR7RD") || !strcmp(prid, "AR7DB"))
  472 + && usb_prod != NULL && strstr(usb_prod, "DSL-502T")) {
  473 + ar7_led_data.num_leds = ARRAY_SIZE(dsl502t_leds);
  474 + ar7_led_data.leds = dsl502t_leds;
  475 + } else if (strstr(prid, "DG834")) {
  476 + ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds);
  477 + ar7_led_data.leds = dg834g_leds;
  478 + }
  479 +}
  480 +
  481 +static int __init ar7_register_devices(void)
  482 +{
  483 + int res;
  484 + static struct uart_port uart_port[2];
  485 +
  486 + memset(uart_port, 0, sizeof(struct uart_port) * 2);
  487 +
  488 + uart_port[0].type = PORT_16550A;
  489 + uart_port[0].line = 0;
  490 + uart_port[0].irq = AR7_IRQ_UART0;
  491 + uart_port[0].uartclk = ar7_bus_freq() / 2;
  492 + uart_port[0].iotype = UPIO_MEM32;
  493 + uart_port[0].mapbase = AR7_REGS_UART0;
  494 + uart_port[0].membase = ioremap(uart_port[0].mapbase, 256);
  495 + uart_port[0].regshift = 2;
  496 + res = early_serial_setup(&uart_port[0]);
  497 + if (res)
  498 + return res;
  499 +
  500 +
  501 + /* Only TNETD73xx have a second serial port */
  502 + if (ar7_has_second_uart()) {
  503 + uart_port[1].type = PORT_16550A;
  504 + uart_port[1].line = 1;
  505 + uart_port[1].irq = AR7_IRQ_UART1;
  506 + uart_port[1].uartclk = ar7_bus_freq() / 2;
  507 + uart_port[1].iotype = UPIO_MEM32;
  508 + uart_port[1].mapbase = UR8_REGS_UART1;
  509 + uart_port[1].membase = ioremap(uart_port[1].mapbase, 256);
  510 + uart_port[1].regshift = 2;
  511 + res = early_serial_setup(&uart_port[1]);
  512 + if (res)
  513 + return res;
  514 + }
  515 +
  516 + res = platform_device_register(&physmap_flash);
  517 + if (res)
  518 + return res;
  519 +
  520 + ar7_device_disable(vlynq_low_data.reset_bit);
  521 + res = platform_device_register(&vlynq_low);
  522 + if (res)
  523 + return res;
  524 +
  525 + if (ar7_has_high_vlynq()) {
  526 + ar7_device_disable(vlynq_high_data.reset_bit);
  527 + res = platform_device_register(&vlynq_high);
  528 + if (res)
  529 + return res;
  530 + }
  531 +
  532 + if (ar7_has_high_cpmac()) {
  533 + cpmac_get_mac(1, cpmac_high_data.dev_addr);
  534 + res = platform_device_register(&cpmac_high);
  535 + if (res)
  536 + return res;
  537 + } else {
  538 + cpmac_low_data.phy_mask = 0xffffffff;
  539 + }
  540 +
  541 + cpmac_get_mac(0, cpmac_low_data.dev_addr);
  542 + res = platform_device_register(&cpmac_low);
  543 + if (res)
  544 + return res;
  545 +
  546 + detect_leds();
  547 + res = platform_device_register(&ar7_gpio_leds);
  548 + if (res)
  549 + return res;
  550 +
  551 + res = platform_device_register(&ar7_udc);
  552 +
  553 + return res;
  554 +}
  555 +arch_initcall(ar7_register_devices);
arch/mips/ar7/prom.c
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * Carsten Langgaard, carstenl@mips.com
  3 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
  4 + *
  5 + * This program is free software; you can distribute it and/or modify it
  6 + * under the terms of the GNU General Public License (Version 2) as
  7 + * published by the Free Software Foundation.
  8 + *
  9 + * This program is distributed in the hope it will be useful, but WITHOUT
  10 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12 + * for more details.
  13 + *
  14 + * You should have received a copy of the GNU General Public License along
  15 + * with this program; if not, write to the Free Software Foundation, Inc.,
  16 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17 + *
  18 + * Putting things on the screen/serial line using YAMONs facilities.
  19 + */
  20 +#include <linux/init.h>
  21 +#include <linux/kernel.h>
  22 +#include <linux/serial_reg.h>
  23 +#include <linux/spinlock.h>
  24 +#include <linux/module.h>
  25 +#include <linux/string.h>
  26 +#include <linux/io.h>
  27 +#include <asm/bootinfo.h>
  28 +
  29 +#include <asm/mach-ar7/ar7.h>
  30 +#include <asm/mach-ar7/prom.h>
  31 +
  32 +#define MAX_ENTRY 80
  33 +
  34 +struct env_var {
  35 + char *name;
  36 + char *value;
  37 +};
  38 +
  39 +static struct env_var adam2_env[MAX_ENTRY];
  40 +
  41 +char *prom_getenv(const char *name)
  42 +{
  43 + int i;
  44 + for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++)
  45 + if (!strcmp(name, adam2_env[i].name))
  46 + return adam2_env[i].value;
  47 +
  48 + return NULL;
  49 +}
  50 +EXPORT_SYMBOL(prom_getenv);
  51 +
  52 +char * __init prom_getcmdline(void)
  53 +{
  54 + return &(arcs_cmdline[0]);
  55 +}
  56 +
  57 +static void __init ar7_init_cmdline(int argc, char *argv[])
  58 +{
  59 + char *cp;
  60 + int actr;
  61 +
  62 + actr = 1; /* Always ignore argv[0] */
  63 +
  64 + cp = &(arcs_cmdline[0]);
  65 + while (actr < argc) {
  66 + strcpy(cp, argv[actr]);
  67 + cp += strlen(argv[actr]);
  68 + *cp++ = ' ';
  69 + actr++;
  70 + }
  71 + if (cp != &(arcs_cmdline[0])) {
  72 + /* get rid of trailing space */
  73 + --cp;
  74 + *cp = '\0';
  75 + }
  76 +}
  77 +
  78 +struct psbl_rec {
  79 + u32 psbl_size;
  80 + u32 env_base;
  81 + u32 env_size;
  82 + u32 ffs_base;
  83 + u32 ffs_size;
  84 +};
  85 +
  86 +static __initdata char psp_env_version[] = "TIENV0.8";
  87 +
  88 +struct psp_env_chunk {
  89 + u8 num;
  90 + u8 ctrl;
  91 + u16 csum;
  92 + u8 len;
  93 + char data[11];
  94 +} __attribute__ ((packed));
  95 +
  96 +struct psp_var_map_entry {
  97 + u8 num;
  98 + char *value;
  99 +};
  100 +
  101 +static struct psp_var_map_entry psp_var_map[] = {
  102 + { 1, "cpufrequency" },
  103 + { 2, "memsize" },
  104 + { 3, "flashsize" },
  105 + { 4, "modetty0" },
  106 + { 5, "modetty1" },
  107 + { 8, "maca" },
  108 + { 9, "macb" },
  109 + { 28, "sysfrequency" },
  110 + { 38, "mipsfrequency" },
  111 +};
  112 +
  113 +/*
  114 +
  115 +Well-known variable (num is looked up in table above for matching variable name)
  116 +Example: cpufrequency=211968000
  117 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
  118 +| 01 |CTRL|CHECKSUM | 01 | _2 | _1 | _1 | _9 | _6 | _8 | _0 | _0 | _0 | \0 | FF
  119 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
  120 +
  121 +Name=Value pair in a single chunk
  122 +Example: NAME=VALUE
  123 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
  124 +| 00 |CTRL|CHECKSUM | 01 | _N | _A | _M | _E | _0 | _V | _A | _L | _U | _E | \0
  125 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
  126 +
  127 +Name=Value pair in 2 chunks (len is the number of chunks)
  128 +Example: bootloaderVersion=1.3.7.15
  129 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
  130 +| 00 |CTRL|CHECKSUM | 02 | _b | _o | _o | _t | _l | _o | _a | _d | _e | _r | _V
  131 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
  132 +| _e | _r | _s | _i | _o | _n | \0 | _1 | _. | _3 | _. | _7 | _. | _1 | _5 | \0
  133 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+---
  134 +
  135 +Data is padded with 0xFF
  136 +
  137 +*/
  138 +
  139 +#define PSP_ENV_SIZE 4096
  140 +
  141 +static char psp_env_data[PSP_ENV_SIZE] = { 0, };
  142 +
  143 +static char * __init lookup_psp_var_map(u8 num)
  144 +{
  145 + int i;
  146 +
  147 + for (i = 0; i < sizeof(psp_var_map); i++)
  148 + if (psp_var_map[i].num == num)
  149 + return psp_var_map[i].value;
  150 +
  151 + return NULL;
  152 +}
  153 +
  154 +static void __init add_adam2_var(char *name, char *value)
  155 +{
  156 + int i;
  157 + for (i = 0; i < MAX_ENTRY; i++) {
  158 + if (!adam2_env[i].name) {
  159 + adam2_env[i].name = name;
  160 + adam2_env[i].value = value;
  161 + return;
  162 + } else if (!strcmp(adam2_env[i].name, name)) {
  163 + adam2_env[i].value = value;
  164 + return;
  165 + }
  166 + }
  167 +}
  168 +
  169 +static int __init parse_psp_env(void *psp_env_base)
  170 +{
  171 + int i, n;
  172 + char *name, *value;
  173 + struct psp_env_chunk *chunks = (struct psp_env_chunk *)psp_env_data;
  174 +
  175 + memcpy_fromio(chunks, psp_env_base, PSP_ENV_SIZE);
  176 +
  177 + i = 1;
  178 + n = PSP_ENV_SIZE / sizeof(struct psp_env_chunk);
  179 + while (i < n) {
  180 + if ((chunks[i].num == 0xff) || ((i + chunks[i].len) > n))
  181 + break;
  182 + value = chunks[i].data;
  183 + if (chunks[i].num) {
  184 + name = lookup_psp_var_map(chunks[i].num);
  185 + } else {
  186 + name = value;
  187 + value += strlen(name) + 1;
  188 + }
  189 + if (name)
  190 + add_adam2_var(name, value);
  191 + i += chunks[i].len;
  192 + }
  193 + return 0;
  194 +}
  195 +
  196 +static void __init ar7_init_env(struct env_var *env)
  197 +{
  198 + int i;
  199 + struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x14000300));
  200 + void *psp_env = (void *)KSEG1ADDR(psbl->env_base);
  201 +
  202 + if (strcmp(psp_env, psp_env_version) == 0) {
  203 + parse_psp_env(psp_env);
  204 + } else {
  205 + for (i = 0; i < MAX_ENTRY; i++, env++)
  206 + if (env->name)
  207 + add_adam2_var(env->name, env->value);
  208 + }
  209 +}
  210 +
  211 +static void __init console_config(void)
  212 +{
  213 +#ifdef CONFIG_SERIAL_8250_CONSOLE
  214 + char console_string[40];
  215 + int baud = 0;
  216 + char parity = '\0', bits = '\0', flow = '\0';
  217 + char *s, *p;
  218 +
  219 + if (strstr(prom_getcmdline(), "console="))
  220 + return;
  221 +
  222 +#ifdef CONFIG_KGDB
  223 + if (!strstr(prom_getcmdline(), "nokgdb")) {
  224 + strcat(prom_getcmdline(), " console=kgdb");
  225 + kgdb_enabled = 1;
  226 + return;
  227 + }
  228 +#endif
  229 +
  230 + s = prom_getenv("modetty0");
  231 + if (s) {
  232 + baud = simple_strtoul(s, &p, 10);
  233 + s = p;
  234 + if (*s == ',')
  235 + s++;
  236 + if (*s)
  237 + parity = *s++;
  238 + if (*s == ',')
  239 + s++;
  240 + if (*s)
  241 + bits = *s++;
  242 + if (*s == ',')
  243 + s++;
  244 + if (*s == 'h')
  245 + flow = 'r';
  246 + }
  247 +
  248 + if (baud == 0)
  249 + baud = 38400;
  250 + if (parity != 'n' && parity != 'o' && parity != 'e')
  251 + parity = 'n';
  252 + if (bits != '7' && bits != '8')
  253 + bits = '8';
  254 +
  255 + if (flow == 'r')
  256 + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud,
  257 + parity, bits, flow);
  258 + else
  259 + sprintf(console_string, " console=ttyS0,%d%c%c", baud, parity,
  260 + bits);
  261 + strcat(prom_getcmdline(), console_string);
  262 +#endif
  263 +}
  264 +
  265 +void __init prom_init(void)
  266 +{
  267 + ar7_init_cmdline(fw_arg0, (char **)fw_arg1);
  268 + ar7_init_env((struct env_var *)fw_arg2);
  269 + console_config();
  270 +}
  271 +
  272 +#define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4)))
  273 +static inline unsigned int serial_in(int offset)
  274 +{
  275 + return readl((void *)PORT(offset));
  276 +}
  277 +
  278 +static inline void serial_out(int offset, int value)
  279 +{
  280 + writel(value, (void *)PORT(offset));
  281 +}
  282 +
  283 +char prom_getchar(void)
  284 +{
  285 + while (!(serial_in(UART_LSR) & UART_LSR_DR))
  286 + ;
  287 + return serial_in(UART_RX);
  288 +}
  289 +
  290 +int prom_putchar(char c)
  291 +{
  292 + while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0)
  293 + ;
  294 + serial_out(UART_TX, c);
  295 + return 1;
  296 +}
arch/mips/ar7/setup.c
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * Carsten Langgaard, carstenl@mips.com
  3 + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  4 + *
  5 + * This program is free software; you can distribute it and/or modify it
  6 + * under the terms of the GNU General Public License (Version 2) as
  7 + * published by the Free Software Foundation.
  8 + *
  9 + * This program is distributed in the hope it will be useful, but WITHOUT
  10 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12 + * for more details.
  13 + *
  14 + * You should have received a copy of the GNU General Public License along
  15 + * with this program; if not, write to the Free Software Foundation, Inc.,
  16 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17 + */
  18 +#include <linux/version.h>
  19 +#include <linux/init.h>
  20 +#include <linux/ioport.h>
  21 +#include <linux/pm.h>
  22 +#include <linux/time.h>
  23 +
  24 +#include <asm/reboot.h>
  25 +#include <asm/mach-ar7/ar7.h>
  26 +#include <asm/mach-ar7/prom.h>
  27 +
  28 +static void ar7_machine_restart(char *command)
  29 +{
  30 + u32 *softres_reg = ioremap(AR7_REGS_RESET +
  31 + AR7_RESET_SOFTWARE, 1);
  32 + writel(1, softres_reg);
  33 +}
  34 +
  35 +static void ar7_machine_halt(void)
  36 +{
  37 + while (1)
  38 + ;
  39 +}
  40 +
  41 +static void ar7_machine_power_off(void)
  42 +{
  43 + u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1);
  44 + u32 power_state = readl(power_reg) | (3 << 30);
  45 + writel(power_state, power_reg);
  46 + ar7_machine_halt();
  47 +}
  48 +
  49 +const char *get_system_type(void)
  50 +{
  51 + u16 chip_id = ar7_chip_id();
  52 + switch (chip_id) {
  53 + case AR7_CHIP_7300:
  54 + return "TI AR7 (TNETD7300)";
  55 + case AR7_CHIP_7100:
  56 + return "TI AR7 (TNETD7100)";
  57 + case AR7_CHIP_7200:
  58 + return "TI AR7 (TNETD7200)";
  59 + default:
  60 + return "TI AR7 (Unknown)";
  61 + }
  62 +}
  63 +
  64 +static int __init ar7_init_console(void)
  65 +{
  66 + return 0;
  67 +}
  68 +console_initcall(ar7_init_console);
  69 +
  70 +/*
  71 + * Initializes basic routines and structures pointers, memory size (as
  72 + * given by the bios and saves the command line.
  73 + */
  74 +
  75 +void __init plat_mem_setup(void)
  76 +{
  77 + unsigned long io_base;
  78 +
  79 + _machine_restart = ar7_machine_restart;
  80 + _machine_halt = ar7_machine_halt;
  81 + pm_power_off = ar7_machine_power_off;
  82 + panic_timeout = 3;
  83 +
  84 + io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000);
  85 + if (!io_base)
  86 + panic("Can't remap IO base!\n");
  87 + set_io_port_base(io_base);
  88 +
  89 + prom_meminit();
  90 +
  91 + printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n",
  92 + get_system_type(),
  93 + ar7_chip_id(), ar7_chip_rev());
  94 +}
arch/mips/ar7/time.c
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * Carsten Langgaard, carstenl@mips.com
  3 + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
  4 + *
  5 + * This program is free software; you can distribute it and/or modify it
  6 + * under the terms of the GNU General Public License (Version 2) as
  7 + * published by the Free Software Foundation.
  8 + *
  9 + * This program is distributed in the hope it will be useful, but WITHOUT
  10 + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  12 + * for more details.
  13 + *
  14 + * You should have received a copy of the GNU General Public License along
  15 + * with this program; if not, write to the Free Software Foundation, Inc.,
  16 + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  17 + *
  18 + * Setting up the clock on the MIPS boards.
  19 + */
  20 +
  21 +#include <linux/init.h>
  22 +#include <linux/time.h>
  23 +
  24 +#include <asm/time.h>
  25 +#include <asm/mach-ar7/ar7.h>
  26 +
  27 +void __init plat_time_init(void)
  28 +{
  29 + mips_hpt_frequency = ar7_cpu_freq() / 2;
  30 +}
arch/mips/configs/ar7_defconfig
Diff comments   View file @ 7ca5dc1
Changes suppressed. Click to show
  1 +#
  2 +# Automatically generated make config: don't edit
  3 +# Linux kernel version: 2.6.30
  4 +# Wed Jun 24 14:08:59 2009
  5 +#
  6 +CONFIG_MIPS=y
  7 +
  8 +#
  9 +# Machine selection
  10 +#
  11 +# CONFIG_MACH_ALCHEMY is not set
  12 +CONFIG_AR7=y
  13 +# CONFIG_BASLER_EXCITE is not set
  14 +# CONFIG_BCM47XX is not set
  15 +# CONFIG_MIPS_COBALT is not set
  16 +# CONFIG_MACH_DECSTATION is not set
  17 +# CONFIG_MACH_JAZZ is not set
  18 +# CONFIG_LASAT is not set
  19 +# CONFIG_LEMOTE_FULONG is not set
  20 +# CONFIG_MIPS_MALTA is not set
  21 +# CONFIG_MIPS_SIM is not set
  22 +# CONFIG_NEC_MARKEINS is not set
  23 +# CONFIG_MACH_VR41XX is not set
  24 +# CONFIG_NXP_STB220 is not set
  25 +# CONFIG_NXP_STB225 is not set
  26 +# CONFIG_PNX8550_JBS is not set
  27 +# CONFIG_PNX8550_STB810 is not set
  28 +# CONFIG_PMC_MSP is not set
  29 +# CONFIG_PMC_YOSEMITE is not set
  30 +# CONFIG_SGI_IP22 is not set
  31 +# CONFIG_SGI_IP27 is not set
  32 +# CONFIG_SGI_IP28 is not set
  33 +# CONFIG_SGI_IP32 is not set
  34 +# CONFIG_SIBYTE_CRHINE is not set
  35 +# CONFIG_SIBYTE_CARMEL is not set
  36 +# CONFIG_SIBYTE_CRHONE is not set
  37 +# CONFIG_SIBYTE_RHONE is not set
  38 +# CONFIG_SIBYTE_SWARM is not set
  39 +# CONFIG_SIBYTE_LITTLESUR is not set
  40 +# CONFIG_SIBYTE_SENTOSA is not set
  41 +# CONFIG_SIBYTE_BIGSUR is not set
  42 +# CONFIG_SNI_RM is not set
  43 +# CONFIG_MACH_TX39XX is not set
  44 +# CONFIG_MACH_TX49XX is not set
  45 +# CONFIG_MIKROTIK_RB532 is not set
  46 +# CONFIG_WR_PPMC is not set
  47 +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set
  48 +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set
  49 +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set
  50 +CONFIG_RWSEM_GENERIC_SPINLOCK=y
  51 +# CONFIG_ARCH_HAS_ILOG2_U32 is not set
  52 +# CONFIG_ARCH_HAS_ILOG2_U64 is not set
  53 +CONFIG_ARCH_SUPPORTS_OPROFILE=y
  54 +CONFIG_GENERIC_FIND_NEXT_BIT=y
  55 +CONFIG_GENERIC_HWEIGHT=y
  56 +CONFIG_GENERIC_CALIBRATE_DELAY=y
  57 +CONFIG_GENERIC_CLOCKEVENTS=y
  58 +CONFIG_GENERIC_TIME=y
  59 +CONFIG_GENERIC_CMOS_UPDATE=y
  60 +CONFIG_SCHED_OMIT_FRAME_POINTER=y
  61 +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y
  62 +CONFIG_CEVT_R4K_LIB=y
  63 +CONFIG_CEVT_R4K=y
  64 +CONFIG_CSRC_R4K_LIB=y
  65 +CONFIG_CSRC_R4K=y
  66 +CONFIG_DMA_NONCOHERENT=y
  67 +CONFIG_DMA_NEED_PCI_MAP_STATE=y
  68 +CONFIG_EARLY_PRINTK=y
  69 +CONFIG_SYS_HAS_EARLY_PRINTK=y
  70 +# CONFIG_HOTPLUG_CPU is not set
  71 +# CONFIG_NO_IOPORT is not set
  72 +CONFIG_GENERIC_GPIO=y
  73 +# CONFIG_CPU_BIG_ENDIAN is not set
  74 +CONFIG_CPU_LITTLE_ENDIAN=y
  75 +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y
  76 +CONFIG_IRQ_CPU=y
  77 +CONFIG_NO_EXCEPT_FILL=y
  78 +CONFIG_SWAP_IO_SPACE=y
  79 +CONFIG_BOOT_ELF32=y
  80 +CONFIG_MIPS_L1_CACHE_SHIFT=5
  81 +
  82 +#
  83 +# CPU selection
  84 +#
  85 +# CONFIG_CPU_LOONGSON2 is not set
  86 +CONFIG_CPU_MIPS32_R1=y
  87 +# CONFIG_CPU_MIPS32_R2 is not set
  88 +# CONFIG_CPU_MIPS64_R1 is not set
  89 +# CONFIG_CPU_MIPS64_R2 is not set
  90 +# CONFIG_CPU_R3000 is not set
  91 +# CONFIG_CPU_TX39XX is not set
  92 +# CONFIG_CPU_VR41XX is not set
  93 +# CONFIG_CPU_R4300 is not set
  94 +# CONFIG_CPU_R4X00 is not set
  95 +# CONFIG_CPU_TX49XX is not set
  96 +# CONFIG_CPU_R5000 is not set
  97 +# CONFIG_CPU_R5432 is not set
  98 +# CONFIG_CPU_R5500 is not set
  99 +# CONFIG_CPU_R6000 is not set
  100 +# CONFIG_CPU_NEVADA is not set
  101 +# CONFIG_CPU_R8000 is not set
  102 +# CONFIG_CPU_R10000 is not set
  103 +# CONFIG_CPU_RM7000 is not set
  104 +# CONFIG_CPU_RM9000 is not set
  105 +# CONFIG_CPU_SB1 is not set
  106 +# CONFIG_CPU_CAVIUM_OCTEON is not set
  107 +CONFIG_SYS_HAS_CPU_MIPS32_R1=y
  108 +CONFIG_CPU_MIPS32=y
  109 +CONFIG_CPU_MIPSR1=y
  110 +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
  111 +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
  112 +CONFIG_HARDWARE_WATCHPOINTS=y
  113 +
  114 +#
  115 +# Kernel type
  116 +#
  117 +CONFIG_32BIT=y
  118 +# CONFIG_64BIT is not set
  119 +CONFIG_PAGE_SIZE_4KB=y
  120 +# CONFIG_PAGE_SIZE_8KB is not set
  121 +# CONFIG_PAGE_SIZE_16KB is not set
  122 +# CONFIG_PAGE_SIZE_32KB is not set
  123 +# CONFIG_PAGE_SIZE_64KB is not set
  124 +CONFIG_CPU_HAS_PREFETCH=y
  125 +CONFIG_MIPS_MT_DISABLED=y
  126 +# CONFIG_MIPS_MT_SMP is not set
  127 +# CONFIG_MIPS_MT_SMTC is not set
  128 +CONFIG_CPU_HAS_LLSC=y
  129 +CONFIG_CPU_HAS_SYNC=y
  130 +CONFIG_GENERIC_HARDIRQS=y
  131 +CONFIG_GENERIC_IRQ_PROBE=y
  132 +CONFIG_CPU_SUPPORTS_HIGHMEM=y
  133 +CONFIG_ARCH_FLATMEM_ENABLE=y
  134 +CONFIG_ARCH_POPULATES_NODE_MAP=y
  135 +CONFIG_SELECT_MEMORY_MODEL=y
  136 +CONFIG_FLATMEM_MANUAL=y
  137 +# CONFIG_DISCONTIGMEM_MANUAL is not set
  138 +# CONFIG_SPARSEMEM_MANUAL is not set
  139 +CONFIG_FLATMEM=y
  140 +CONFIG_FLAT_NODE_MEM_MAP=y
  141 +CONFIG_PAGEFLAGS_EXTENDED=y
  142 +CONFIG_SPLIT_PTLOCK_CPUS=4
  143 +# CONFIG_PHYS_ADDR_T_64BIT is not set
  144 +CONFIG_ZONE_DMA_FLAG=0
  145 +CONFIG_VIRT_TO_BUS=y
  146 +CONFIG_HAVE_MLOCK=y
  147 +CONFIG_HAVE_MLOCKED_PAGE_BIT=y
  148 +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
  149 +CONFIG_TICK_ONESHOT=y
  150 +# CONFIG_NO_HZ is not set
  151 +CONFIG_HIGH_RES_TIMERS=y
  152 +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
  153 +# CONFIG_HZ_48 is not set
  154 +CONFIG_HZ_100=y
  155 +# CONFIG_HZ_128 is not set
  156 +# CONFIG_HZ_250 is not set
  157 +# CONFIG_HZ_256 is not set
  158 +# CONFIG_HZ_1000 is not set
  159 +# CONFIG_HZ_1024 is not set
  160 +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
  161 +CONFIG_HZ=100
  162 +CONFIG_PREEMPT_NONE=y
  163 +# CONFIG_PREEMPT_VOLUNTARY is not set
  164 +# CONFIG_PREEMPT is not set
  165 +CONFIG_KEXEC=y
  166 +# CONFIG_SECCOMP is not set
  167 +CONFIG_LOCKDEP_SUPPORT=y
  168 +CONFIG_STACKTRACE_SUPPORT=y
  169 +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
  170 +
  171 +#
  172 +# General setup
  173 +#
  174 +CONFIG_EXPERIMENTAL=y
  175 +CONFIG_BROKEN_ON_SMP=y
  176 +CONFIG_INIT_ENV_ARG_LIMIT=32
  177 +CONFIG_LOCALVERSION=""
  178 +# CONFIG_LOCALVERSION_AUTO is not set
  179 +CONFIG_SWAP=y
  180 +CONFIG_SYSVIPC=y
  181 +CONFIG_SYSVIPC_SYSCTL=y
  182 +# CONFIG_POSIX_MQUEUE is not set
  183 +CONFIG_BSD_PROCESS_ACCT=y
  184 +# CONFIG_BSD_PROCESS_ACCT_V3 is not set
  185 +# CONFIG_TASKSTATS is not set
  186 +# CONFIG_AUDIT is not set
  187 +
  188 +#
  189 +# RCU Subsystem
  190 +#
  191 +CONFIG_CLASSIC_RCU=y
  192 +# CONFIG_TREE_RCU is not set
  193 +# CONFIG_PREEMPT_RCU is not set
  194 +# CONFIG_TREE_RCU_TRACE is not set
  195 +# CONFIG_PREEMPT_RCU_TRACE is not set
  196 +# CONFIG_IKCONFIG is not set
  197 +CONFIG_LOG_BUF_SHIFT=14
  198 +# CONFIG_GROUP_SCHED is not set
  199 +# CONFIG_CGROUPS is not set
  200 +CONFIG_SYSFS_DEPRECATED=y
  201 +CONFIG_SYSFS_DEPRECATED_V2=y
  202 +CONFIG_RELAY=y
  203 +# CONFIG_NAMESPACES is not set
  204 +CONFIG_BLK_DEV_INITRD=y
  205 +CONFIG_INITRAMFS_SOURCE=""
  206 +CONFIG_RD_GZIP=y
  207 +# CONFIG_RD_BZIP2 is not set
  208 +CONFIG_RD_LZMA=y
  209 +CONFIG_CC_OPTIMIZE_FOR_SIZE=y
  210 +CONFIG_SYSCTL=y
  211 +CONFIG_ANON_INODES=y
  212 +CONFIG_EMBEDDED=y
  213 +CONFIG_SYSCTL_SYSCALL=y
  214 +# CONFIG_KALLSYMS is not set
  215 +CONFIG_HOTPLUG=y
  216 +CONFIG_PRINTK=y
  217 +CONFIG_BUG=y
  218 +# CONFIG_ELF_CORE is not set
  219 +# CONFIG_PCSPKR_PLATFORM is not set
  220 +CONFIG_BASE_FULL=y
  221 +CONFIG_FUTEX=y
  222 +CONFIG_EPOLL=y
  223 +CONFIG_SIGNALFD=y
  224 +CONFIG_TIMERFD=y
  225 +CONFIG_EVENTFD=y
  226 +CONFIG_SHMEM=y
  227 +CONFIG_AIO=y
  228 +
  229 +#
  230 +# Performance Counters
  231 +#
  232 +# CONFIG_VM_EVENT_COUNTERS is not set
  233 +CONFIG_STRIP_ASM_SYMS=y
  234 +# CONFIG_COMPAT_BRK is not set
  235 +CONFIG_SLAB=y
  236 +# CONFIG_SLUB is not set
  237 +# CONFIG_SLOB is not set
  238 +# CONFIG_PROFILING is not set
  239 +# CONFIG_MARKERS is not set
  240 +CONFIG_HAVE_OPROFILE=y
  241 +# CONFIG_SLOW_WORK is not set
  242 +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
  243 +CONFIG_SLABINFO=y
  244 +CONFIG_RT_MUTEXES=y
  245 +CONFIG_BASE_SMALL=0
  246 +CONFIG_MODULES=y
  247 +# CONFIG_MODULE_FORCE_LOAD is not set
  248 +CONFIG_MODULE_UNLOAD=y
  249 +# CONFIG_MODULE_FORCE_UNLOAD is not set
  250 +# CONFIG_MODVERSIONS is not set
  251 +# CONFIG_MODULE_SRCVERSION_ALL is not set
  252 +CONFIG_BLOCK=y
  253 +# CONFIG_LBD is not set
  254 +# CONFIG_BLK_DEV_BSG is not set
  255 +# CONFIG_BLK_DEV_INTEGRITY is not set
  256 +
  257 +#
  258 +# IO Schedulers
  259 +#
  260 +CONFIG_IOSCHED_NOOP=y
  261 +# CONFIG_IOSCHED_AS is not set
  262 +CONFIG_IOSCHED_DEADLINE=y
  263 +# CONFIG_IOSCHED_CFQ is not set
  264 +# CONFIG_DEFAULT_AS is not set
  265 +CONFIG_DEFAULT_DEADLINE=y
  266 +# CONFIG_DEFAULT_CFQ is not set
  267 +# CONFIG_DEFAULT_NOOP is not set
  268 +CONFIG_DEFAULT_IOSCHED="deadline"
  269 +CONFIG_PROBE_INITRD_HEADER=y
  270 +# CONFIG_FREEZER is not set
  271 +
  272 +#
  273 +# Bus options (PCI, PCMCIA, EISA, ISA, TC)
  274 +#
  275 +# CONFIG_ARCH_SUPPORTS_MSI is not set
  276 +CONFIG_MMU=y
  277 +# CONFIG_PCCARD is not set
  278 +
  279 +#
  280 +# Executable file formats
  281 +#
  282 +CONFIG_BINFMT_ELF=y
  283 +# CONFIG_HAVE_AOUT is not set
  284 +# CONFIG_BINFMT_MISC is not set
  285 +CONFIG_TRAD_SIGNALS=y
  286 +
  287 +#
  288 +# Power management options
  289 +#
  290 +CONFIG_ARCH_HIBERNATION_POSSIBLE=y
  291 +CONFIG_ARCH_SUSPEND_POSSIBLE=y
  292 +# CONFIG_PM is not set
  293 +CONFIG_NET=y
  294 +
  295 +#
  296 +# Networking options
  297 +#
  298 +CONFIG_PACKET=y
  299 +CONFIG_PACKET_MMAP=y
  300 +CONFIG_UNIX=y
  301 +# CONFIG_NET_KEY is not set
  302 +CONFIG_INET=y
  303 +CONFIG_IP_MULTICAST=y
  304 +CONFIG_IP_ADVANCED_ROUTER=y
  305 +CONFIG_ASK_IP_FIB_HASH=y
  306 +# CONFIG_IP_FIB_TRIE is not set
  307 +CONFIG_IP_FIB_HASH=y
  308 +CONFIG_IP_MULTIPLE_TABLES=y
  309 +CONFIG_IP_ROUTE_MULTIPATH=y
  310 +CONFIG_IP_ROUTE_VERBOSE=y
  311 +# CONFIG_IP_PNP is not set
  312 +# CONFIG_NET_IPIP is not set
  313 +# CONFIG_NET_IPGRE is not set
  314 +CONFIG_IP_MROUTE=y
  315 +# CONFIG_IP_PIMSM_V1 is not set
  316 +# CONFIG_IP_PIMSM_V2 is not set
  317 +CONFIG_ARPD=y
  318 +CONFIG_SYN_COOKIES=y
  319 +# CONFIG_INET_AH is not set
  320 +# CONFIG_INET_ESP is not set
  321 +# CONFIG_INET_IPCOMP is not set
  322 +# CONFIG_INET_XFRM_TUNNEL is not set
  323 +# CONFIG_INET_TUNNEL is not set
  324 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
  325 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
  326 +# CONFIG_INET_XFRM_MODE_BEET is not set
  327 +# CONFIG_INET_LRO is not set
  328 +# CONFIG_INET_DIAG is not set
  329 +CONFIG_TCP_CONG_ADVANCED=y
  330 +# CONFIG_TCP_CONG_BIC is not set
  331 +# CONFIG_TCP_CONG_CUBIC is not set
  332 +CONFIG_TCP_CONG_WESTWOOD=y
  333 +# CONFIG_TCP_CONG_HTCP is not set
  334 +# CONFIG_TCP_CONG_HSTCP is not set
  335 +# CONFIG_TCP_CONG_HYBLA is not set
  336 +# CONFIG_TCP_CONG_VEGAS is not set
  337 +# CONFIG_TCP_CONG_SCALABLE is not set
  338 +# CONFIG_TCP_CONG_LP is not set
  339 +# CONFIG_TCP_CONG_VENO is not set
  340 +# CONFIG_TCP_CONG_YEAH is not set
  341 +# CONFIG_TCP_CONG_ILLINOIS is not set
  342 +# CONFIG_DEFAULT_BIC is not set
  343 +# CONFIG_DEFAULT_CUBIC is not set
  344 +# CONFIG_DEFAULT_HTCP is not set
  345 +# CONFIG_DEFAULT_VEGAS is not set
  346 +CONFIG_DEFAULT_WESTWOOD=y
  347 +# CONFIG_DEFAULT_RENO is not set
  348 +CONFIG_DEFAULT_TCP_CONG="westwood"
  349 +# CONFIG_TCP_MD5SIG is not set
  350 +# CONFIG_IPV6 is not set
  351 +# CONFIG_NETWORK_SECMARK is not set
  352 +CONFIG_NETFILTER=y
  353 +# CONFIG_NETFILTER_DEBUG is not set
  354 +CONFIG_NETFILTER_ADVANCED=y
  355 +# CONFIG_BRIDGE_NETFILTER is not set
  356 +
  357 +#
  358 +# Core Netfilter Configuration
  359 +#
  360 +# CONFIG_NETFILTER_NETLINK_QUEUE is not set
  361 +# CONFIG_NETFILTER_NETLINK_LOG is not set
  362 +CONFIG_NF_CONNTRACK=m
  363 +# CONFIG_NF_CT_ACCT is not set
  364 +CONFIG_NF_CONNTRACK_MARK=y
  365 +# CONFIG_NF_CONNTRACK_EVENTS is not set
  366 +# CONFIG_NF_CT_PROTO_DCCP is not set
  367 +# CONFIG_NF_CT_PROTO_SCTP is not set
  368 +# CONFIG_NF_CT_PROTO_UDPLITE is not set
  369 +# CONFIG_NF_CONNTRACK_AMANDA is not set
  370 +CONFIG_NF_CONNTRACK_FTP=m
  371 +# CONFIG_NF_CONNTRACK_H323 is not set
  372 +CONFIG_NF_CONNTRACK_IRC=m
  373 +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
  374 +# CONFIG_NF_CONNTRACK_PPTP is not set
  375 +# CONFIG_NF_CONNTRACK_SANE is not set
  376 +# CONFIG_NF_CONNTRACK_SIP is not set
  377 +CONFIG_NF_CONNTRACK_TFTP=m
  378 +# CONFIG_NF_CT_NETLINK is not set
  379 +# CONFIG_NETFILTER_TPROXY is not set
  380 +CONFIG_NETFILTER_XTABLES=m
  381 +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
  382 +# CONFIG_NETFILTER_XT_TARGET_CONNMARK is not set
  383 +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set
  384 +# CONFIG_NETFILTER_XT_TARGET_HL is not set
  385 +# CONFIG_NETFILTER_XT_TARGET_LED is not set
  386 +# CONFIG_NETFILTER_XT_TARGET_MARK is not set
  387 +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set
  388 +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
  389 +CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
  390 +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set
  391 +# CONFIG_NETFILTER_XT_TARGET_TRACE is not set
  392 +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
  393 +# CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP is not set
  394 +# CONFIG_NETFILTER_XT_MATCH_CLUSTER is not set
  395 +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
  396 +# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
  397 +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set
  398 +# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
  399 +# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
  400 +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
  401 +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
  402 +# CONFIG_NETFILTER_XT_MATCH_ESP is not set
  403 +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
  404 +# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
  405 +# CONFIG_NETFILTER_XT_MATCH_HL is not set
  406 +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set
  407 +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
  408 +CONFIG_NETFILTER_XT_MATCH_LIMIT=m
  409 +CONFIG_NETFILTER_XT_MATCH_MAC=m
  410 +# CONFIG_NETFILTER_XT_MATCH_MARK is not set
  411 +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
  412 +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set
  413 +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
  414 +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
  415 +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set
  416 +# CONFIG_NETFILTER_XT_MATCH_REALM is not set
  417 +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set
  418 +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
  419 +CONFIG_NETFILTER_XT_MATCH_STATE=m
  420 +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
  421 +# CONFIG_NETFILTER_XT_MATCH_STRING is not set
  422 +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
  423 +# CONFIG_NETFILTER_XT_MATCH_TIME is not set
  424 +# CONFIG_NETFILTER_XT_MATCH_U32 is not set
  425 +# CONFIG_IP_VS is not set
  426 +
  427 +#
  428 +# IP: Netfilter Configuration
  429 +#
  430 +CONFIG_NF_DEFRAG_IPV4=m
  431 +CONFIG_NF_CONNTRACK_IPV4=m
  432 +CONFIG_NF_CONNTRACK_PROC_COMPAT=y
  433 +# CONFIG_IP_NF_QUEUE is not set
  434 +CONFIG_IP_NF_IPTABLES=m
  435 +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
  436 +# CONFIG_IP_NF_MATCH_AH is not set
  437 +# CONFIG_IP_NF_MATCH_ECN is not set
  438 +# CONFIG_IP_NF_MATCH_TTL is not set
  439 +CONFIG_IP_NF_FILTER=m
  440 +CONFIG_IP_NF_TARGET_REJECT=m
  441 +CONFIG_IP_NF_TARGET_LOG=m
  442 +# CONFIG_IP_NF_TARGET_ULOG is not set
  443 +CONFIG_NF_NAT=m
  444 +CONFIG_NF_NAT_NEEDED=y
  445 +CONFIG_IP_NF_TARGET_MASQUERADE=m
  446 +# CONFIG_IP_NF_TARGET_NETMAP is not set
  447 +# CONFIG_IP_NF_TARGET_REDIRECT is not set
  448 +# CONFIG_NF_NAT_SNMP_BASIC is not set
  449 +CONFIG_NF_NAT_FTP=m
  450 +CONFIG_NF_NAT_IRC=m
  451 +CONFIG_NF_NAT_TFTP=m
  452 +# CONFIG_NF_NAT_AMANDA is not set
  453 +# CONFIG_NF_NAT_PPTP is not set
  454 +# CONFIG_NF_NAT_H323 is not set
  455 +# CONFIG_NF_NAT_SIP is not set
  456 +CONFIG_IP_NF_MANGLE=m
  457 +# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
  458 +# CONFIG_IP_NF_TARGET_ECN is not set
  459 +# CONFIG_IP_NF_TARGET_TTL is not set
  460 +CONFIG_IP_NF_RAW=m
  461 +# CONFIG_IP_NF_ARPTABLES is not set
  462 +# CONFIG_IP_DCCP is not set
  463 +# CONFIG_IP_SCTP is not set
  464 +# CONFIG_TIPC is not set
  465 +CONFIG_ATM=m
  466 +# CONFIG_ATM_CLIP is not set
  467 +# CONFIG_ATM_LANE is not set
  468 +CONFIG_ATM_BR2684=m
  469 +CONFIG_ATM_BR2684_IPFILTER=y
  470 +CONFIG_STP=y
  471 +CONFIG_BRIDGE=y
  472 +# CONFIG_NET_DSA is not set
  473 +CONFIG_VLAN_8021Q=y
  474 +# CONFIG_VLAN_8021Q_GVRP is not set
  475 +# CONFIG_DECNET is not set
  476 +CONFIG_LLC=y
  477 +# CONFIG_LLC2 is not set
  478 +# CONFIG_IPX is not set
  479 +# CONFIG_ATALK is not set
  480 +# CONFIG_X25 is not set
  481 +# CONFIG_LAPB is not set
  482 +# CONFIG_ECONET is not set
  483 +# CONFIG_WAN_ROUTER is not set
  484 +# CONFIG_PHONET is not set
  485 +# CONFIG_IEEE802154 is not set
  486 +CONFIG_NET_SCHED=y
  487 +
  488 +#
  489 +# Queueing/Scheduling
  490 +#
  491 +# CONFIG_NET_SCH_CBQ is not set
  492 +# CONFIG_NET_SCH_HTB is not set
  493 +# CONFIG_NET_SCH_HFSC is not set
  494 +# CONFIG_NET_SCH_ATM is not set
  495 +# CONFIG_NET_SCH_PRIO is not set
  496 +# CONFIG_NET_SCH_MULTIQ is not set
  497 +# CONFIG_NET_SCH_RED is not set
  498 +# CONFIG_NET_SCH_SFQ is not set
  499 +# CONFIG_NET_SCH_TEQL is not set
  500 +# CONFIG_NET_SCH_TBF is not set
  501 +# CONFIG_NET_SCH_GRED is not set
  502 +# CONFIG_NET_SCH_DSMARK is not set
  503 +# CONFIG_NET_SCH_NETEM is not set
  504 +# CONFIG_NET_SCH_DRR is not set
  505 +# CONFIG_NET_SCH_INGRESS is not set
  506 +
  507 +#
  508 +# Classification
  509 +#
  510 +# CONFIG_NET_CLS_BASIC is not set
  511 +# CONFIG_NET_CLS_TCINDEX is not set
  512 +# CONFIG_NET_CLS_ROUTE4 is not set
  513 +# CONFIG_NET_CLS_FW is not set
  514 +# CONFIG_NET_CLS_U32 is not set
  515 +# CONFIG_NET_CLS_RSVP is not set
  516 +# CONFIG_NET_CLS_RSVP6 is not set
  517 +# CONFIG_NET_CLS_FLOW is not set
  518 +# CONFIG_NET_EMATCH is not set
  519 +CONFIG_NET_CLS_ACT=y
  520 +CONFIG_NET_ACT_POLICE=y
  521 +# CONFIG_NET_ACT_GACT is not set
  522 +# CONFIG_NET_ACT_MIRRED is not set
  523 +# CONFIG_NET_ACT_IPT is not set
  524 +# CONFIG_NET_ACT_NAT is not set
  525 +# CONFIG_NET_ACT_PEDIT is not set
  526 +# CONFIG_NET_ACT_SIMP is not set
  527 +# CONFIG_NET_ACT_SKBEDIT is not set
  528 +CONFIG_NET_SCH_FIFO=y
  529 +# CONFIG_DCB is not set
  530 +
  531 +#
  532 +# Network testing
  533 +#
  534 +# CONFIG_NET_PKTGEN is not set
  535 +CONFIG_HAMRADIO=y
  536 +
  537 +#
  538 +# Packet Radio protocols
  539 +#
  540 +# CONFIG_AX25 is not set
  541 +# CONFIG_CAN is not set
  542 +# CONFIG_IRDA is not set
  543 +# CONFIG_BT is not set
  544 +# CONFIG_AF_RXRPC is not set
  545 +CONFIG_FIB_RULES=y
  546 +CONFIG_WIRELESS=y
  547 +CONFIG_CFG80211=m
  548 +# CONFIG_CFG80211_REG_DEBUG is not set
  549 +# CONFIG_CFG80211_DEBUGFS is not set
  550 +# CONFIG_WIRELESS_OLD_REGULATORY is not set
  551 +CONFIG_WIRELESS_EXT=y
  552 +CONFIG_WIRELESS_EXT_SYSFS=y
  553 +# CONFIG_LIB80211 is not set
  554 +CONFIG_MAC80211=m
  555 +CONFIG_MAC80211_DEFAULT_PS=y
  556 +CONFIG_MAC80211_DEFAULT_PS_VALUE=1
  557 +
  558 +#
  559 +# Rate control algorithm selection
  560 +#
  561 +CONFIG_MAC80211_RC_PID=y
  562 +CONFIG_MAC80211_RC_MINSTREL=y
  563 +CONFIG_MAC80211_RC_DEFAULT_PID=y
  564 +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set
  565 +CONFIG_MAC80211_RC_DEFAULT="pid"
  566 +# CONFIG_MAC80211_MESH is not set
  567 +# CONFIG_MAC80211_LEDS is not set
  568 +# CONFIG_MAC80211_DEBUGFS is not set
  569 +# CONFIG_MAC80211_DEBUG_MENU is not set
  570 +# CONFIG_WIMAX is not set
  571 +# CONFIG_RFKILL is not set
  572 +# CONFIG_NET_9P is not set
  573 +
  574 +#
  575 +# Device Drivers
  576 +#
  577 +
  578 +#
  579 +# Generic Driver Options
  580 +#
  581 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
  582 +CONFIG_STANDALONE=y
  583 +CONFIG_PREVENT_FIRMWARE_BUILD=y
  584 +CONFIG_FW_LOADER=y
  585 +# CONFIG_FIRMWARE_IN_KERNEL is not set
  586 +CONFIG_EXTRA_FIRMWARE=""
  587 +# CONFIG_SYS_HYPERVISOR is not set
  588 +# CONFIG_CONNECTOR is not set
  589 +CONFIG_MTD=y
  590 +# CONFIG_MTD_DEBUG is not set
  591 +# CONFIG_MTD_CONCAT is not set
  592 +CONFIG_MTD_PARTITIONS=y
  593 +# CONFIG_MTD_TESTS is not set
  594 +# CONFIG_MTD_REDBOOT_PARTS is not set
  595 +# CONFIG_MTD_CMDLINE_PARTS is not set
  596 +# CONFIG_MTD_AR7_PARTS is not set
  597 +
  598 +#
  599 +# User Modules And Translation Layers
  600 +#
  601 +CONFIG_MTD_CHAR=y
  602 +CONFIG_MTD_BLKDEVS=y
  603 +CONFIG_MTD_BLOCK=y
  604 +# CONFIG_FTL is not set
  605 +# CONFIG_NFTL is not set
  606 +# CONFIG_INFTL is not set
  607 +# CONFIG_RFD_FTL is not set
  608 +# CONFIG_SSFDC is not set
  609 +# CONFIG_MTD_OOPS is not set
  610 +
  611 +#
  612 +# RAM/ROM/Flash chip drivers
  613 +#
  614 +CONFIG_MTD_CFI=y
  615 +# CONFIG_MTD_JEDECPROBE is not set
  616 +CONFIG_MTD_GEN_PROBE=y
  617 +# CONFIG_MTD_CFI_ADV_OPTIONS is not set
  618 +CONFIG_MTD_MAP_BANK_WIDTH_1=y
  619 +CONFIG_MTD_MAP_BANK_WIDTH_2=y
  620 +CONFIG_MTD_MAP_BANK_WIDTH_4=y
  621 +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
  622 +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
  623 +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
  624 +CONFIG_MTD_CFI_I1=y
  625 +CONFIG_MTD_CFI_I2=y
  626 +# CONFIG_MTD_CFI_I4 is not set
  627 +# CONFIG_MTD_CFI_I8 is not set
  628 +CONFIG_MTD_CFI_INTELEXT=y
  629 +CONFIG_MTD_CFI_AMDSTD=y
  630 +CONFIG_MTD_CFI_STAA=y
  631 +CONFIG_MTD_CFI_UTIL=y
  632 +# CONFIG_MTD_RAM is not set
  633 +# CONFIG_MTD_ROM is not set
  634 +# CONFIG_MTD_ABSENT is not set
  635 +
  636 +#
  637 +# Mapping drivers for chip access
  638 +#
  639 +CONFIG_MTD_COMPLEX_MAPPINGS=y
  640 +CONFIG_MTD_PHYSMAP=y
  641 +# CONFIG_MTD_PHYSMAP_COMPAT is not set
  642 +# CONFIG_MTD_PLATRAM is not set
  643 +
  644 +#
  645 +# Self-contained MTD device drivers
  646 +#
  647 +# CONFIG_MTD_SLRAM is not set
  648 +# CONFIG_MTD_PHRAM is not set
  649 +# CONFIG_MTD_MTDRAM is not set
  650 +# CONFIG_MTD_BLOCK2MTD is not set
  651 +
  652 +#
  653 +# Disk-On-Chip Device Drivers
  654 +#
  655 +# CONFIG_MTD_DOC2000 is not set
  656 +# CONFIG_MTD_DOC2001 is not set
  657 +# CONFIG_MTD_DOC2001PLUS is not set
  658 +# CONFIG_MTD_NAND is not set
  659 +# CONFIG_MTD_ONENAND is not set
  660 +
  661 +#
  662 +# LPDDR flash memory drivers
  663 +#
  664 +# CONFIG_MTD_LPDDR is not set
  665 +
  666 +#
  667 +# UBI - Unsorted block images
  668 +#
  669 +# CONFIG_MTD_UBI is not set
  670 +# CONFIG_PARPORT is not set
  671 +CONFIG_BLK_DEV=y
  672 +# CONFIG_BLK_DEV_COW_COMMON is not set
  673 +# CONFIG_BLK_DEV_LOOP is not set
  674 +# CONFIG_BLK_DEV_NBD is not set
  675 +# CONFIG_BLK_DEV_RAM is not set
  676 +# CONFIG_CDROM_PKTCDVD is not set
  677 +# CONFIG_ATA_OVER_ETH is not set
  678 +# CONFIG_BLK_DEV_HD is not set
  679 +CONFIG_MISC_DEVICES=y
  680 +# CONFIG_ENCLOSURE_SERVICES is not set
  681 +# CONFIG_C2PORT is not set
  682 +
  683 +#
  684 +# EEPROM support
  685 +#
  686 +# CONFIG_EEPROM_93CX6 is not set
  687 +CONFIG_HAVE_IDE=y
  688 +# CONFIG_IDE is not set
  689 +
  690 +#
  691 +# SCSI device support
  692 +#
  693 +# CONFIG_RAID_ATTRS is not set
  694 +# CONFIG_SCSI is not set
  695 +# CONFIG_SCSI_DMA is not set
  696 +# CONFIG_SCSI_NETLINK is not set
  697 +# CONFIG_ATA is not set
  698 +# CONFIG_MD is not set
  699 +CONFIG_NETDEVICES=y
  700 +# CONFIG_IFB is not set
  701 +# CONFIG_DUMMY is not set
  702 +# CONFIG_BONDING is not set
  703 +# CONFIG_MACVLAN is not set
  704 +# CONFIG_EQUALIZER is not set
  705 +# CONFIG_TUN is not set
  706 +# CONFIG_VETH is not set
  707 +CONFIG_PHYLIB=y
  708 +
  709 +#
  710 +# MII PHY device drivers
  711 +#
  712 +# CONFIG_MARVELL_PHY is not set
  713 +# CONFIG_DAVICOM_PHY is not set
  714 +# CONFIG_QSEMI_PHY is not set
  715 +# CONFIG_LXT_PHY is not set
  716 +# CONFIG_CICADA_PHY is not set
  717 +# CONFIG_VITESSE_PHY is not set
  718 +# CONFIG_SMSC_PHY is not set
  719 +# CONFIG_BROADCOM_PHY is not set
  720 +# CONFIG_ICPLUS_PHY is not set
  721 +# CONFIG_REALTEK_PHY is not set
  722 +# CONFIG_NATIONAL_PHY is not set
  723 +# CONFIG_STE10XP is not set
  724 +# CONFIG_LSI_ET1011C_PHY is not set
  725 +CONFIG_FIXED_PHY=y
  726 +# CONFIG_MDIO_BITBANG is not set
  727 +CONFIG_NET_ETHERNET=y
  728 +CONFIG_MII=y
  729 +# CONFIG_AX88796 is not set
  730 +# CONFIG_SMC91X is not set
  731 +# CONFIG_DM9000 is not set
  732 +# CONFIG_ETHOC is not set
  733 +# CONFIG_DNET is not set
  734 +# CONFIG_IBM_NEW_EMAC_ZMII is not set
  735 +# CONFIG_IBM_NEW_EMAC_RGMII is not set
  736 +# CONFIG_IBM_NEW_EMAC_TAH is not set
  737 +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
  738 +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
  739 +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
  740 +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
  741 +# CONFIG_B44 is not set
  742 +# CONFIG_KS8842 is not set
  743 +CONFIG_CPMAC=y
  744 +# CONFIG_NETDEV_1000 is not set
  745 +# CONFIG_NETDEV_10000 is not set
  746 +
  747 +#
  748 +# Wireless LAN
  749 +#
  750 +# CONFIG_WLAN_PRE80211 is not set
  751 +CONFIG_WLAN_80211=y
  752 +# CONFIG_LIBERTAS is not set
  753 +# CONFIG_LIBERTAS_THINFIRM is not set
  754 +# CONFIG_MAC80211_HWSIM is not set
  755 +# CONFIG_P54_COMMON is not set
  756 +# CONFIG_HOSTAP is not set
  757 +# CONFIG_B43 is not set
  758 +# CONFIG_B43LEGACY is not set
  759 +# CONFIG_RT2X00 is not set
  760 +
  761 +#
  762 +# Enable WiMAX (Networking options) to see the WiMAX drivers
  763 +#
  764 +# CONFIG_WAN is not set
  765 +CONFIG_ATM_DRIVERS=y
  766 +# CONFIG_ATM_DUMMY is not set
  767 +# CONFIG_ATM_TCP is not set
  768 +CONFIG_PPP=m
  769 +CONFIG_PPP_MULTILINK=y
  770 +CONFIG_PPP_FILTER=y
  771 +CONFIG_PPP_ASYNC=m
  772 +# CONFIG_PPP_SYNC_TTY is not set
  773 +# CONFIG_PPP_DEFLATE is not set
  774 +# CONFIG_PPP_BSDCOMP is not set
  775 +# CONFIG_PPP_MPPE is not set
  776 +CONFIG_PPPOE=m
  777 +CONFIG_PPPOATM=m
  778 +# CONFIG_PPPOL2TP is not set
  779 +# CONFIG_SLIP is not set
  780 +CONFIG_SLHC=m
  781 +# CONFIG_NETCONSOLE is not set
  782 +# CONFIG_NETPOLL is not set
  783 +# CONFIG_NET_POLL_CONTROLLER is not set
  784 +# CONFIG_ISDN is not set
  785 +# CONFIG_PHONE is not set
  786 +
  787 +#
  788 +# Input device support
  789 +#
  790 +# CONFIG_INPUT is not set
  791 +
  792 +#
  793 +# Hardware I/O ports
  794 +#
  795 +# CONFIG_SERIO is not set
  796 +# CONFIG_GAMEPORT is not set
  797 +
  798 +#
  799 +# Character devices
  800 +#
  801 +# CONFIG_VT is not set
  802 +# CONFIG_DEVKMEM is not set
  803 +# CONFIG_SERIAL_NONSTANDARD is not set
  804 +
  805 +#
  806 +# Serial drivers
  807 +#
  808 +CONFIG_SERIAL_8250=y
  809 +CONFIG_SERIAL_8250_CONSOLE=y
  810 +CONFIG_SERIAL_8250_NR_UARTS=2
  811 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2
  812 +# CONFIG_SERIAL_8250_EXTENDED is not set
  813 +
  814 +#
  815 +# Non-8250 serial port support
  816 +#
  817 +CONFIG_SERIAL_CORE=y
  818 +CONFIG_SERIAL_CORE_CONSOLE=y
  819 +CONFIG_UNIX98_PTYS=y
  820 +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
  821 +# CONFIG_LEGACY_PTYS is not set
  822 +# CONFIG_IPMI_HANDLER is not set
  823 +CONFIG_HW_RANDOM=y
  824 +# CONFIG_HW_RANDOM_TIMERIOMEM is not set
  825 +# CONFIG_R3964 is not set
  826 +# CONFIG_RAW_DRIVER is not set
  827 +# CONFIG_TCG_TPM is not set
  828 +# CONFIG_I2C is not set
  829 +# CONFIG_SPI is not set
  830 +# CONFIG_W1 is not set
  831 +# CONFIG_POWER_SUPPLY is not set
  832 +# CONFIG_HWMON is not set
  833 +# CONFIG_THERMAL is not set
  834 +# CONFIG_THERMAL_HWMON is not set
  835 +CONFIG_WATCHDOG=y
  836 +# CONFIG_WATCHDOG_NOWAYOUT is not set
  837 +
  838 +#
  839 +# Watchdog Device Drivers
  840 +#
  841 +# CONFIG_SOFT_WATCHDOG is not set
  842 +CONFIG_AR7_WDT=y
  843 +CONFIG_SSB_POSSIBLE=y
  844 +
  845 +#
  846 +# Sonics Silicon Backplane
  847 +#
  848 +CONFIG_SSB=y
  849 +# CONFIG_SSB_SILENT is not set
  850 +# CONFIG_SSB_DEBUG is not set
  851 +CONFIG_SSB_SERIAL=y
  852 +CONFIG_SSB_DRIVER_MIPS=y
  853 +CONFIG_SSB_EMBEDDED=y
  854 +CONFIG_SSB_DRIVER_EXTIF=y
  855 +
  856 +#
  857 +# Multifunction device drivers
  858 +#
  859 +# CONFIG_MFD_CORE is not set
  860 +# CONFIG_MFD_SM501 is not set
  861 +# CONFIG_HTC_PASIC3 is not set
  862 +# CONFIG_MFD_TMIO is not set
  863 +# CONFIG_REGULATOR is not set
  864 +# CONFIG_MEDIA_SUPPORT is not set
  865 +
  866 +#
  867 +# Graphics support
  868 +#
  869 +# CONFIG_VGASTATE is not set
  870 +# CONFIG_VIDEO_OUTPUT_CONTROL is not set
  871 +# CONFIG_FB is not set
  872 +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
  873 +
  874 +#
  875 +# Display device support
  876 +#
  877 +# CONFIG_DISPLAY_SUPPORT is not set
  878 +# CONFIG_SOUND is not set
  879 +# CONFIG_USB_SUPPORT is not set
  880 +# CONFIG_MMC is not set
  881 +# CONFIG_MEMSTICK is not set
  882 +CONFIG_NEW_LEDS=y
  883 +CONFIG_LEDS_CLASS=y
  884 +
  885 +#
  886 +# LED drivers
  887 +#
  888 +# CONFIG_LEDS_GPIO is not set
  889 +
  890 +#
  891 +# LED Triggers
  892 +#
  893 +CONFIG_LEDS_TRIGGERS=y
  894 +CONFIG_LEDS_TRIGGER_TIMER=y
  895 +CONFIG_LEDS_TRIGGER_HEARTBEAT=y
  896 +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set
  897 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
  898 +
  899 +#
  900 +# iptables trigger is under Netfilter config (LED target)
  901 +#
  902 +# CONFIG_ACCESSIBILITY is not set
  903 +CONFIG_RTC_LIB=y
  904 +# CONFIG_RTC_CLASS is not set
  905 +# CONFIG_DMADEVICES is not set
  906 +# CONFIG_AUXDISPLAY is not set
  907 +# CONFIG_UIO is not set
  908 +
  909 +#
  910 +# TI VLYNQ
  911 +#
  912 +CONFIG_VLYNQ=y
  913 +# CONFIG_STAGING is not set
  914 +
  915 +#
  916 +# File systems
  917 +#
  918 +# CONFIG_EXT2_FS is not set
  919 +# CONFIG_EXT3_FS is not set
  920 +# CONFIG_EXT4_FS is not set
  921 +# CONFIG_REISERFS_FS is not set
  922 +# CONFIG_JFS_FS is not set
  923 +# CONFIG_FS_POSIX_ACL is not set
  924 +# CONFIG_XFS_FS is not set
  925 +# CONFIG_OCFS2_FS is not set
  926 +# CONFIG_BTRFS_FS is not set
  927 +CONFIG_FILE_LOCKING=y
  928 +CONFIG_FSNOTIFY=y
  929 +# CONFIG_DNOTIFY is not set
  930 +# CONFIG_INOTIFY is not set
  931 +CONFIG_INOTIFY_USER=y
  932 +# CONFIG_QUOTA is not set
  933 +# CONFIG_AUTOFS_FS is not set
  934 +# CONFIG_AUTOFS4_FS is not set
  935 +# CONFIG_FUSE_FS is not set
  936 +
  937 +#
  938 +# Caches
  939 +#
  940 +# CONFIG_FSCACHE is not set
  941 +
  942 +#
  943 +# CD-ROM/DVD Filesystems
  944 +#
  945 +# CONFIG_ISO9660_FS is not set
  946 +# CONFIG_UDF_FS is not set
  947 +
  948 +#
  949 +# DOS/FAT/NT Filesystems
  950 +#
  951 +# CONFIG_MSDOS_FS is not set
  952 +# CONFIG_VFAT_FS is not set
  953 +# CONFIG_NTFS_FS is not set
  954 +
  955 +#
  956 +# Pseudo filesystems
  957 +#
  958 +CONFIG_PROC_FS=y
  959 +CONFIG_PROC_KCORE=y
  960 +CONFIG_PROC_SYSCTL=y
  961 +# CONFIG_PROC_PAGE_MONITOR is not set
  962 +CONFIG_SYSFS=y
  963 +CONFIG_TMPFS=y
  964 +# CONFIG_TMPFS_POSIX_ACL is not set
  965 +# CONFIG_HUGETLB_PAGE is not set
  966 +# CONFIG_CONFIGFS_FS is not set
  967 +CONFIG_MISC_FILESYSTEMS=y
  968 +# CONFIG_ADFS_FS is not set
  969 +# CONFIG_AFFS_FS is not set
  970 +# CONFIG_HFS_FS is not set
  971 +# CONFIG_HFSPLUS_FS is not set
  972 +# CONFIG_BEFS_FS is not set
  973 +# CONFIG_BFS_FS is not set
  974 +# CONFIG_EFS_FS is not set
  975 +CONFIG_JFFS2_FS=y
  976 +CONFIG_JFFS2_FS_DEBUG=0
  977 +CONFIG_JFFS2_FS_WRITEBUFFER=y
  978 +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
  979 +CONFIG_JFFS2_SUMMARY=y
  980 +# CONFIG_JFFS2_FS_XATTR is not set
  981 +CONFIG_JFFS2_COMPRESSION_OPTIONS=y
  982 +CONFIG_JFFS2_ZLIB=y
  983 +# CONFIG_JFFS2_LZO is not set
  984 +CONFIG_JFFS2_RTIME=y
  985 +# CONFIG_JFFS2_RUBIN is not set
  986 +# CONFIG_JFFS2_CMODE_NONE is not set
  987 +CONFIG_JFFS2_CMODE_PRIORITY=y
  988 +# CONFIG_JFFS2_CMODE_SIZE is not set
  989 +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set
  990 +# CONFIG_CRAMFS is not set
  991 +CONFIG_SQUASHFS=y
  992 +# CONFIG_SQUASHFS_EMBEDDED is not set
  993 +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
  994 +# CONFIG_VXFS_FS is not set
  995 +# CONFIG_MINIX_FS is not set
  996 +# CONFIG_OMFS_FS is not set
  997 +# CONFIG_HPFS_FS is not set
  998 +# CONFIG_QNX4FS_FS is not set
  999 +# CONFIG_ROMFS_FS is not set
  1000 +# CONFIG_SYSV_FS is not set
  1001 +# CONFIG_UFS_FS is not set
  1002 +# CONFIG_NILFS2_FS is not set
  1003 +CONFIG_NETWORK_FILESYSTEMS=y
  1004 +# CONFIG_NFS_FS is not set
  1005 +# CONFIG_NFSD is not set
  1006 +# CONFIG_SMB_FS is not set
  1007 +# CONFIG_CIFS is not set
  1008 +# CONFIG_NCP_FS is not set
  1009 +# CONFIG_CODA_FS is not set
  1010 +# CONFIG_AFS_FS is not set
  1011 +
  1012 +#
  1013 +# Partition Types
  1014 +#
  1015 +CONFIG_PARTITION_ADVANCED=y
  1016 +# CONFIG_ACORN_PARTITION is not set
  1017 +# CONFIG_OSF_PARTITION is not set
  1018 +# CONFIG_AMIGA_PARTITION is not set
  1019 +# CONFIG_ATARI_PARTITION is not set
  1020 +# CONFIG_MAC_PARTITION is not set
  1021 +CONFIG_MSDOS_PARTITION=y
  1022 +CONFIG_BSD_DISKLABEL=y
  1023 +# CONFIG_MINIX_SUBPARTITION is not set
  1024 +# CONFIG_SOLARIS_X86_PARTITION is not set
  1025 +# CONFIG_UNIXWARE_DISKLABEL is not set
  1026 +# CONFIG_LDM_PARTITION is not set
  1027 +# CONFIG_SGI_PARTITION is not set
  1028 +# CONFIG_ULTRIX_PARTITION is not set
  1029 +# CONFIG_SUN_PARTITION is not set
  1030 +# CONFIG_KARMA_PARTITION is not set
  1031 +# CONFIG_EFI_PARTITION is not set
  1032 +# CONFIG_SYSV68_PARTITION is not set
  1033 +# CONFIG_NLS is not set
  1034 +# CONFIG_DLM is not set
  1035 +
  1036 +#
  1037 +# Kernel hacking
  1038 +#
  1039 +CONFIG_TRACE_IRQFLAGS_SUPPORT=y
  1040 +# CONFIG_PRINTK_TIME is not set
  1041 +CONFIG_ENABLE_WARN_DEPRECATED=y
  1042 +# CONFIG_ENABLE_MUST_CHECK is not set
  1043 +CONFIG_FRAME_WARN=1024
  1044 +# CONFIG_MAGIC_SYSRQ is not set
  1045 +# CONFIG_UNUSED_SYMBOLS is not set
  1046 +CONFIG_DEBUG_FS=y
  1047 +# CONFIG_HEADERS_CHECK is not set
  1048 +# CONFIG_DEBUG_KERNEL is not set
  1049 +# CONFIG_DEBUG_MEMORY_INIT is not set
  1050 +# CONFIG_RCU_CPU_STALL_DETECTOR is not set
  1051 +CONFIG_SYSCTL_SYSCALL_CHECK=y
  1052 +CONFIG_TRACING_SUPPORT=y
  1053 +# CONFIG_FTRACE is not set
  1054 +# CONFIG_DYNAMIC_DEBUG is not set
  1055 +# CONFIG_SAMPLES is not set
  1056 +CONFIG_HAVE_ARCH_KGDB=y
  1057 +CONFIG_CMDLINE="rootfstype=squashfs,jffs2"
  1058 +
  1059 +#
  1060 +# Security options
  1061 +#
  1062 +# CONFIG_KEYS is not set
  1063 +# CONFIG_SECURITY is not set
  1064 +# CONFIG_SECURITYFS is not set
  1065 +# CONFIG_SECURITY_FILE_CAPABILITIES is not set
  1066 +CONFIG_CRYPTO=y
  1067 +
  1068 +#
  1069 +# Crypto core or helper
  1070 +#
  1071 +# CONFIG_CRYPTO_FIPS is not set
  1072 +CONFIG_CRYPTO_ALGAPI=m
  1073 +CONFIG_CRYPTO_ALGAPI2=m
  1074 +CONFIG_CRYPTO_AEAD2=m
  1075 +CONFIG_CRYPTO_BLKCIPHER=m
  1076 +CONFIG_CRYPTO_BLKCIPHER2=m
  1077 +CONFIG_CRYPTO_HASH2=m
  1078 +CONFIG_CRYPTO_RNG2=m
  1079 +CONFIG_CRYPTO_PCOMP=m
  1080 +CONFIG_CRYPTO_MANAGER=m
  1081 +CONFIG_CRYPTO_MANAGER2=m
  1082 +# CONFIG_CRYPTO_GF128MUL is not set
  1083 +# CONFIG_CRYPTO_NULL is not set
  1084 +CONFIG_CRYPTO_WORKQUEUE=m
  1085 +# CONFIG_CRYPTO_CRYPTD is not set
  1086 +# CONFIG_CRYPTO_AUTHENC is not set
  1087 +# CONFIG_CRYPTO_TEST is not set
  1088 +
  1089 +#
  1090 +# Authenticated Encryption with Associated Data
  1091 +#
  1092 +# CONFIG_CRYPTO_CCM is not set
  1093 +# CONFIG_CRYPTO_GCM is not set
  1094 +# CONFIG_CRYPTO_SEQIV is not set
  1095 +
  1096 +#
  1097 +# Block modes
  1098 +#
  1099 +# CONFIG_CRYPTO_CBC is not set
  1100 +# CONFIG_CRYPTO_CTR is not set
  1101 +# CONFIG_CRYPTO_CTS is not set
  1102 +CONFIG_CRYPTO_ECB=m
  1103 +# CONFIG_CRYPTO_LRW is not set
  1104 +# CONFIG_CRYPTO_PCBC is not set
  1105 +# CONFIG_CRYPTO_XTS is not set
  1106 +
  1107 +#
  1108 +# Hash modes
  1109 +#
  1110 +# CONFIG_CRYPTO_HMAC is not set
  1111 +# CONFIG_CRYPTO_XCBC is not set
  1112 +
  1113 +#
  1114 +# Digest
  1115 +#
  1116 +# CONFIG_CRYPTO_CRC32C is not set
  1117 +# CONFIG_CRYPTO_MD4 is not set
  1118 +# CONFIG_CRYPTO_MD5 is not set
  1119 +# CONFIG_CRYPTO_MICHAEL_MIC is not set
  1120 +# CONFIG_CRYPTO_RMD128 is not set
  1121 +# CONFIG_CRYPTO_RMD160 is not set
  1122 +# CONFIG_CRYPTO_RMD256 is not set
  1123 +# CONFIG_CRYPTO_RMD320 is not set
  1124 +# CONFIG_CRYPTO_SHA1 is not set
  1125 +# CONFIG_CRYPTO_SHA256 is not set
  1126 +# CONFIG_CRYPTO_SHA512 is not set
  1127 +# CONFIG_CRYPTO_TGR192 is not set
  1128 +# CONFIG_CRYPTO_WP512 is not set
  1129 +
  1130 +#
  1131 +# Ciphers
  1132 +#
  1133 +CONFIG_CRYPTO_AES=m
  1134 +# CONFIG_CRYPTO_ANUBIS is not set
  1135 +CONFIG_CRYPTO_ARC4=m
  1136 +# CONFIG_CRYPTO_BLOWFISH is not set
  1137 +# CONFIG_CRYPTO_CAMELLIA is not set
  1138 +# CONFIG_CRYPTO_CAST5 is not set
  1139 +# CONFIG_CRYPTO_CAST6 is not set
  1140 +# CONFIG_CRYPTO_DES is not set
  1141 +# CONFIG_CRYPTO_FCRYPT is not set
  1142 +# CONFIG_CRYPTO_KHAZAD is not set
  1143 +# CONFIG_CRYPTO_SALSA20 is not set
  1144 +# CONFIG_CRYPTO_SEED is not set
  1145 +# CONFIG_CRYPTO_SERPENT is not set
  1146 +# CONFIG_CRYPTO_TEA is not set
  1147 +# CONFIG_CRYPTO_TWOFISH is not set
  1148 +
  1149 +#
  1150 +# Compression
  1151 +#
  1152 +# CONFIG_CRYPTO_DEFLATE is not set
  1153 +# CONFIG_CRYPTO_ZLIB is not set
  1154 +# CONFIG_CRYPTO_LZO is not set
  1155 +
  1156 +#
  1157 +# Random Number Generation
  1158 +#
  1159 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
  1160 +# CONFIG_CRYPTO_HW is not set
  1161 +# CONFIG_BINARY_PRINTF is not set
  1162 +
  1163 +#
  1164 +# Library routines
  1165 +#
  1166 +CONFIG_BITREVERSE=y
  1167 +CONFIG_GENERIC_FIND_LAST_BIT=y
  1168 +CONFIG_CRC_CCITT=m
  1169 +# CONFIG_CRC16 is not set
  1170 +# CONFIG_CRC_T10DIF is not set
  1171 +# CONFIG_CRC_ITU_T is not set
  1172 +CONFIG_CRC32=y
  1173 +# CONFIG_CRC7 is not set
  1174 +# CONFIG_LIBCRC32C is not set
  1175 +CONFIG_ZLIB_INFLATE=y
  1176 +CONFIG_ZLIB_DEFLATE=y
  1177 +CONFIG_DECOMPRESS_GZIP=y
  1178 +CONFIG_DECOMPRESS_LZMA=y
  1179 +CONFIG_HAS_IOMEM=y
  1180 +CONFIG_HAS_IOPORT=y
  1181 +CONFIG_HAS_DMA=y
  1182 +CONFIG_NLATTR=y
arch/mips/include/asm/mach-ar7/ar7.h
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
  3 + * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
  4 + *
  5 + * This program is free software; you can redistribute it and/or modify
  6 + * it under the terms of the GNU General Public License as published by
  7 + * the Free Software Foundation; either version 2 of the License, or
  8 + * (at your option) any later version.
  9 + *
  10 + * This program is distributed in the hope that it will be useful,
  11 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 + * GNU General Public License for more details.
  14 + *
  15 + * You should have received a copy of the GNU General Public License
  16 + * along with this program; if not, write to the Free Software
  17 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  18 + */
  19 +
  20 +#ifndef __AR7_H__
  21 +#define __AR7_H__
  22 +
  23 +#include <linux/delay.h>
  24 +#include <linux/io.h>
  25 +#include <linux/errno.h>
  26 +
  27 +#include <asm/addrspace.h>
  28 +
  29 +#define AR7_SDRAM_BASE 0x14000000
  30 +
  31 +#define AR7_REGS_BASE 0x08610000
  32 +
  33 +#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000)
  34 +#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900)
  35 +/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
  36 +#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00)
  37 +#define AR7_REGS_CLOCKS (AR7_REGS_POWER + 0x80)
  38 +#define UR8_REGS_CLOCKS (AR7_REGS_POWER + 0x20)
  39 +#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00)
  40 +#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200)
  41 +#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600)
  42 +#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
  43 +#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00)
  44 +#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
  45 +#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00)
  46 +#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400)
  47 +#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800)
  48 +
  49 +#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00)
  50 +#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00)
  51 +#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00)
  52 +
  53 +#define AR7_RESET_PEREPHERIAL 0x0
  54 +#define AR7_RESET_SOFTWARE 0x4
  55 +#define AR7_RESET_STATUS 0x8
  56 +
  57 +#define AR7_RESET_BIT_CPMAC_LO 17
  58 +#define AR7_RESET_BIT_CPMAC_HI 21
  59 +#define AR7_RESET_BIT_MDIO 22
  60 +#define AR7_RESET_BIT_EPHY 26
  61 +
  62 +/* GPIO control registers */
  63 +#define AR7_GPIO_INPUT 0x0
  64 +#define AR7_GPIO_OUTPUT 0x4
  65 +#define AR7_GPIO_DIR 0x8
  66 +#define AR7_GPIO_ENABLE 0xc
  67 +
  68 +#define AR7_CHIP_7100 0x18
  69 +#define AR7_CHIP_7200 0x2b
  70 +#define AR7_CHIP_7300 0x05
  71 +
  72 +/* Interrupts */
  73 +#define AR7_IRQ_UART0 15
  74 +#define AR7_IRQ_UART1 16
  75 +
  76 +/* Clocks */
  77 +#define AR7_AFE_CLOCK 35328000
  78 +#define AR7_REF_CLOCK 25000000
  79 +#define AR7_XTAL_CLOCK 24000000
  80 +
  81 +struct plat_cpmac_data {
  82 + int reset_bit;
  83 + int power_bit;
  84 + u32 phy_mask;
  85 + char dev_addr[6];
  86 +};
  87 +
  88 +struct plat_dsl_data {
  89 + int reset_bit_dsl;
  90 + int reset_bit_sar;
  91 +};
  92 +
  93 +extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
  94 +
  95 +static inline u16 ar7_chip_id(void)
  96 +{
  97 + return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff;
  98 +}
  99 +
  100 +static inline u8 ar7_chip_rev(void)
  101 +{
  102 + return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff;
  103 +}
  104 +
  105 +static inline int ar7_cpu_freq(void)
  106 +{
  107 + return ar7_cpu_clock;
  108 +}
  109 +
  110 +static inline int ar7_bus_freq(void)
  111 +{
  112 + return ar7_bus_clock;
  113 +}
  114 +
  115 +static inline int ar7_vbus_freq(void)
  116 +{
  117 + return ar7_bus_clock / 2;
  118 +}
  119 +#define ar7_cpmac_freq ar7_vbus_freq
  120 +
  121 +static inline int ar7_dsp_freq(void)
  122 +{
  123 + return ar7_dsp_clock;
  124 +}
  125 +
  126 +static inline int ar7_has_high_cpmac(void)
  127 +{
  128 + u16 chip_id = ar7_chip_id();
  129 + switch (chip_id) {
  130 + case AR7_CHIP_7100:
  131 + case AR7_CHIP_7200:
  132 + return 0;
  133 + case AR7_CHIP_7300:
  134 + return 1;
  135 + default:
  136 + return -ENXIO;
  137 + }
  138 +}
  139 +#define ar7_has_high_vlynq ar7_has_high_cpmac
  140 +#define ar7_has_second_uart ar7_has_high_cpmac
  141 +
  142 +static inline void ar7_device_enable(u32 bit)
  143 +{
  144 + void *reset_reg =
  145 + (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
  146 + writel(readl(reset_reg) | (1 << bit), reset_reg);
  147 + msleep(20);
  148 +}
  149 +
  150 +static inline void ar7_device_disable(u32 bit)
  151 +{
  152 + void *reset_reg =
  153 + (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
  154 + writel(readl(reset_reg) & ~(1 << bit), reset_reg);
  155 + msleep(20);
  156 +}
  157 +
  158 +static inline void ar7_device_reset(u32 bit)
  159 +{
  160 + ar7_device_disable(bit);
  161 + ar7_device_enable(bit);
  162 +}
  163 +
  164 +static inline void ar7_device_on(u32 bit)
  165 +{
  166 + void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
  167 + writel(readl(power_reg) | (1 << bit), power_reg);
  168 + msleep(20);
  169 +}
  170 +
  171 +static inline void ar7_device_off(u32 bit)
  172 +{
  173 + void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
  174 + writel(readl(power_reg) & ~(1 << bit), power_reg);
  175 + msleep(20);
  176 +}
  177 +
  178 +#endif /* __AR7_H__ */
arch/mips/include/asm/mach-ar7/gpio.h
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * Copyright (C) 2007 Florian Fainelli <florian@openwrt.org>
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License as published by
  6 + * the Free Software Foundation; either version 2 of the License, or
  7 + * (at your option) any later version.
  8 + *
  9 + * This program is distributed in the hope that it will be useful,
  10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 + * GNU General Public License for more details.
  13 + *
  14 + * You should have received a copy of the GNU General Public License
  15 + * along with this program; if not, write to the Free Software
  16 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17 + */
  18 +
  19 +#ifndef __AR7_GPIO_H__
  20 +#define __AR7_GPIO_H__
  21 +
  22 +#include <asm/mach-ar7/ar7.h>
  23 +
  24 +#define AR7_GPIO_MAX 32
  25 +
  26 +extern int gpio_request(unsigned gpio, const char *label);
  27 +extern void gpio_free(unsigned gpio);
  28 +
  29 +/* Common GPIO layer */
  30 +static inline int gpio_get_value(unsigned gpio)
  31 +{
  32 + void __iomem *gpio_in =
  33 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT);
  34 +
  35 + return readl(gpio_in) & (1 << gpio);
  36 +}
  37 +
  38 +static inline void gpio_set_value(unsigned gpio, int value)
  39 +{
  40 + void __iomem *gpio_out =
  41 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT);
  42 + unsigned tmp;
  43 +
  44 + tmp = readl(gpio_out) & ~(1 << gpio);
  45 + if (value)
  46 + tmp |= 1 << gpio;
  47 + writel(tmp, gpio_out);
  48 +}
  49 +
  50 +static inline int gpio_direction_input(unsigned gpio)
  51 +{
  52 + void __iomem *gpio_dir =
  53 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
  54 +
  55 + if (gpio >= AR7_GPIO_MAX)
  56 + return -EINVAL;
  57 +
  58 + writel(readl(gpio_dir) | (1 << gpio), gpio_dir);
  59 +
  60 + return 0;
  61 +}
  62 +
  63 +static inline int gpio_direction_output(unsigned gpio, int value)
  64 +{
  65 + void __iomem *gpio_dir =
  66 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR);
  67 +
  68 + if (gpio >= AR7_GPIO_MAX)
  69 + return -EINVAL;
  70 +
  71 + gpio_set_value(gpio, value);
  72 + writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir);
  73 +
  74 + return 0;
  75 +}
  76 +
  77 +static inline int gpio_to_irq(unsigned gpio)
  78 +{
  79 + return -EINVAL;
  80 +}
  81 +
  82 +static inline int irq_to_gpio(unsigned irq)
  83 +{
  84 + return -EINVAL;
  85 +}
  86 +
  87 +/* Board specific GPIO functions */
  88 +static inline int ar7_gpio_enable(unsigned gpio)
  89 +{
  90 + void __iomem *gpio_en =
  91 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
  92 +
  93 + writel(readl(gpio_en) | (1 << gpio), gpio_en);
  94 +
  95 + return 0;
  96 +}
  97 +
  98 +static inline int ar7_gpio_disable(unsigned gpio)
  99 +{
  100 + void __iomem *gpio_en =
  101 + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE);
  102 +
  103 + writel(readl(gpio_en) & ~(1 << gpio), gpio_en);
  104 +
  105 + return 0;
  106 +}
  107 +
  108 +#include <asm-generic/gpio.h>
  109 +
  110 +#endif
arch/mips/include/asm/mach-ar7/irq.h
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * This file is subject to the terms and conditions of the GNU General Public
  3 + * License. See the file "COPYING" in the main directory of this archive
  4 + * for more details.
  5 + *
  6 + * Shamelessly copied from asm-mips/mach-emma2rh/
  7 + * Copyright (C) 2003 by Ralf Baechle
  8 + */
  9 +#ifndef __ASM_AR7_IRQ_H
  10 +#define __ASM_AR7_IRQ_H
  11 +
  12 +#define NR_IRQS 256
  13 +
  14 +#include_next <irq.h>
  15 +
  16 +#endif /* __ASM_AR7_IRQ_H */
arch/mips/include/asm/mach-ar7/prom.h
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * Copyright (C) 2006, 2007 Florian Fainelli <florian@openwrt.org>
  3 + *
  4 + * This program is free software; you can redistribute it and/or modify
  5 + * it under the terms of the GNU General Public License as published by
  6 + * the Free Software Foundation; either version 2 of the License, or
  7 + * (at your option) any later version.
  8 + *
  9 + * This program is distributed in the hope that it will be useful,
  10 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12 + * GNU General Public License for more details.
  13 + *
  14 + * You should have received a copy of the GNU General Public License
  15 + * along with this program; if not, write to the Free Software
  16 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  17 + */
  18 +
  19 +#ifndef __PROM_H__
  20 +#define __PROM_H__
  21 +
  22 +extern char *prom_getenv(const char *name);
  23 +extern void prom_meminit(void);
  24 +
  25 +#endif /* __PROM_H__ */
arch/mips/include/asm/mach-ar7/spaces.h
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * This file is subject to the terms and conditions of the GNU General Public
  3 + * License. See the file "COPYING" in the main directory of this archive
  4 + * for more details.
  5 + *
  6 + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
  7 + * Copyright (C) 2000, 2002 Maciej W. Rozycki
  8 + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
  9 + */
  10 +#ifndef _ASM_AR7_SPACES_H
  11 +#define _ASM_AR7_SPACES_H
  12 +
  13 +/*
  14 + * This handles the memory map.
  15 + * We handle pages at KSEG0 for kernels with 32 bit address space.
  16 + */
  17 +#define PAGE_OFFSET 0x94000000UL
  18 +#define PHYS_OFFSET 0x14000000UL
  19 +
  20 +#include <asm/mach-generic/spaces.h>
  21 +
  22 +#endif /* __ASM_AR7_SPACES_H */
arch/mips/include/asm/mach-ar7/war.h
Diff comments   View file @ 7ca5dc1
  1 +/*
  2 + * This file is subject to the terms and conditions of the GNU General Public
  3 + * License. See the file "COPYING" in the main directory of this archive
  4 + * for more details.
  5 + *
  6 + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
  7 + */
  8 +#ifndef __ASM_MIPS_MACH_AR7_WAR_H
  9 +#define __ASM_MIPS_MACH_AR7_WAR_H
  10 +
  11 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
  12 +#define R4600_V1_HIT_CACHEOP_WAR 0
  13 +#define R4600_V2_HIT_CACHEOP_WAR 0
  14 +#define R5432_CP0_INTERRUPT_WAR 0
  15 +#define BCM1250_M3_WAR 0
  16 +#define SIBYTE_1956_WAR 0
  17 +#define MIPS4K_ICACHE_REFILL_WAR 0
  18 +#define MIPS_CACHE_SYNC_WAR 0
  19 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
  20 +#define RM9000_CDEX_SMP_WAR 0
  21 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
  22 +#define R10000_LLSC_WAR 0
  23 +#define MIPS34K_MISSED_ITLB_WAR 0
  24 +
  25 +#endif /* __ASM_MIPS_MACH_AR7_WAR_H */