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Commit 7d0857a54aedbd47b3de503933d65ce462970bd6

Authored by Vineet Gupta
1 parent 57e26e5745
Exists in smarc-imx_3.14.28_1.0.0_ga and in 1 other branch imx_3.14.28_1.0.0_ga

ARC: [SMP] Disallow RTSC 

RTSC is strictly incore and must not be allowed in SMP configs

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

Showing 2 changed files with 5 additions and 8 deletions Inline Diff

1 # 1 #
2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3 # 3 #
4 # This program is free software; you can redistribute it and/or modify 4 # This program is free software; you can redistribute it and/or modify
5 # it under the terms of the GNU General Public License version 2 as 5 # it under the terms of the GNU General Public License version 2 as
6 # published by the Free Software Foundation. 6 # published by the Free Software Foundation.
7 # 7 #
8 8
9 config ARC 9 config ARC
10 def_bool y 10 def_bool y
11 select CLONE_BACKWARDS 11 select CLONE_BACKWARDS
12 # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev 12 # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
13 select DEVTMPFS if !INITRAMFS_SOURCE="" 13 select DEVTMPFS if !INITRAMFS_SOURCE=""
14 select GENERIC_ATOMIC64 14 select GENERIC_ATOMIC64
15 select GENERIC_CLOCKEVENTS 15 select GENERIC_CLOCKEVENTS
16 select GENERIC_FIND_FIRST_BIT 16 select GENERIC_FIND_FIRST_BIT
17 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP 17 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
18 select GENERIC_IRQ_SHOW 18 select GENERIC_IRQ_SHOW
19 select GENERIC_PENDING_IRQ if SMP 19 select GENERIC_PENDING_IRQ if SMP
20 select GENERIC_SMP_IDLE_THREAD 20 select GENERIC_SMP_IDLE_THREAD
21 select HAVE_ARCH_KGDB 21 select HAVE_ARCH_KGDB
22 select HAVE_ARCH_TRACEHOOK 22 select HAVE_ARCH_TRACEHOOK
23 select HAVE_IOREMAP_PROT 23 select HAVE_IOREMAP_PROT
24 select HAVE_KPROBES 24 select HAVE_KPROBES
25 select HAVE_KRETPROBES 25 select HAVE_KRETPROBES
26 select HAVE_MEMBLOCK 26 select HAVE_MEMBLOCK
27 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND 27 select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
28 select HAVE_OPROFILE 28 select HAVE_OPROFILE
29 select HAVE_PERF_EVENTS 29 select HAVE_PERF_EVENTS
30 select IRQ_DOMAIN 30 select IRQ_DOMAIN
31 select MODULES_USE_ELF_RELA 31 select MODULES_USE_ELF_RELA
32 select NO_BOOTMEM 32 select NO_BOOTMEM
33 select OF 33 select OF
34 select OF_EARLY_FLATTREE 34 select OF_EARLY_FLATTREE
35 select PERF_USE_VMALLOC 35 select PERF_USE_VMALLOC
36 select HAVE_DEBUG_STACKOVERFLOW 36 select HAVE_DEBUG_STACKOVERFLOW
37 37
38 config TRACE_IRQFLAGS_SUPPORT 38 config TRACE_IRQFLAGS_SUPPORT
39 def_bool y 39 def_bool y
40 40
41 config LOCKDEP_SUPPORT 41 config LOCKDEP_SUPPORT
42 def_bool y 42 def_bool y
43 43
44 config SCHED_OMIT_FRAME_POINTER 44 config SCHED_OMIT_FRAME_POINTER
45 def_bool y 45 def_bool y
46 46
47 config GENERIC_CSUM 47 config GENERIC_CSUM
48 def_bool y 48 def_bool y
49 49
50 config RWSEM_GENERIC_SPINLOCK 50 config RWSEM_GENERIC_SPINLOCK
51 def_bool y 51 def_bool y
52 52
53 config ARCH_FLATMEM_ENABLE 53 config ARCH_FLATMEM_ENABLE
54 def_bool y 54 def_bool y
55 55
56 config MMU 56 config MMU
57 def_bool y 57 def_bool y
58 58
59 config NO_IOPORT 59 config NO_IOPORT
60 def_bool y 60 def_bool y
61 61
62 config GENERIC_CALIBRATE_DELAY 62 config GENERIC_CALIBRATE_DELAY
63 def_bool y 63 def_bool y
64 64
65 config GENERIC_HWEIGHT 65 config GENERIC_HWEIGHT
66 def_bool y 66 def_bool y
67 67
68 config STACKTRACE_SUPPORT 68 config STACKTRACE_SUPPORT
69 def_bool y 69 def_bool y
70 select STACKTRACE 70 select STACKTRACE
71 71
72 config HAVE_LATENCYTOP_SUPPORT 72 config HAVE_LATENCYTOP_SUPPORT
73 def_bool y 73 def_bool y
74 74
75 config NO_DMA 75 config NO_DMA
76 def_bool n 76 def_bool n
77 77
78 source "init/Kconfig" 78 source "init/Kconfig"
79 source "kernel/Kconfig.freezer" 79 source "kernel/Kconfig.freezer"
80 80
81 menu "ARC Architecture Configuration" 81 menu "ARC Architecture Configuration"
82 82
83 menu "ARC Platform/SoC/Board" 83 menu "ARC Platform/SoC/Board"
84 84
85 source "arch/arc/plat-arcfpga/Kconfig" 85 source "arch/arc/plat-arcfpga/Kconfig"
86 source "arch/arc/plat-tb10x/Kconfig" 86 source "arch/arc/plat-tb10x/Kconfig"
87 #New platform adds here 87 #New platform adds here
88 88
89 endmenu 89 endmenu
90 90
91 menu "ARC CPU Configuration" 91 menu "ARC CPU Configuration"
92 92
93 choice 93 choice
94 prompt "ARC Core" 94 prompt "ARC Core"
95 default ARC_CPU_770 95 default ARC_CPU_770
96 96
97 config ARC_CPU_750D 97 config ARC_CPU_750D
98 bool "ARC750D" 98 bool "ARC750D"
99 help 99 help
100 Support for ARC750 core 100 Support for ARC750 core
101 101
102 config ARC_CPU_770 102 config ARC_CPU_770
103 bool "ARC770" 103 bool "ARC770"
104 select ARC_CPU_REL_4_10 104 select ARC_CPU_REL_4_10
105 help 105 help
106 Support for ARC770 core introduced with Rel 4.10 (Summer 2011) 106 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
107 This core has a bunch of cool new features: 107 This core has a bunch of cool new features:
108 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) 108 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
109 Shared Address Spaces (for sharing TLB entires in MMU) 109 Shared Address Spaces (for sharing TLB entires in MMU)
110 -Caches: New Prog Model, Region Flush 110 -Caches: New Prog Model, Region Flush
111 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr 111 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
112 112
113 endchoice 113 endchoice
114 114
115 config CPU_BIG_ENDIAN 115 config CPU_BIG_ENDIAN
116 bool "Enable Big Endian Mode" 116 bool "Enable Big Endian Mode"
117 default n 117 default n
118 help 118 help
119 Build kernel for Big Endian Mode of ARC CPU 119 Build kernel for Big Endian Mode of ARC CPU
120 120
121 # If a platform can't work with 0x8000_0000 based dma_addr_t 121 # If a platform can't work with 0x8000_0000 based dma_addr_t
122 config ARC_PLAT_NEEDS_CPU_TO_DMA 122 config ARC_PLAT_NEEDS_CPU_TO_DMA
123 bool 123 bool
124 124
125 config SMP 125 config SMP
126 bool "Symmetric Multi-Processing (Incomplete)" 126 bool "Symmetric Multi-Processing (Incomplete)"
127 default n 127 default n
128 select USE_GENERIC_SMP_HELPERS 128 select USE_GENERIC_SMP_HELPERS
129 help 129 help
130 This enables support for systems with more than one CPU. If you have 130 This enables support for systems with more than one CPU. If you have
131 a system with only one CPU, like most personal computers, say N. If 131 a system with only one CPU, like most personal computers, say N. If
132 you have a system with more than one CPU, say Y. 132 you have a system with more than one CPU, say Y.
133 133
134 if SMP 134 if SMP
135 135
136 config ARC_HAS_COH_CACHES 136 config ARC_HAS_COH_CACHES
137 def_bool n 137 def_bool n
138 138
139 config ARC_HAS_COH_RTSC
140 def_bool n
141
142 config ARC_HAS_REENTRANT_IRQ_LV2 139 config ARC_HAS_REENTRANT_IRQ_LV2
143 def_bool n 140 def_bool n
144 141
145 endif 142 endif
146 143
147 config NR_CPUS 144 config NR_CPUS
148 int "Maximum number of CPUs (2-4096)" 145 int "Maximum number of CPUs (2-4096)"
149 range 2 4096 146 range 2 4096
150 depends on SMP 147 depends on SMP
151 default "2" 148 default "2"
152 149
153 menuconfig ARC_CACHE 150 menuconfig ARC_CACHE
154 bool "Enable Cache Support" 151 bool "Enable Cache Support"
155 default y 152 default y
156 # if SMP, cache enabled ONLY if ARC implementation has cache coherency 153 # if SMP, cache enabled ONLY if ARC implementation has cache coherency
157 depends on !SMP || ARC_HAS_COH_CACHES 154 depends on !SMP || ARC_HAS_COH_CACHES
158 155
159 if ARC_CACHE 156 if ARC_CACHE
160 157
161 config ARC_CACHE_LINE_SHIFT 158 config ARC_CACHE_LINE_SHIFT
162 int "Cache Line Length (as power of 2)" 159 int "Cache Line Length (as power of 2)"
163 range 5 7 160 range 5 7
164 default "6" 161 default "6"
165 help 162 help
166 Starting with ARC700 4.9, Cache line length is configurable, 163 Starting with ARC700 4.9, Cache line length is configurable,
167 This option specifies "N", with Line-len = 2 power N 164 This option specifies "N", with Line-len = 2 power N
168 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively 165 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
169 Linux only supports same line lengths for I and D caches. 166 Linux only supports same line lengths for I and D caches.
170 167
171 config ARC_HAS_ICACHE 168 config ARC_HAS_ICACHE
172 bool "Use Instruction Cache" 169 bool "Use Instruction Cache"
173 default y 170 default y
174 171
175 config ARC_HAS_DCACHE 172 config ARC_HAS_DCACHE
176 bool "Use Data Cache" 173 bool "Use Data Cache"
177 default y 174 default y
178 175
179 config ARC_CACHE_PAGES 176 config ARC_CACHE_PAGES
180 bool "Per Page Cache Control" 177 bool "Per Page Cache Control"
181 default y 178 default y
182 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE 179 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
183 help 180 help
184 This can be used to over-ride the global I/D Cache Enable on a 181 This can be used to over-ride the global I/D Cache Enable on a
185 per-page basis (but only for pages accessed via MMU such as 182 per-page basis (but only for pages accessed via MMU such as
186 Kernel Virtual address or User Virtual Address) 183 Kernel Virtual address or User Virtual Address)
187 TLB entries have a per-page Cache Enable Bit. 184 TLB entries have a per-page Cache Enable Bit.
188 Note that Global I/D ENABLE + Per Page DISABLE works but corollary 185 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
189 Global DISABLE + Per Page ENABLE won't work 186 Global DISABLE + Per Page ENABLE won't work
190 187
191 config ARC_CACHE_VIPT_ALIASING 188 config ARC_CACHE_VIPT_ALIASING
192 bool "Support VIPT Aliasing D$" 189 bool "Support VIPT Aliasing D$"
193 depends on ARC_HAS_DCACHE 190 depends on ARC_HAS_DCACHE
194 default n 191 default n
195 192
196 endif #ARC_CACHE 193 endif #ARC_CACHE
197 194
198 config ARC_HAS_ICCM 195 config ARC_HAS_ICCM
199 bool "Use ICCM" 196 bool "Use ICCM"
200 help 197 help
201 Single Cycle RAMS to store Fast Path Code 198 Single Cycle RAMS to store Fast Path Code
202 default n 199 default n
203 200
204 config ARC_ICCM_SZ 201 config ARC_ICCM_SZ
205 int "ICCM Size in KB" 202 int "ICCM Size in KB"
206 default "64" 203 default "64"
207 depends on ARC_HAS_ICCM 204 depends on ARC_HAS_ICCM
208 205
209 config ARC_HAS_DCCM 206 config ARC_HAS_DCCM
210 bool "Use DCCM" 207 bool "Use DCCM"
211 help 208 help
212 Single Cycle RAMS to store Fast Path Data 209 Single Cycle RAMS to store Fast Path Data
213 default n 210 default n
214 211
215 config ARC_DCCM_SZ 212 config ARC_DCCM_SZ
216 int "DCCM Size in KB" 213 int "DCCM Size in KB"
217 default "64" 214 default "64"
218 depends on ARC_HAS_DCCM 215 depends on ARC_HAS_DCCM
219 216
220 config ARC_DCCM_BASE 217 config ARC_DCCM_BASE
221 hex "DCCM map address" 218 hex "DCCM map address"
222 default "0xA0000000" 219 default "0xA0000000"
223 depends on ARC_HAS_DCCM 220 depends on ARC_HAS_DCCM
224 221
225 config ARC_HAS_HW_MPY 222 config ARC_HAS_HW_MPY
226 bool "Use Hardware Multiplier (Normal or Faster XMAC)" 223 bool "Use Hardware Multiplier (Normal or Faster XMAC)"
227 default y 224 default y
228 help 225 help
229 Influences how gcc generates code for MPY operations. 226 Influences how gcc generates code for MPY operations.
230 If enabled, MPYxx insns are generated, provided by Standard/XMAC 227 If enabled, MPYxx insns are generated, provided by Standard/XMAC
231 Multipler. Otherwise software multipy lib is used 228 Multipler. Otherwise software multipy lib is used
232 229
233 choice 230 choice
234 prompt "ARC700 MMU Version" 231 prompt "ARC700 MMU Version"
235 default ARC_MMU_V3 if ARC_CPU_770 232 default ARC_MMU_V3 if ARC_CPU_770
236 default ARC_MMU_V2 if ARC_CPU_750D 233 default ARC_MMU_V2 if ARC_CPU_750D
237 234
238 config ARC_MMU_V1 235 config ARC_MMU_V1
239 bool "MMU v1" 236 bool "MMU v1"
240 help 237 help
241 Orig ARC700 MMU 238 Orig ARC700 MMU
242 239
243 config ARC_MMU_V2 240 config ARC_MMU_V2
244 bool "MMU v2" 241 bool "MMU v2"
245 help 242 help
246 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio 243 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
247 when 2 D-TLB and 1 I-TLB entries index into same 2way set. 244 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
248 245
249 config ARC_MMU_V3 246 config ARC_MMU_V3
250 bool "MMU v3" 247 bool "MMU v3"
251 depends on ARC_CPU_770 248 depends on ARC_CPU_770
252 help 249 help
253 Introduced with ARC700 4.10: New Features 250 Introduced with ARC700 4.10: New Features
254 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) 251 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
255 Shared Address Spaces (SASID) 252 Shared Address Spaces (SASID)
256 253
257 endchoice 254 endchoice
258 255
259 256
260 choice 257 choice
261 prompt "MMU Page Size" 258 prompt "MMU Page Size"
262 default ARC_PAGE_SIZE_8K 259 default ARC_PAGE_SIZE_8K
263 260
264 config ARC_PAGE_SIZE_8K 261 config ARC_PAGE_SIZE_8K
265 bool "8KB" 262 bool "8KB"
266 help 263 help
267 Choose between 8k vs 16k 264 Choose between 8k vs 16k
268 265
269 config ARC_PAGE_SIZE_16K 266 config ARC_PAGE_SIZE_16K
270 bool "16KB" 267 bool "16KB"
271 depends on ARC_MMU_V3 268 depends on ARC_MMU_V3
272 269
273 config ARC_PAGE_SIZE_4K 270 config ARC_PAGE_SIZE_4K
274 bool "4KB" 271 bool "4KB"
275 depends on ARC_MMU_V3 272 depends on ARC_MMU_V3
276 273
277 endchoice 274 endchoice
278 275
279 config ARC_COMPACT_IRQ_LEVELS 276 config ARC_COMPACT_IRQ_LEVELS
280 bool "ARCompact IRQ Priorities: High(2)/Low(1)" 277 bool "ARCompact IRQ Priorities: High(2)/Low(1)"
281 default n 278 default n
282 # Timer HAS to be high priority, for any other high priority config 279 # Timer HAS to be high priority, for any other high priority config
283 select ARC_IRQ3_LV2 280 select ARC_IRQ3_LV2
284 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy 281 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
285 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2 282 depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
286 283
287 if ARC_COMPACT_IRQ_LEVELS 284 if ARC_COMPACT_IRQ_LEVELS
288 285
289 config ARC_IRQ3_LV2 286 config ARC_IRQ3_LV2
290 bool 287 bool
291 288
292 config ARC_IRQ5_LV2 289 config ARC_IRQ5_LV2
293 bool 290 bool
294 291
295 config ARC_IRQ6_LV2 292 config ARC_IRQ6_LV2
296 bool 293 bool
297 294
298 endif 295 endif
299 296
300 config ARC_FPU_SAVE_RESTORE 297 config ARC_FPU_SAVE_RESTORE
301 bool "Enable FPU state persistence across context switch" 298 bool "Enable FPU state persistence across context switch"
302 default n 299 default n
303 help 300 help
304 Double Precision Floating Point unit had dedictaed regs which 301 Double Precision Floating Point unit had dedictaed regs which
305 need to be saved/restored across context-switch. 302 need to be saved/restored across context-switch.
306 Note that ARC FPU is overly simplistic, unlike say x86, which has 303 Note that ARC FPU is overly simplistic, unlike say x86, which has
307 hardware pieces to allow software to conditionally save/restore, 304 hardware pieces to allow software to conditionally save/restore,
308 based on actual usage of FPU by a task. Thus our implemn does 305 based on actual usage of FPU by a task. Thus our implemn does
309 this for all tasks in system. 306 this for all tasks in system.
310 307
311 config ARC_CANT_LLSC 308 config ARC_CANT_LLSC
312 def_bool n 309 def_bool n
313 310
314 menuconfig ARC_CPU_REL_4_10 311 menuconfig ARC_CPU_REL_4_10
315 bool "Enable support for Rel 4.10 features" 312 bool "Enable support for Rel 4.10 features"
316 default n 313 default n
317 help 314 help
318 -ARC770 (and dependent features) enabled 315 -ARC770 (and dependent features) enabled
319 -ARC750 also shares some of the new features with 770 316 -ARC750 also shares some of the new features with 770
320 317
321 config ARC_HAS_LLSC 318 config ARC_HAS_LLSC
322 bool "Insn: LLOCK/SCOND (efficient atomic ops)" 319 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
323 default y 320 default y
324 depends on ARC_CPU_770 && !ARC_CANT_LLSC 321 depends on ARC_CPU_770 && !ARC_CANT_LLSC
325 322
326 config ARC_HAS_SWAPE 323 config ARC_HAS_SWAPE
327 bool "Insn: SWAPE (endian-swap)" 324 bool "Insn: SWAPE (endian-swap)"
328 default y 325 default y
329 depends on ARC_CPU_REL_4_10 326 depends on ARC_CPU_REL_4_10
330 327
331 config ARC_HAS_RTSC 328 config ARC_HAS_RTSC
332 bool "Insn: RTSC (64-bit r/o cycle counter)" 329 bool "Insn: RTSC (64-bit r/o cycle counter)"
333 default y 330 default y
334 depends on ARC_CPU_REL_4_10 331 depends on ARC_CPU_REL_4_10
335 # if SMP, enable RTSC only if counter is coherent across cores 332 depends on !SMP
336 depends on !SMP || ARC_HAS_COH_RTSC
337 333
338 endmenu # "ARC CPU Configuration" 334 endmenu # "ARC CPU Configuration"
339 335
340 config LINUX_LINK_BASE 336 config LINUX_LINK_BASE
341 hex "Linux Link Address" 337 hex "Linux Link Address"
342 default "0x80000000" 338 default "0x80000000"
343 help 339 help
344 ARC700 divides the 32 bit phy address space into two equal halves 340 ARC700 divides the 32 bit phy address space into two equal halves
345 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU 341 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
346 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel 342 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
347 Typically Linux kernel is linked at the start of untransalted addr, 343 Typically Linux kernel is linked at the start of untransalted addr,
348 hence the default value of 0x8zs. 344 hence the default value of 0x8zs.
349 However some customers have peripherals mapped at this addr, so 345 However some customers have peripherals mapped at this addr, so
350 Linux needs to be scooted a bit. 346 Linux needs to be scooted a bit.
351 If you don't know what the above means, leave this setting alone. 347 If you don't know what the above means, leave this setting alone.
352 348
353 config ARC_CURR_IN_REG 349 config ARC_CURR_IN_REG
354 bool "Dedicate Register r25 for current_task pointer" 350 bool "Dedicate Register r25 for current_task pointer"
355 default y 351 default y
356 help 352 help
357 This reserved Register R25 to point to Current Task in 353 This reserved Register R25 to point to Current Task in
358 kernel mode. This saves memory access for each such access 354 kernel mode. This saves memory access for each such access
359 355
360 356
361 config ARC_MISALIGN_ACCESS 357 config ARC_MISALIGN_ACCESS
362 bool "Emulate unaligned memory access (userspace only)" 358 bool "Emulate unaligned memory access (userspace only)"
363 default N 359 default N
364 select SYSCTL_ARCH_UNALIGN_NO_WARN 360 select SYSCTL_ARCH_UNALIGN_NO_WARN
365 select SYSCTL_ARCH_UNALIGN_ALLOW 361 select SYSCTL_ARCH_UNALIGN_ALLOW
366 help 362 help
367 This enables misaligned 16 & 32 bit memory access from user space. 363 This enables misaligned 16 & 32 bit memory access from user space.
368 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide 364 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
369 potential bugs in code 365 potential bugs in code
370 366
371 config HZ 367 config HZ
372 int "Timer Frequency" 368 int "Timer Frequency"
373 default 100 369 default 100
374 370
375 config ARC_METAWARE_HLINK 371 config ARC_METAWARE_HLINK
376 bool "Support for Metaware debugger assisted Host access" 372 bool "Support for Metaware debugger assisted Host access"
377 default n 373 default n
378 help 374 help
379 This options allows a Linux userland apps to directly access 375 This options allows a Linux userland apps to directly access
380 host file system (open/creat/read/write etc) with help from 376 host file system (open/creat/read/write etc) with help from
381 Metaware Debugger. This can come in handy for Linux-host communication 377 Metaware Debugger. This can come in handy for Linux-host communication
382 when there is no real usable peripheral such as EMAC. 378 when there is no real usable peripheral such as EMAC.
383 379
384 menuconfig ARC_DBG 380 menuconfig ARC_DBG
385 bool "ARC debugging" 381 bool "ARC debugging"
386 default y 382 default y
387 383
388 config ARC_DW2_UNWIND 384 config ARC_DW2_UNWIND
389 bool "Enable DWARF specific kernel stack unwind" 385 bool "Enable DWARF specific kernel stack unwind"
390 depends on ARC_DBG 386 depends on ARC_DBG
391 default y 387 default y
392 select KALLSYMS 388 select KALLSYMS
393 help 389 help
394 Compiles the kernel with DWARF unwind information and can be used 390 Compiles the kernel with DWARF unwind information and can be used
395 to get stack backtraces. 391 to get stack backtraces.
396 392
397 If you say Y here the resulting kernel image will be slightly larger 393 If you say Y here the resulting kernel image will be slightly larger
398 but not slower, and it will give very useful debugging information. 394 but not slower, and it will give very useful debugging information.
399 If you don't debug the kernel, you can say N, but we may not be able 395 If you don't debug the kernel, you can say N, but we may not be able
400 to solve problems without frame unwind information 396 to solve problems without frame unwind information
401 397
402 config ARC_DBG_TLB_PARANOIA 398 config ARC_DBG_TLB_PARANOIA
403 bool "Paranoia Checks in Low Level TLB Handlers" 399 bool "Paranoia Checks in Low Level TLB Handlers"
404 depends on ARC_DBG 400 depends on ARC_DBG
405 default n 401 default n
406 402
407 config ARC_DBG_TLB_MISS_COUNT 403 config ARC_DBG_TLB_MISS_COUNT
408 bool "Profile TLB Misses" 404 bool "Profile TLB Misses"
409 default n 405 default n
410 select DEBUG_FS 406 select DEBUG_FS
411 depends on ARC_DBG 407 depends on ARC_DBG
412 help 408 help
413 Counts number of I and D TLB Misses and exports them via Debugfs 409 Counts number of I and D TLB Misses and exports them via Debugfs
414 The counters can be cleared via Debugfs as well 410 The counters can be cleared via Debugfs as well
415 411
416 config CMDLINE_UBOOT 412 config CMDLINE_UBOOT
417 bool "Support U-boot kernel command line passing" 413 bool "Support U-boot kernel command line passing"
418 default n 414 default n
419 help 415 help
420 If you are using U-boot (www.denx.de) and wish to pass the kernel 416 If you are using U-boot (www.denx.de) and wish to pass the kernel
421 command line from the U-boot environment to the Linux kernel then 417 command line from the U-boot environment to the Linux kernel then
422 switch this option on. 418 switch this option on.
423 ARC U-boot will setup the cmdline in RAM/flash and set r2 to point 419 ARC U-boot will setup the cmdline in RAM/flash and set r2 to point
424 to it. kernel startup code will append this to DeviceTree 420 to it. kernel startup code will append this to DeviceTree
425 /bootargs provided cmdline args. 421 /bootargs provided cmdline args.
426 422
427 config ARC_BUILTIN_DTB_NAME 423 config ARC_BUILTIN_DTB_NAME
428 string "Built in DTB" 424 string "Built in DTB"
429 help 425 help
430 Set the name of the DTB to embed in the vmlinux binary 426 Set the name of the DTB to embed in the vmlinux binary
431 Leaving it blank selects the minimal "skeleton" dtb 427 Leaving it blank selects the minimal "skeleton" dtb
432 428
433 source "kernel/Kconfig.preempt" 429 source "kernel/Kconfig.preempt"
434 430
435 menu "Executable file formats" 431 menu "Executable file formats"
436 source "fs/Kconfig.binfmt" 432 source "fs/Kconfig.binfmt"
437 endmenu 433 endmenu
438 434
439 endmenu # "ARC Architecture Configuration" 435 endmenu # "ARC Architecture Configuration"
440 436
441 source "mm/Kconfig" 437 source "mm/Kconfig"
442 source "net/Kconfig" 438 source "net/Kconfig"
443 source "drivers/Kconfig" 439 source "drivers/Kconfig"
444 source "fs/Kconfig" 440 source "fs/Kconfig"
445 source "arch/arc/Kconfig.debug" 441 source "arch/arc/Kconfig.debug"
446 source "security/Kconfig" 442 source "security/Kconfig"
447 source "crypto/Kconfig" 443 source "crypto/Kconfig"
448 source "lib/Kconfig" 444 source "lib/Kconfig"
449 445
arch/arc/kernel/time.c
Diff comments   View file @ 7d0857a
1 /* 1 /*
2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) 2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as 5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation. 6 * published by the Free Software Foundation.
7 * 7 *
8 * vineetg: Jan 1011 8 * vineetg: Jan 1011
9 * -sched_clock( ) no longer jiffies based. Uses the same clocksource 9 * -sched_clock( ) no longer jiffies based. Uses the same clocksource
10 * as gtod 10 * as gtod
11 * 11 *
12 * Rajeshwarr/Vineetg: Mar 2008 12 * Rajeshwarr/Vineetg: Mar 2008
13 * -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code) 13 * -Implemented CONFIG_GENERIC_TIME (rather deleted arch specific code)
14 * for arch independent gettimeofday() 14 * for arch independent gettimeofday()
15 * -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers 15 * -Implemented CONFIG_GENERIC_CLOCKEVENTS as base for hrtimers
16 * 16 *
17 * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c 17 * Vineetg: Mar 2008: Forked off from time.c which now is time-jiff.c
18 */ 18 */
19 19
20 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1 20 /* ARC700 has two 32bit independent prog Timers: TIMER0 and TIMER1
21 * Each can programmed to go from @count to @limit and optionally 21 * Each can programmed to go from @count to @limit and optionally
22 * interrupt when that happens. 22 * interrupt when that happens.
23 * A write to Control Register clears the Interrupt 23 * A write to Control Register clears the Interrupt
24 * 24 *
25 * We've designated TIMER0 for events (clockevents) 25 * We've designated TIMER0 for events (clockevents)
26 * while TIMER1 for free running (clocksource) 26 * while TIMER1 for free running (clocksource)
27 * 27 *
28 * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1 28 * Newer ARC700 cores have 64bit clk fetching RTSC insn, preferred over TIMER1
29 */ 29 */
30 30
31 #include <linux/spinlock.h> 31 #include <linux/spinlock.h>
32 #include <linux/interrupt.h> 32 #include <linux/interrupt.h>
33 #include <linux/module.h> 33 #include <linux/module.h>
34 #include <linux/sched.h> 34 #include <linux/sched.h>
35 #include <linux/kernel.h> 35 #include <linux/kernel.h>
36 #include <linux/time.h> 36 #include <linux/time.h>
37 #include <linux/init.h> 37 #include <linux/init.h>
38 #include <linux/timex.h> 38 #include <linux/timex.h>
39 #include <linux/profile.h> 39 #include <linux/profile.h>
40 #include <linux/clocksource.h> 40 #include <linux/clocksource.h>
41 #include <linux/clockchips.h> 41 #include <linux/clockchips.h>
42 #include <asm/irq.h> 42 #include <asm/irq.h>
43 #include <asm/arcregs.h> 43 #include <asm/arcregs.h>
44 #include <asm/clk.h> 44 #include <asm/clk.h>
45 #include <asm/mach_desc.h> 45 #include <asm/mach_desc.h>
46 46
47 /* Timer related Aux registers */ 47 /* Timer related Aux registers */
48 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ 48 #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
49 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ 49 #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
50 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ 50 #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
51 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ 51 #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
52 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ 52 #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
53 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ 53 #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
54 54
55 #define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */ 55 #define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
56 #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ 56 #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
57 57
58 #define ARC_TIMER_MAX 0xFFFFFFFF 58 #define ARC_TIMER_MAX 0xFFFFFFFF
59 59
60 /********** Clock Source Device *********/ 60 /********** Clock Source Device *********/
61 61
62 #ifdef CONFIG_ARC_HAS_RTSC 62 #ifdef CONFIG_ARC_HAS_RTSC
63 63
64 int arc_counter_setup(void) 64 int arc_counter_setup(void)
65 { 65 {
66 /* RTSC insn taps into cpu clk, needs no setup */ 66 /*
67 67 * For SMP this needs to be 0. However Kconfig glue doesn't
68 /* For SMP, only allowed if cross-core-sync, hence usable as cs */ 68 * enable this option for SMP configs
69 */
69 return 1; 70 return 1;
70 } 71 }
71 72
72 static cycle_t arc_counter_read(struct clocksource *cs) 73 static cycle_t arc_counter_read(struct clocksource *cs)
73 { 74 {
74 unsigned long flags; 75 unsigned long flags;
75 union { 76 union {
76 #ifdef CONFIG_CPU_BIG_ENDIAN 77 #ifdef CONFIG_CPU_BIG_ENDIAN
77 struct { u32 high, low; }; 78 struct { u32 high, low; };
78 #else 79 #else
79 struct { u32 low, high; }; 80 struct { u32 low, high; };
80 #endif 81 #endif
81 cycle_t full; 82 cycle_t full;
82 } stamp; 83 } stamp;
83 84
84 flags = arch_local_irq_save(); 85 flags = arch_local_irq_save();
85 86
86 __asm__ __volatile( 87 __asm__ __volatile(
87 " .extCoreRegister tsch, 58, r, cannot_shortcut \n" 88 " .extCoreRegister tsch, 58, r, cannot_shortcut \n"
88 " rtsc %0, 0 \n" 89 " rtsc %0, 0 \n"
89 " mov %1, 0 \n" 90 " mov %1, 0 \n"
90 : "=r" (stamp.low), "=r" (stamp.high)); 91 : "=r" (stamp.low), "=r" (stamp.high));
91 92
92 arch_local_irq_restore(flags); 93 arch_local_irq_restore(flags);
93 94
94 return stamp.full; 95 return stamp.full;
95 } 96 }
96 97
97 static struct clocksource arc_counter = { 98 static struct clocksource arc_counter = {
98 .name = "ARC RTSC", 99 .name = "ARC RTSC",
99 .rating = 300, 100 .rating = 300,
100 .read = arc_counter_read, 101 .read = arc_counter_read,
101 .mask = CLOCKSOURCE_MASK(32), 102 .mask = CLOCKSOURCE_MASK(32),
102 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 103 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
103 }; 104 };
104 105
105 #else /* !CONFIG_ARC_HAS_RTSC */ 106 #else /* !CONFIG_ARC_HAS_RTSC */
106 107
107 static bool is_usable_as_clocksource(void) 108 static bool is_usable_as_clocksource(void)
108 { 109 {
109 #ifdef CONFIG_SMP 110 #ifdef CONFIG_SMP
110 return 0; 111 return 0;
111 #else 112 #else
112 return 1; 113 return 1;
113 #endif 114 #endif
114 } 115 }
115 116
116 /* 117 /*
117 * set 32bit TIMER1 to keep counting monotonically and wraparound 118 * set 32bit TIMER1 to keep counting monotonically and wraparound
118 */ 119 */
119 int arc_counter_setup(void) 120 int arc_counter_setup(void)
120 { 121 {
121 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX); 122 write_aux_reg(ARC_REG_TIMER1_LIMIT, ARC_TIMER_MAX);
122 write_aux_reg(ARC_REG_TIMER1_CNT, 0); 123 write_aux_reg(ARC_REG_TIMER1_CNT, 0);
123 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH); 124 write_aux_reg(ARC_REG_TIMER1_CTRL, TIMER_CTRL_NH);
124 125
125 return is_usable_as_clocksource(); 126 return is_usable_as_clocksource();
126 } 127 }
127 128
128 static cycle_t arc_counter_read(struct clocksource *cs) 129 static cycle_t arc_counter_read(struct clocksource *cs)
129 { 130 {
130 return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT); 131 return (cycle_t) read_aux_reg(ARC_REG_TIMER1_CNT);
131 } 132 }
132 133
133 static struct clocksource arc_counter = { 134 static struct clocksource arc_counter = {
134 .name = "ARC Timer1", 135 .name = "ARC Timer1",
135 .rating = 300, 136 .rating = 300,
136 .read = arc_counter_read, 137 .read = arc_counter_read,
137 .mask = CLOCKSOURCE_MASK(32), 138 .mask = CLOCKSOURCE_MASK(32),
138 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 139 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
139 }; 140 };
140 141
141 #endif 142 #endif
142 143
143 /********** Clock Event Device *********/ 144 /********** Clock Event Device *********/
144 145
145 /* 146 /*
146 * Arm the timer to interrupt after @limit cycles 147 * Arm the timer to interrupt after @limit cycles
147 * The distinction for oneshot/periodic is done in arc_event_timer_ack() below 148 * The distinction for oneshot/periodic is done in arc_event_timer_ack() below
148 */ 149 */
149 static void arc_timer_event_setup(unsigned int limit) 150 static void arc_timer_event_setup(unsigned int limit)
150 { 151 {
151 write_aux_reg(ARC_REG_TIMER0_LIMIT, limit); 152 write_aux_reg(ARC_REG_TIMER0_LIMIT, limit);
152 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */ 153 write_aux_reg(ARC_REG_TIMER0_CNT, 0); /* start from 0 */
153 154
154 write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH); 155 write_aux_reg(ARC_REG_TIMER0_CTRL, TIMER_CTRL_IE | TIMER_CTRL_NH);
155 } 156 }
156 157
157 /* 158 /*
158 * Acknowledge the interrupt (oneshot) and optionally re-arm it (periodic) 159 * Acknowledge the interrupt (oneshot) and optionally re-arm it (periodic)
159 * -Any write to CTRL Reg will ack the intr (NH bit: Count when not halted) 160 * -Any write to CTRL Reg will ack the intr (NH bit: Count when not halted)
160 * -Rearming is done by setting the IE bit 161 * -Rearming is done by setting the IE bit
161 * 162 *
162 * Small optimisation: Normal code would have been 163 * Small optimisation: Normal code would have been
163 * if (irq_reenable) 164 * if (irq_reenable)
164 * CTRL_REG = (IE | NH); 165 * CTRL_REG = (IE | NH);
165 * else 166 * else
166 * CTRL_REG = NH; 167 * CTRL_REG = NH;
167 * However since IE is BIT0 we can fold the branch 168 * However since IE is BIT0 we can fold the branch
168 */ 169 */
169 static void arc_timer_event_ack(unsigned int irq_reenable) 170 static void arc_timer_event_ack(unsigned int irq_reenable)
170 { 171 {
171 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH); 172 write_aux_reg(ARC_REG_TIMER0_CTRL, irq_reenable | TIMER_CTRL_NH);
172 } 173 }
173 174
174 static int arc_clkevent_set_next_event(unsigned long delta, 175 static int arc_clkevent_set_next_event(unsigned long delta,
175 struct clock_event_device *dev) 176 struct clock_event_device *dev)
176 { 177 {
177 arc_timer_event_setup(delta); 178 arc_timer_event_setup(delta);
178 return 0; 179 return 0;
179 } 180 }
180 181
181 static void arc_clkevent_set_mode(enum clock_event_mode mode, 182 static void arc_clkevent_set_mode(enum clock_event_mode mode,
182 struct clock_event_device *dev) 183 struct clock_event_device *dev)
183 { 184 {
184 switch (mode) { 185 switch (mode) {
185 case CLOCK_EVT_MODE_PERIODIC: 186 case CLOCK_EVT_MODE_PERIODIC:
186 arc_timer_event_setup(arc_get_core_freq() / HZ); 187 arc_timer_event_setup(arc_get_core_freq() / HZ);
187 break; 188 break;
188 case CLOCK_EVT_MODE_ONESHOT: 189 case CLOCK_EVT_MODE_ONESHOT:
189 break; 190 break;
190 default: 191 default:
191 break; 192 break;
192 } 193 }
193 194
194 return; 195 return;
195 } 196 }
196 197
197 static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = { 198 static DEFINE_PER_CPU(struct clock_event_device, arc_clockevent_device) = {
198 .name = "ARC Timer0", 199 .name = "ARC Timer0",
199 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, 200 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
200 .mode = CLOCK_EVT_MODE_UNUSED, 201 .mode = CLOCK_EVT_MODE_UNUSED,
201 .rating = 300, 202 .rating = 300,
202 .irq = TIMER0_IRQ, /* hardwired, no need for resources */ 203 .irq = TIMER0_IRQ, /* hardwired, no need for resources */
203 .set_next_event = arc_clkevent_set_next_event, 204 .set_next_event = arc_clkevent_set_next_event,
204 .set_mode = arc_clkevent_set_mode, 205 .set_mode = arc_clkevent_set_mode,
205 }; 206 };
206 207
207 static irqreturn_t timer_irq_handler(int irq, void *dev_id) 208 static irqreturn_t timer_irq_handler(int irq, void *dev_id)
208 { 209 {
209 struct clock_event_device *clk = this_cpu_ptr(&arc_clockevent_device); 210 struct clock_event_device *clk = this_cpu_ptr(&arc_clockevent_device);
210 211
211 arc_timer_event_ack(clk->mode == CLOCK_EVT_MODE_PERIODIC); 212 arc_timer_event_ack(clk->mode == CLOCK_EVT_MODE_PERIODIC);
212 clk->event_handler(clk); 213 clk->event_handler(clk);
213 return IRQ_HANDLED; 214 return IRQ_HANDLED;
214 } 215 }
215 216
216 static struct irqaction arc_timer_irq = { 217 static struct irqaction arc_timer_irq = {
217 .name = "Timer0 (clock-evt-dev)", 218 .name = "Timer0 (clock-evt-dev)",
218 .flags = IRQF_TIMER | IRQF_PERCPU, 219 .flags = IRQF_TIMER | IRQF_PERCPU,
219 .handler = timer_irq_handler, 220 .handler = timer_irq_handler,
220 }; 221 };
221 222
222 /* 223 /*
223 * Setup the local event timer for @cpu 224 * Setup the local event timer for @cpu
224 * N.B. weak so that some exotic ARC SoCs can completely override it 225 * N.B. weak so that some exotic ARC SoCs can completely override it
225 */ 226 */
226 void __weak arc_local_timer_setup(unsigned int cpu) 227 void __weak arc_local_timer_setup(unsigned int cpu)
227 { 228 {
228 struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu); 229 struct clock_event_device *clk = &per_cpu(arc_clockevent_device, cpu);
229 230
230 clk->cpumask = cpumask_of(cpu); 231 clk->cpumask = cpumask_of(cpu);
231 clockevents_config_and_register(clk, arc_get_core_freq(), 232 clockevents_config_and_register(clk, arc_get_core_freq(),
232 0, ARC_TIMER_MAX); 233 0, ARC_TIMER_MAX);
233 234
234 /* 235 /*
235 * setup the per-cpu timer IRQ handler - for all cpus 236 * setup the per-cpu timer IRQ handler - for all cpus
236 * For non boot CPU explicitly unmask at intc 237 * For non boot CPU explicitly unmask at intc
237 * setup_irq() -> .. -> irq_startup() already does this on boot-cpu 238 * setup_irq() -> .. -> irq_startup() already does this on boot-cpu
238 */ 239 */
239 if (!cpu) 240 if (!cpu)
240 setup_irq(TIMER0_IRQ, &arc_timer_irq); 241 setup_irq(TIMER0_IRQ, &arc_timer_irq);
241 else 242 else
242 arch_unmask_irq(TIMER0_IRQ); 243 arch_unmask_irq(TIMER0_IRQ);
243 } 244 }
244 245
245 /* 246 /*
246 * Called from start_kernel() - boot CPU only 247 * Called from start_kernel() - boot CPU only
247 * 248 *
248 * -Sets up h/w timers as applicable on boot cpu 249 * -Sets up h/w timers as applicable on boot cpu
249 * -Also sets up any global state needed for timer subsystem: 250 * -Also sets up any global state needed for timer subsystem:
250 * - for "counting" timer, registers a clocksource, usable across CPUs 251 * - for "counting" timer, registers a clocksource, usable across CPUs
251 * (provided that underlying counter h/w is synchronized across cores) 252 * (provided that underlying counter h/w is synchronized across cores)
252 * - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic) 253 * - for "event" timer, sets up TIMER0 IRQ (as that is platform agnostic)
253 */ 254 */
254 void __init time_init(void) 255 void __init time_init(void)
255 { 256 {
256 /* 257 /*
257 * sets up the timekeeping free-flowing counter which also returns 258 * sets up the timekeeping free-flowing counter which also returns
258 * whether the counter is usable as clocksource 259 * whether the counter is usable as clocksource
259 */ 260 */
260 if (arc_counter_setup()) 261 if (arc_counter_setup())
261 /* 262 /*
262 * CLK upto 4.29 GHz can be safely represented in 32 bits 263 * CLK upto 4.29 GHz can be safely represented in 32 bits
263 * because Max 32 bit number is 4,294,967,295 264 * because Max 32 bit number is 4,294,967,295
264 */ 265 */
265 clocksource_register_hz(&arc_counter, arc_get_core_freq()); 266 clocksource_register_hz(&arc_counter, arc_get_core_freq());
266 267
267 /* sets up the periodic event timer */ 268 /* sets up the periodic event timer */
268 arc_local_timer_setup(smp_processor_id()); 269 arc_local_timer_setup(smp_processor_id());
269 270
270 if (machine_desc->init_time) 271 if (machine_desc->init_time)
271 machine_desc->init_time(); 272 machine_desc->init_time();
272 } 273 }
273 274